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Digital System Design with Systemverilog

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Digital System Design with Systemverilog Digital System Design with SystemVerilog Mark Zwoli´nski October 9, 2009 DRAFT 2 DRAFT Contents Preface 19 1 Introduction 25 1.1 Modern digital design . 25 1.2 Designing with hardware description languages . 25 1.2.1 Design automation . 25 1.2.2 What is SystemVerilog? . 26 1.2.3 WhatisVHDL? ...................... 26 1.2.4 Simulation ......................... 27 1.2.5 Synthesis .......................... 27 1.2.6 Reusability ......................... 28 1.2.7 Verification ......................... 28 1.2.8 Designflow......................... 29 1.3 CMOStechnology ......................... 32 1.3.1 Logicgates ......................... 32 1.3.2 ASICsandFPGAs ..................... 33 1.4 Programmablelogic. 38 1.5 Electrical properties . 42 1.5.1 Noisemargins ....................... 42 1.5.2 Fan-out ........................... 44 Summary ................................. 45 Furtherreading .............................. 46 Exercises ................................. 46 2 Combinational logic design 47 2.1 Booleanalgebra........................... 47 2.1.1 Values............................ 47 2.1.2 Operators .......................... 47 2.1.3 Truthtables......................... 48 2.1.4 Rules of Boolean algebra . 49 2.1.5 DeMorgan’slaw ...................... 50 2.1.6 Shannon’s expansion theorem . 50 2.2 Logicgates ............................. 50 DRAFT3 4 CONTENTS 2.3 Combinational logic design . 52 2.3.1 Logic minimization . 53 2.3.2 Karnaughmaps....................... 54 2.4 Timing................................ 59 2.5 Numbercodes............................ 60 2.5.1 Integers........................... 63 2.5.2 Fixed point numbers . 63 2.5.3 Floating point numbers . 64 2.5.4 Alphanumeric characters . 64 2.5.5 Graycodes ......................... 64 2.5.6 Paritybits.......................... 65 Summary ................................. 66 Furtherreading .............................. 66 Exercises ................................. 66 3 Combinational logic 69 3.1 Modulesandfiles .......................... 69 3.2 Identifiers, spaces and comments . 70 3.3 Basicgatemodels.......................... 71 3.4 Asimplenetlist ........................... 72 3.5 Logicvalues............................. 73 3.6 Continuous assignments . 73 3.6.1 SystemVerilog operators . 74 3.7 Delays................................ 75 3.8 Parameters.............................. 77 3.9 Testbenches ............................. 78 Summary ................................. 79 Furtherreading .............................. 79 Exercises ................................. 79 4 Combinational building blocks 81 4.1 Multiplexers............................. 81 4.1.1 2to1multiplexer.. ..... ...... ..... .... 81 4.1.2 4to1multiplexer.. ..... ...... ..... .... 82 4.2 Decoders .............................. 83 4.2.1 2-4decoder......................... 83 4.2.2 Parameterizable decoder . 85 4.2.3 Seven-segment decoder . 86 4.3 Priorityencoder........................... 88 4.3.1 Don’t cares and uniqueness . 88 4.4 Adders................................ 89 4.4.1 Functional model . 89 4.4.2 Rippleadder ........................ 90 4.4.3DRAFT Tasks ............................ 91 CONTENTS 5 4.5 Paritychecker............................ 92 4.6 Three state buffers . 94 4.6.1 Multi-valued logic . 94 4.7 Testbenches for combinational blocks . 95 Summary ................................. 97 Furtherreading .............................. 97 Exercises ................................. 97 5 Sequential logic blocks 99 5.1 Latches ............................... 99 5.1.1 SRlatch........................... 99 5.1.2 Dlatch ........................... 101 5.2 Flip-flops .............................. 102 5.2.1 Edge-triggered D flip-flop . 102 5.2.2 Asynchronous set and reset . 102 5.2.3 Synchronous set and reset and clock enable . 104 5.3 JKandTflip-flops ......................... 106 5.4 Registers and shift registers . 108 5.4.1 Multiple bit register . 108 5.4.2 Shift registers . 108 5.5 Counters............................... 111 5.5.1 Binary counter . 111 5.5.2 Johnson counter . 114 5.5.3 Linear feedback shift register . 116 5.6 Memory............................... 119 5.6.1 ROM ............................ 119 5.6.2 StaticRAM......................... 120 5.6.3 SynchronousRAM . 121 5.7 Sequential multiplier . 122 5.8 Testbenches for sequential building blocks . 124 5.8.1 Clock generation . 124 5.8.2 Reset and other deterministic signals . 125 5.8.3 Checking responses . 126 Summary ................................. 128 Furtherreading .............................. 128 Exercises ................................. 128 6 Synchronous sequential design 131 6.1 Synchronous sequential systems . 131 6.2 Models of synchronous sequential systems . 132 6.2.1 Moore and Mealy machines . 132 6.2.2 State registers . 132 6.2.3 Design of a three-bit counter . 133 6.3 Algorithmic stateDRAFT machines . 135 6 CONTENTS 6.4 Synthesis from ASM charts . 140 6.4.1 Hardware implementation . 140 6.4.2 State assignment . 143 6.4.3 State minimization . 148 6.5 State machines in SystemVerilog . 153 6.5.1 Afirstexample ... ..... ...... ..... .... 153 6.5.2 A sequential parity detector . 156 6.5.3 Vending machine . 157 6.5.4 Storingdata......................... 159 6.6 Testbenches for state machines . 161 Summary ................................. 162 Furtherreading .............................. 162 Exercises ................................. 162 7 Complex sequential systems 167 7.1 Linked state machines . 167 7.2 Datapath/controller partitioning . 168 7.3 Instructions ............................. 174 7.4 A simple microprocessor . 175 7.5 Microprocessor model . 180 Summary ................................. 189 Furtherreading .............................. 189 Exercises ................................. 189 8 Writing testbenches 191 8.1 Basic testbenches . 192 8.1.1 Clock generation . 192 8.1.2 Reset and other deterministic signals . 193 8.1.3 Monitoring responses . 193 8.1.4 Dumping responses . 193 8.1.5 Test vectors from a file . 194 8.2 Testbench structure . 194 8.2.1 Programs .......................... 196 8.3 Constrained random stimulus generation . 197 8.3.1 Object-oriented programming . 198 8.3.2 Randomization . 199 8.4 Assertion-based verification . 201 Summary ................................. 205 Furtherreading .............................. 206 ExercisesDRAFT ................................. 206 CONTENTS 7 9 SystemVerilog simulation 209 9.1 Event-driven simulation . 209 9.2 SystemVerilog simulation . 213 9.3 Races ................................ 215 9.3.1 Avoiding races . 216 9.4 Delaymodels ............................ 217 9.5 Simulatortools ........................... 218 Summary ................................. 219 Furtherreading .............................. 220 Exercises ................................. 220 10 SystemVerilog synthesis 223 10.1 RTLsynthesis............................ 225 10.1.1 Non-synthesizable SystemVerilog . 225 10.1.2 Inferred flip-flops and latches . 226 10.1.3 Combinational logic . 230 10.1.4 Summary of RTL synthesis rules . 234 10.2 Constraints ............................. 234 10.2.1 Attributes ... ..... ...... ..... ...... 235 10.2.2 Area and structural constraints . 236 10.2.3 full case and parallel case attributes . 238 10.3 SynthesisforFPGAs . 239 10.4 Behavioral synthesis . 242 10.5 Verifying synthesis results . 247 10.5.1 Timing simulation . 250 Summary ................................. 251 Furtherreading .............................. 252 Exercises ................................. 252 11 Testing digital systems 255 11.1 The need for testing . 255 11.2 Faultmodels............................. 256 11.2.1 Single-stuck fault model . 257 11.2.2 PLAfaults ......................... 257 11.3 Fault-oriented test pattern generation . 258 11.3.1 Sensitive path algorithm . 259 11.3.2 Undetectable faults . 260 11.3.3 The D algorithm . 261 11.3.4 PODEM .......................... 264 11.3.5 Fault collapsing . 265 11.4 Fault simulation . 265 11.4.1 Parallel fault simulation . 267 11.4.2 Concurrent fault simulation . 268 Summary .................................DRAFT 269 8 CONTENTS Furtherreading .............................. 269 Exercises ................................. 269 12 Design for testability 275 12.1 Ad hoc testability improvements . 276 12.2 Structured design for test . 276 12.3 Built-in self-test . 279 12.3.1 Example .......................... 281 12.3.2 Built-in logic block observation (BILBO) . 285 12.4 Boundary scan (IEEE 1149.1) . 288 Summary ................................. 295 Furtherreading .............................. 296 Exercises ................................. 296 13 Asynchronous sequential design 299 13.1 Asynchronous circuits . 299 13.2 Analysis of asynchronous circuits . 302 13.2.1 Informal analysis . 302 13.2.2 Formal analysis . 304 13.3 Design of asynchronous circuits . 306 13.4 Asynchronous state machines . 315 13.5 Setup and hold times and metastability . 319 13.5.1 The fundamental mode restriction and synchronous circuits 319 13.5.2 SystemVerilog modeling of setup and hold time violations 320 13.5.3 Metastability . 322 Summary ................................. 323 Furtherreading .............................. 324 Exercises ................................. 324 14 Interfacing with the analog world 327 14.1 Digital to analog converters . 327 14.2 Analog to digital converters . 329 14.3 Verilog-AMS ............................ 332 14.3.1 Verilog-AMS fundamentals . 332 14.3.2 Contribution statements . 334 14.3.3 Mixed-signal modeling . 336 14.4 Phased-locked loops
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