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Development of a Programmable Array Logic i DEVELOPMENT OF A PROGRAMMABLE ARRAY LOGIC PROGRAMMER USING A HOME COMPUTER by GERT DANIEL JORDAAN Dissertation submitted in compliance with the requirements for the MASTER'S DIPLOMA in TECHNOLOGY in the Department of Electronics at the TECHNIKON O. F . S . OCTOBER, 1988. Supervisor: Prof. F.W. Bruwer Co-supervisor: Mr. B. de Witt © Central University of Technology, Free State ACKNOWLEDGEMENTS I would like to thank the following persons without whose help this project could hardly have been completed: The supervisor, prof. F.W. Bruwer, and co-supervisor, mr. 8. de Witt, for help and guidance during the course of the project. Mr. H.F. Coetzer for technical as well as philolog ical assistance. It is really appreciated that time could be found in his very full schedule, for this assistance. Dr. C.A.J. van Rensburg for his per_onal interest in the research project and for continuous encouragement and help. Dr. J. van der Mer-we for his assistance - in particular with respect to the registration and other administrative aspects of the project. / Miss M. du Toit who was largely responsible for the word processing. For the guidance provided by my parents and the opportuni- ties which they afforded me. My children, Tania, Johan, Madelie and Lourens,. whose main contribution was to have to forego much of my attention and time for such a long period. Last, but not least, my wife, Christa, for her encouragement and understanding. © Central University of Technology,ii Free State CONTENTS PAGE Cilapter 1 1 Intr--oduc tion 1.1 Recent Trends in Electronics 1 1.2 Problem Investigated 1 1.3 Development of PAL Programmer 3 1.3.1 Generation of Fuse Map 3 1.3.2 Programming of Programmable Array Logic 3 Devices 1 . 3 . 2 . 1 Programming Software 4 1.3.2.2 Programmer Hardware 4 1.4 Evaluation of ProQrammer 4 1.5 Importance of Research Project Chaptel- 2 7 PALs as Programmable Logic Devices 2.1 Programmable Read Only Memory 8 2.2 Programmable Logic AI-ray lIZ) 2.3 Progra.mmable Array Logic 11 2.4 PLD Technology 14 2.5 Programming of PLDs 15 2.6 Summary 16 Chapter 3 17 Program Constraints, Style and Testing 3.1 Constraints 17 3.1.1 Finances 17 3.1.2 Hardware 17 © Central University1 1 of i Technology, Free State 3.1.3 Language 18 3.2 Program Goals 18 3.2.1 Reliability 18 3.2.2 Efficiency 19 3.2.3 GE.'nera Ii ty and Ease of Use 20 3.3 Structured P,'ogramming 21 3.4 Modular Programming 22 3.5 Program Testing 23 3.6 Program Documentation 26 Chapter 4 28 Fuse Map Generating Software 4.1 PAL File 28 4.2 Testing PAL Fi Ie 30 4.3 Fuse Map 20 30 4.3.1 PAL, Circuit and Pin Variables 35 Defined 4.3.2 Input and Conversion of Boolean 36 Expressions 4.3.3 Don't Care Fuses 38 4.3.4 Phantom Fuses 40 4.3.5 Display of Fuse Map 41 4.3.6 Save Fuse Map 44 4.3.7 Printing Fuse Map 46 4.4 Summary 46 Chapter 5 47 Programming Software 5.1 Port Extens10n 47 5.2 Memory Management 49 © Central University of Technology,1V Free State 5.3 Addressing Modes 49 5.4 Program PA L - Main Program 50 5.5 Ports and Power Supply 52 5.6 Pre-verification of PAL 52 5.6.1 Addressing of Input Lines 55 5.6.2 Addressing of Product Lines 57 5.6.3 Verification of Fuse Condition 59 5.7 Programming of PAL 60 5.7.1 Addressing of Input Lines 60 5.7.2 Addressing of Product Lines and 63 Adj us ting LR 5.7.3 Control of Output Disable and Clock 63 Pins 5.7.4 Programming of Fuses 65 5.8 Verification of Programmed PAL 66 5.9 Security Fuses 71 5.10 Summary 72 Chapter 6 73 PAL Programmer Hardware 6.1 810ck Diagram 73 6.1.1 Peripheral Interface Adapters 73 6.1.2 Voltage Select 1 to 5 75 6.2 Power Supply 76 6.2.1 Transformer, Rectifier and Filter 76 6.2.2 VDD/VH 77 6.2.3 VHH/VP 77 6.2.4 PAL Supply Voltage 78 6.3 Output Disable (OD) and Clock Pins 78 6.4 Input Lines (Voltage Select 2) 80 © Central University of Technology,v Free State 6.5 Product Lines and L/R Pin (pins 12 -19) 81 6.5.1 Multiplexers 82 6 . 5.2 Level Shif t er 82 6.6 Programmer Construction 83 6.7 Summary 83 Chapter 7 85 Evaluation of Programmer 7 .1 Full Adder 86 7.2 Decade Counter 87 7.3 Summary 9 1 Chapter 8 95 Summary APPENDIX A - PAL File 98 APPENDIX B - Test PAL File 99 APPENDIX C - Fuse Map 20 100 APPENDIX D Program PAL - Main Program 103 APPENDIX E - Program Fuse - Machine Code Routine 108 APPENDIX F - Circuit Diagram of Programmer 112 REFERENCES 120 © Central University of Technology, Free State LIST OF FIGURES PAGE Chapter 2 Fig . 2.1 Blockdiagram of a PLD. 9 Chapter 4 Fig. 4.1 Flowchart of PAL File . 31 Fig. 4.2 Flowchart of Testing PAL File. 32 Fig. 4.3 Flowchart of Fuse Map 20. 34 Fig. 4.4 F I owc hart of Input pin con version. 39 Fig . 4.5 Flowchart of Input line modification. 42 Fig. 4.6 Flowchart of Product line modification. 43 Fig . 4.7 Flowchart of printing of fuse map. 45 Chapter 5 Fig . 5.1 Program PAL - Subroutines overlay. 48 Fig. 5.2 Flowchart - Programming software. 51 Fig. 5 . 3 Flowchart of pre-verify. 54 Fig. 5.4 Flowchart - Add r essing o f Input Lines 56 (BASIC) . Fig . 5.5 Addressing of product lines 0 to 31 58 (BAS I C) . Fig . 5.6 Verify fuse as not blown. 59 F ig . 5.7 Flowchart of program routine . 61 Fig . 5.8 Flowchart of Addressing of input lines 62 (machine c ode ) . Fig. 5.9 Addressing product lines and adjusting 64 LR (machine code). Fig. 5.10 Control of OD and CLK pin s. 65 Fig. 5.11 Program fuse. 67 © Central University of \1Technology, i i Free State Fig. 5.12 Programming waveforms . 67 Fig. 5.13 Address fuse for reprogramming during 70 verification .. Fig. 5.14 Reprogram fuse duri ng verification . 71 Chapter 6 Fig. 6.1 Block diag ram of PAL programmer . 74 F i g. 6.2 Circuit diagram of DD/CLK pins (no's 1 79 and 11). Fig . 6.3 Control of input lines (pins 2 to 9). 8 1 Fig. 6.4 Control of product lines and L /R p,n 82 ( pin s 12 to 19). Chapter 7 Fig. 7.1 Hard copy of full adder fuse map. 88 Fig. 7.2 Karnaugh maps - decade counter. 91 Fig. 7.3 Hard copy of decade counter fuse map. 92 © Central University of vTechnology, 1 1 ; Free State CHAPTER 1 INTRODUCTION 1.1 Recent Trends In Electronics development of programmable logic devices was a lOQical step in the onQoing pl~ocess of increasing the integra t Ion o f electronic circui.try by which the component cou nt of elec- tronic syste1ns is decreased . The u se of such programmable logic devices offers the following advantages : 1) Design cycles of s ystems are drastically reduced. 2) P r oduction costs are reduced . 3) I nventory levels of chips a re reduced . 4 ) Proprietary des i gns and s ignatures Wllich cannot copied by com p e t itors A Levy, April, 1986: 33). The programmab le integrated circuits are mass-produced, but small numbers of LI1esc can be progr-am(n ed to the spec iali zed functions req u ired . Thl5 Inay prove to be a nlore economic solution than ttle developm~nt of customlsed inte- grated if fairl y snla ], l numbers of these ChlPS are required. 1.2 Problem Investlgated The main aim of this project is to inves tigate the p r ogranl- ming princi p les and characteristi c s of programmable array logic devices, comnlonly re1er red to as PALs (although PAL is © Central University of Technology, Free State a registered trademark of Monolithic Memories, it i s used to describe any device within this family originating f r om any source) , and to deve lop a relatively inexpensive PAL pro- grammer that can be used in conjunction with a personal computer. The only computer available for experimental use at the time of initiation o f the project was a Commodore 64. For this reason it was decided to develop the programmer aroun d the Commodore. It i s appreciated that a computer such as the IBM PC, or a compatible, would have been much more suitable for this purpose. However, the Commodore proved to be qui t e up to the task with the only real problem being the slow execu- tion speed of some of the programs written in BASIC . While this may have bc~n unacceptable in a commercial mode 1 , it did not have any real bearing on the attainment of the goal of the project. The programmer is capable of programming the majority of 20 pin programmable array logic devices, currently manufac- tured by Monolithic Memories and National Semiconductor. The design was limited to 20 p i n chips but the same principles aroe valid for 24 pin devices . Incorporation of 24 pin de- vices in the project would only have resulted in the paral ­ leI development of two very similar sets of software, with- out r eally contributing towards the scope of the project.
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