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PROGRAMMABLE ARRAY LOGIC the PAL Device Is a Special Case of PLA Which Has a Programmable and Array and a Fixed OR Array

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PROGRAMMABLE ARRAY LOGIC the PAL Device Is a Special Case of PLA Which Has a Programmable and Array and a Fixed OR Array PROGRAMMABLE ARRAY LOGIC The PAL device is a special case of PLA which has a programmable AND array and a fixed OR array. The basic structure of Rom is same as PLA. It is cheap compared to PLA as only the AND array is programmable. It is also easy to program a PAL compared to PLA as only AND must be programmed. The figure 1 below shows a segment of an unprogrammed PAL. The input buffer with non inverted and inverted outputs is used, since each PAL must drive many AND Gates inputs. When the PAL is programmed, the fusible links (F1, F2, F3…F8) are selectively blown to leave the desired connections to the AND Gate inputs. Connections to the AND Gate inputs in a PAL are represented by Xs , as shown here: Figure 1: segment of an unprogrammed and programmed PAL. As an example, we will use the PAL segment of figure 1 to realize the function I1I2’+I 1I2. the Xs indicate that the I 1 and I 2’ lines are connected to the first AND Gate, and the I 1’ and I 2 lines are connected to the other Gate. Typical combinational PAL have 10 to 20 inputs and from 2 to 10 outputs with 2 to 8 AND gates driving each OR gate. PALs are also available which contain D flip-flops with inputs driven from the programming array logic. Such PAL provides a convenient way of realizing sequential networks. Figure 2 below shows a segment of a sequential PAL. The D flip-flop is driven from the OR gate, which is fed by two AND gates. The flip-flop output is fed back to the programmable AND array through a buffer. Thus the AND gate inputs can be connected to A, A’, B, B’, Q, or Q’. The Xs on the diagram show the realization of the next-state equation. Q+ = D = A’BQ’ + AB’Q The flip-flop output is connected to an inverting tristate buffer, which is enabled when EN = 1 Figure 2 Segment of a Sequential PAL Figure 3 below shows a logic diagram for a typical sequential PAL, the 16R4. This PAL has an AND gate array with 16 input variables, and it has 4 D flip-flops. Each flip-flop output goes through a tristate-inverting buffer (output pins 14-17). One input (pin 11) is used to enable these buffers. The rising edge of a common clock (pin 1) causes the flip-flops to change the state. Each D flip-flop input is driven from an OR gate, and each OR gate is fed from 8 AND gates. The AND gate inputs can come from the external PAL inputs (pins2-9) or from the flip-flop outputs, which are fed back internally. In addition there are four input/output (i/o) terminals (pins 12,13,18 and 19), which can be used as either network outputs or as inputs to the AND gates. Thus each AND gate can have a maximum of 16 inputs (8 external inputs, 4 inputs fed back from the flip-flop outputs, and 4 inputs from the i/o terminals). When used as an output, each I/O terminal is driven from an inverting tristate buffer. Each of these buffers is fed from an OR gate and each OR gate is fed from 7 AND gates. An eighth AND gate is used to enable the buffer. Figure 3: logic diagram for 16R4 pal When the 16R4 PAL is used to realize a sequential network, the I/O terminals are normally used for the z outputs. Thus, a single 16R4 with no additional logic could realize a sequential network with up to 8 inputs, 4 outputs, and 16 states. Each next state equation could contain up to 8 terms, and each output equation could contain up to 7 terms. As an example, we will realize the BCD to Excess-3 code converter using three flip-flops to store Q1,Q2 and Q3, and the array logic that drives these flip-flops is programmed to realize D1, D2 and D3, as shown in figure 3 .The Xs on the diagram indicate the connections to the AND-gate inputs. An X inside an AND gate indicates that the gate is not used. For D3, three AND gates are used, and the function realized is D3 = Q1Q2Q3 + X’Q1Q3’ + XQ1’Q2’ The flip-flop outputs are not used externally, so the output buffers are disabled. Since the Z output comes through the inverting buffer, the array logic must realize Z’ = (X + Q3)(X’ + Q3’) = XQ3’ + X’Q3 The z output buffer is permanently enabled in this example, so there are no connections to the AND gate that drives the enable input, in which case the AND gate output is logic1. When designing with PALS, we must simplify our logic equations and try to fit them in one or more PALs. Unlike the more general PLA, the AND terms cannot be shared among two or more OR gates; therefore, each function to be realized can be simplified by itself without regard to common terms. For a given type of PAL the number of AND terms that feed each output OR gate is fixed and limited. If the number of AND terms in a simplified function is too large, we may be forced to choose a PAL with more OR-gate inputs and fewer outputs. Computer aided design programs for PAL s are widely available. Such programs accept logic equations, truth tables, state graphs, or state tables as inputs and automatically generate the required fused patterns. These patterns can then be downloaded into a PLD programmer, which will blow the required, fuses and verify the operation of the PAL. Other sequential programmable logic devices (PLDs) The 16R4 is an example of a simple sequential PLD. As the integrated technology has improved, a wide variety of other PLDs have become available. Some of these are based on extensions of PAL concept, and others have based on gate arrays. The 22CEV10 is a CMOS electrically erasable PLD that can be used to realize both combinational and sequential networks. • It has 12 dedicated input pins and 10 pins that can be programmed as either inputs or outputs. • It contains 10 d flip-flops and 10 OR gates. • The number of AND gates that feed each OR gate ranges from 8 to 16. • Each OR gate drives an output logic macrocell. • Each macrocell contains one of the 10 D flip-flops. • The flip-flops have the common clock, a common asynchronous reset (AR) input and a common synchronous preset (SP) input. Similarly, 22V10 indicates a versatile PAL with a total of 22 input and output pins, 10 of which are bi-directional I/O (input/output) pins. Figure 4: block diagram for 22CEV10 Figure 4 shows the details of a 22CEV10 output macrocell. The connections to the output pins are controlled by programming the macrocell. The output mux controls inputs S1 and S0 select one of the data inputs. For example, S1S0 = 10 selects data input 2. Each macrocell has two programmable interconnect bits. S1 or S0 is connected to ground (logic 0) when the corresponding bit is programmed. Erasing a bit disconnects the control line (S1 or S0) from ground and allows it to float to Vcc (logic 1). When S1 = 1, the flip flop is bypassed, and the output is from the OR gate. The OR gate output is connected to the I/O pin through the multiplexer and the output buffer. The OR gate is also fed back so that it can be used as an input to the AND gate array. If S1 = 0, then the flip-flop output is connected to the output pin, and it is also fed back so that it can be used for AND gate inputs. when S0 = 1, the output is not inverted, so it is active high. When S0 = 0 ,the output is inverted, so it is active low. The output pin is driven from the tristate-inverting buffer. When the buffer output is in the high impedance state, the OR gates and the flip-flops are disconnected from the output pin, and the pin can be used as input. The dashed lines on figure 5 show the path when both S0 and S1 are 1. Note that in the first case the flip flop Q output is inverted by the output buffer, and in the second case the OR gate output is inverted twice so there is no net inversion. Figure 5: internal diagram of macro cell of 22CEV10 Design a sequential traffic-light controller using 22v10 Traffic light controller Consider the design of a sequential traffic-light controller for the intersection of “A” street and “B” street. Features of the traffic-light controller Each street has traffic sensors, which detect the presence of vehicles approaching or stopped at the intersection. Sa =1 means a vehicle is approaching on “A” street, and Sb=1 means a vehicle is approaching on “B” street. “A” street is a main street and has a green light until the car approaches on “B”. Then the light changes and “B” has a green light. At the end of 50 seconds, the light changes back unless there is a car on “B ” street and none on “A”, in which case the “B” cycle is extended to another 10 more seconds. When “A” is green, it remains green at least 60 seconds, and then the lights change only when the car approaches on “B”. Figure 6 shows the external connections to the controller.
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