ECL PAL10/10016PE8-3 are in the correct state as defined by the equation for that for equation the by defined fuses) as intact state (via it correct to the in are connected are which inputs array all com­ 16 of total a has array logic 0/10016PE8-3 PALI The totyping and design iterations can be performed quickly us­ quickly performed be can iterations design pro­ and System as totyping functions. logic Boolean custom sum-of-products implement convenient can designer system the tions, A 10 6 E -3 V C V 3 - 8 PE 16 100 PAL Information Ordering prod­ PAL ECL prior all of those with this compatible of is algorithm device programming and format fuse-map JEDEC conventional for replacements highest- user-programmable the provide speed to technology fuse newly a tungsten with developed process Technology) Coupled Emitter Poly gle device This family. PAL® ECL speed high Semi­ 28-pin National the of conductor member a is PAL10/10016PE8-3 The sum of 8 product terms. Each product term is satisifed when when satisifed is term product Each terms. product OR- 8 of is the sum function output Each functions. output programma­ 8 polarity and ble terms product 64 pairs, input plementary ing these off-the shelf products. shelf off-the these ing connec­ gate AND/OR configure to links fuse programming includ­ functions, specific applications— of variety a wide for csfo National. from ucts The reduction. chip-count significant with logic SSI-MSI ECL Sin­ (Advanced ASPECT Semiconductor’s National utilizes ing random logic, custom decoders, state machines, etc. By etc. machines, state decoders, custom logic, random ing Description General Programmable logic devices provide convenient solutions solutions convenient provide devices logic Programmable 3 ns ECL ASPECT™ Programmable Array Logic Array Programmable ASPECT™ ECL ns3 Only) (PLCC 0/10016PE8-3 PALI ------ELIOCompatibility: I/O ------ECL ------Semiconductor National National ------pe eso: st o tp ns 3 = 3 - Version: ------Speed ------— Temperature Range: Temperature — Packaging: V = 28-Pin PLCC 28-Pin = V Packaging: Outputs of Number Type: Output Inputs Array of Number Family Logic Array Programmable Note: Note: = Commercial: = C PE = Expanded Programmable Programmable Expanded = PE 100 = ECL 100K ECL = 100 10 = ECL10KH ECL10KH = 10 0°Cto + 85°Cfor 100K 85°Cfor H + K 0°Cto for10 °C 5 7 + 0°Cto datasheet For DIP seePAL1O/1OO16P0-3 only) Polarity (No l/O Pins/PLC C C Pins/PLC l/O (No Polarity 2-242 Pormal elcmn o EL logics ECL for replacement Programmable ■ Hg dniyhg promne 8pn LC package PLCC 28-pin performance software density-high industrial High other and ■ PLAN by supported Fully copying direct ■ prevent to fuse polarity Security programmable ■ with versions functions output compatible Eight I/O ■ KH 10 and 100K Both ■ used) pins (all function 28-pin max Full ns 3 ■ tpp speed: High ■ fuse) when the equation defining that output is satisfied. satisfied. is output that defining equation the when fuse) curity fuse may be programmed to prevent direct copying of of copying direct prevent to programmed be may fuse curity After programmers. PLD TTL conventional standard dustry accomplished is Programming easy. and quick velopment (by high logic a either produce to independently output each proprietary logic designs. logic proprietary se­ additional an array, logic the verifying and in­ programming by supported therefore is and levels voltage TTL using de­ design PAL make software and equipment Programming the programming (by low logic a or intact) fuse the leaving configure to designer output the with permit fuses provided These is fuses. polarity function output Each term. product Features Block Diagram Block mi y r a in im l e r p ECL PALI 0/10016PE8-3 Absolute Maximum Ratings If Military/Aerospace specified devices are required, Output Current -50 mA please contact the Sales Lead Temperature Office/Distributors for availability and specifications. (Soldering, 10 Seconds) TBD Temperature under Bias - 55°C to + 1 25°C ESD Tolerance Storage Temperature Range - 65°C to + 1 50°C Czap = 100 pF Vee Relative to Vcc - 7V to + 0.5V Rzap = 1500ft Test Method: Human Body Model Input Voltage Vee to + 0.5V Test Specification: NSC SOP-5028 Recommended Operating Conditions

Symbol Parameter Min Typ Max Units Supply Voltage 10KH -5 .4 6 -5 .2 -4 .9 4 Vee V 100K -4 .8 0 -4 .5 -4 .2 0 T Operating Temperature (Note) 10KH 0 + 75 °c 100K 0 + 85

Electrical Characteristics Over Recommended Operating Conditions Output Load = 50ft to —2.0V

Symbol Parameter Conditions Ta Min Max Units V|H High Level Input Voltage Guaranteed Input Voltage 0°C -1 1 7 0 -8 4 0 10KH High for All Outputs + 25°C -1 1 3 0 -8 1 0 mV + 75°C -1 1 7 0 -7 3 5 100K 0°Cto +85°C -1 1 6 5 -8 8 0

V|L Low Level Input Voltage Guaranteed Input Voltage 0°C -1 9 5 0 -1 4 8 0 Low for All Inputs 10KH + 25°C -1 9 5 0 -1 4 8 0 mV + 75°C -1 9 5 0 -1 4 5 0 100K 0°C to +85°C -1 8 1 0 -1 4 7 5

VOH High Level Output Voltage Vin = V|h Max or Vil Min 0°C -1 0 2 0 -8 4 0 10KH + 25°C -9 8 0 -8 1 0 mV + 75°C -9 2 0 -7 3 5

100K 0°Cto +85°C -1 0 2 5 -8 8 0 v OL Low Level Output Voltage V|n = V|h Max or V il Min 0°C -1 9 5 0 -1 6 3 0 10KH + 25°C -1 9 5 0 -1 6 3 0 mV + 75°C -1 9 5 0 -1 6 0 0 100K 0°C to + 85°C -1 8 1 0 -1 6 2 0 l|H High Level Input Current V|N = V|H Max 0°C 10KH + 75°C 220 J*V 100K 0°C to +85°C l|L Low Level Input Current Vin = V|H Min 0°C 10KH + 75°C 0.5 JLlV

100K 0°Cto +85°C

Supply Current Vee = Min 10KH 0°C to + 75°C Iee -2 2 0 mA All Inputs and Outputs Open 100K 0°C to + 85°C

Note: Operating temperatures for circuits in PL.CC packages are specified as ambient temperatures 0 a) with circuits in a test socket or mounted on a and transverse air flow greater than 500 linear fpm is maintained.

2-243 ECL PAL10/10016PE8-3 10 kH 10 kH 10 kH 100k Test Load Test Timing Measurements Timing rt a P Characteristics Switching oe 1: Note , -2.0V to 50ft R[_ = load: Output Conditions, Operating Recommended Over tpD Symbol Threshold V| V All AC Measurements are to be made from Threshold Point.Threshold made from be MeasurementsAC areto All ih l p m e T = Threshold - 400 mV 400 - Threshold = = Threshold + 400 mV 400 + Threshold = 75°C 25°C All 0°C ------Hi + VILMax V + 'HMin V -1165 -1070 ln M 'N V -1130 -1170 Dout Output Rise Time Rise Output Output Fall Time Fall Output Input to Output to Input ■THRESHOLD 2V — VO -2 Parameter LMax |L V -1450 -1475 -1480 -1480 3 ( HEHL OUTPUT THRESHOLD ld o h s e r h T -1300 -1260 -1300 -1325 L/ -3 2 1 7 0 /1 /L L T INPUT L/ -2 2 1 7 0 /1 /L L T 20% and 80% Points 80% and 20% Measured between between Measured 1) (Note Points Threshold at Measured Measured Test Conditions Test Measured 900 0 -9 -860 -900 -925 ,H V 2-244 -1700 -1660 -1700 -1725 ,L V Connection Diagram Connection Order Number PAL1016PE8-3/PAL10016PE8-3 Number Order 7] 0 0 0 n [ * o pn I To] 1 C ] T ) IT See NS Package Number V28A Number NSSee Package l HI E LULUlill 5 pF to GND to pF 5 I I I I I I r r V I I I I vcc I I I I 0.25 0.25 Min Top View Top PLCC 1 1.25 Max 1.25 3.0 (24 [20 Hi 25 ] 0 0 0 I 0 vcco L/ -4 2 1 7 0 /1 /L L T Units

ECL PAL10/10016PE8-3 Functional Testing Programming As with all field-programmable devices, the user of the ECL Most programmers listed below are able to directly program PAL devices provides the final manufacturing step. While the 28-lead PLCC package. If programming from a DIP National’s PAL devices undergo extensive testing when socket the following adapter wiring is required: they are manufactured, their logic function can be fully test­ PLCC Pin DIP Pin ed only after they have been programmed to the user’s pat­ tern. 1 No Connect 2 1 To ensure that the programmed PAL devices will operate properly in your system, National Semiconductor (along with 3 2 most other manufacturers of PAL devices) strongly recom­ 4 3 mends that devices be functionally tested before being in­ 5 4 stalled in your system. Even though the number of postpro­ 6 5 gramming functional failures is small, testing the logic func­ 7 6 tion of the PAL devices before they reach system assembly 8 7 will save board debugging and rework costs. For more infor­ g 8 mation about the functional testing of PAL devices, please 10 No Connect refer to National Semiconductor’s Application Note #351 and the Programmable Logic Design Guide. 11 9 12 10 Design Development Support 13 11 A variety of software tools and programming hardware is 14 12 available to support the development of designs using PAL 15 No Connect products. Typical software packages accept Boolean logic 16 13 equations to define desired functions. Most are available to 17 14 run on personal and generate JEDEC-compati- 18 15 ble “ fuse maps” . The industry-standard JEDEC format en­ 19 16 sures that the resulting fuse-map files can be downloaded 20 No Connect into a large variety of programming equipment. Many soft­ 21 17 ware packages and programming units support a large vari­ 22 18 ety of programmable logic products as well. The PLAN soft­ ware package from National Semiconductor supports all 23 19 programmable logic products available from National and is 24 20 fully JEDEC-compatible. PLAN software also provides auto­ 25 21 matic device selection based on the designer’s Boolean 26 22 logic equations. 27 23 A detailed logic diagram showing all JEDEC fuse-map ad­ 28 24 dresses for the PALI 0/10016PE8-3 is provided for direct map editing and diagnostic purposes. For a list of current PLCC pins 1, 10, 15 and 20 are not connected to the DIP software and programming support tools available for these pins because these are the additional ECL inputs. If using devices, please contact your local National Semiconductor such an adaptor, a 0.1 p.F capacitor should be added from sales representative or distributor. If detailed specifications PLCC pin 23 to PLCC pin 14. of the ECL PAL programming algorithm are needed, please contact the National Semiconductor Programmable Device Support Department. Support Advin Systems Sailor PAL V8.40 Data I/O Unisite 40 V2.7 International Microsystems ECL-2, ECL-1 Logical Devices Allpro V1.48C Palpro 2X V4.0 Stag Microsystems ZL30A V31

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