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COMBINATIONAL CIRCUITS Combinational Plds Basic Configuration of Three Plds (Programmable Logic Devices)

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COMBINATIONAL CIRCUITS Combinational Plds Basic Configuration of Three Plds (Programmable Logic Devices) COMBINATIONAL CIRCUITS Combinational PLDs Basic Configuration of three PLDs (Programmable Logic Devices) Boolean variables Fixed Programmable INPUTS AND array OUTPUTS OR array (decoder) Programmable Read-Only Memory (PROM) Programmable INPUTS Fixed OUTPUTS AND array OR array Programmable Array Logic (PAL) Programmable INPUTS Programmable AND array OR array OUTPUTS (Field) Programmable Logic Array (PLA) 1 ©Loberg COMBINATIONAL CIRCUITS Combinational PLDs Two-level AND-OR Arrays (Programmable Logic Devices) F (C,B, A) = CBA + CB A A AND B + V B C A C B F C F AND F + V 1 B OR C Multiple functions Simplified equivalent circuit for two-level AND-OR array 2 ©Loberg COMBINATIONAL CIRCUITS Combinational PLDs Field-programmable AND and OR Arrays (Programmable Logic Devices) Field-programmable logic elements are devices that contain uncommitted AND/OR arrays that are (programmed) configured by the designer. + V + V A A F (C,B, A) F (C,B, A) = CBA B B C C Unprogrammed AND array Fuse can be "blown" by passing a high current through it. 3 ©Loberg COMBINATIONAL CIRCUITS Combinational PLDs Field-programmable AND and OR Arrays (Programmable Logic Devices) F (P1 ,P2 ,P3 ) = P1 + P3 P1 P1 P2 P2 P3 P3 F F (P1 ,P2 ,P3 ) Unprogrammed OR array Programmed OR array P1 P2 P3 P1 + P3 4 ©Loberg COMBINATIONAL CIRCUITS Combinational PLDs Output Polarity Options (Programmable Logic Devices) I1 Ik Active high Active low Complementary outputs Programmable polarity P P 1 m + V 5 ©Loberg COMBINATIONAL CIRCUITS Combinational PLDs Bidirectional Pins and Feed back Lines (Programmable Logic Devices) I1 Ik Feedback IOm Three-state driver 6 ©Loberg COMBINATIONAL CIRCUITS Combinational PLDs PLA (Programmable Logic Array) (Programmable Logic Devices) If we use ROM to implement the Boolean function we will waste the silicon area. All Input combinations are implemented in ROM (address decoder). Usually we must implement only few minterms. A B ⇒ Only few OR-operators. C ⇒ A⋅ B ⋅ The standard SOP format has few A C OR operations and several input B ⋅C variables. Inverted A⋅ B ⋅C output PLA saves silicon area 0 C B A 1 = ⋅ + ⋅ + ⋅ ⋅ C B A F1 B A C A C B A F1 F2 = C ⋅ A + B ⋅C F2 7 ©Loberg COMBINATIONAL CIRCUITS Combinational PLDs PLA (Programmable Logic Array) (Programmable Logic Devices) Example (Old Signetics FPLA 82S100 Field Programmable Logic Array) 82S100 is 16X48X8 Fuse Programmable Vcc Logic Array circuit fuse I0 I1 I15 P0 P1 P47 Vcc S0 F0 S1 F1 fuse S7 F7 8 ©Loberg COMBINATIONAL CIRCUITS Combinational PLDs PLA (Programmable Logic Array) (Programmable Logic Devices) I0 Example of FPLA Device Philips PLS153A I7 I/O B9 B0 9 ©Loberg COMBINATIONAL CIRCUITS Combinational PLDs PAL (Programmable Array Logic) (Programmable Logic Devices) Fixed OR array Product term 1 F1 = A⋅ B ⋅C + A⋅ B ⋅C + D 2 F1 3 A I1 Feedback 4 5 F2 6 B I2 7 8 F3 9 C I3 10 11 F4 12 D I4 10 ©Loberg COMBINATIONAL CIRCUITS Combinational PLDs PAL (Programmable Array Logic) (Programmable Logic Devices) Example of PAL Device AMD PAL18P8 11 ©Loberg COMBINATIONAL CIRCUITS Combinational PLDs PAL (Programmable Array Logic) (Programmable Logic Devices) Combinational logic + D-flip-flops (for sequential circuit applications) One example : PEEL 22CV10A Electrically Erasable 1 of 10 Macro cells I I/O MACRO OE AND CELL array SP AC I SP Synchronous Preset Common Clock AC Asynchronous Clear OE Output Enable 12 ©Loberg COMBINATIONAL CIRCUITS Combinational PLDs PAL16R4AM (Programmable Logic Devices) 13 ©Loberg COMBINATIONAL CIRCUITS Combinational PLDs ROM implementation (Programmable Logic Devices) m m 2 × n m inputs (address Ai = 2 combinations) n outputs (data) ROM Linear, one-dimensional Word-lines memory core addressing A0 m W0 A m× 2 W Encoder 1 decoder 1 Address lines Memory Input variables matrix ROM cells Am−2 WM −2 Am−1 WM −1 m-bit address 2m = M n-bit data Data lines Dn−1 Dn−2 D1 D0 Outputs 14 ©Loberg COMBINATIONAL CIRCUITS Combinational PLDs ROM implementation (Programmable Logic Devices) Canonical SOP form of the Boolean function : Minterms Address locations A0 D0 10 Input variables 1k x 8 8 Outputs D7 A9 Select lines Output Enable lines 15 ©Loberg COMBINATIONAL CIRCUITS Combinational PLDs ROM implementation (Programmable Logic Devices) Example 13 input variables In12 - In0 ROM organized as 8Kb x 8 (8192x8bits) 8 different switching functions F7-F0 For example M27C64A UV EPROM V VCC Supply voltage +5V (10%) CC VPP 13 8 VSS Ground A12 − A0 Q0 − Q7 VPP Program Supply 12.5V +- 0.25V Direction during program M27C64A P Program P E E Chip Enable G G Output Enable − Address Inputs VSS A12 A0 Q7 − Q0 Data Outputs Logic diagram Signal Names 16 ©Loberg COMBINATIONAL CIRCUITS Combinational PLDs ROM implementation (Programmable Logic Devices) Example VCC +5V 10 11 VCC In0 A0 Q0 F0 VPP 1 28 9 12 M27C64A A12 P 8 13 NC 7 15 A7 6 16 A8 5 17 A9 4 18 A11 3 19 G In7 Q7 F7 A10 In8 25 1 VPP E In9 24 27 21 P A0 Q7 In10 Q0 In11 23 NC 26 2 20 In12 A12 E Q2 14 G 22 VSS 14 15 Q3 Implemented combinational logic Dip Connections 17 ©Loberg COMBINATIONAL CIRCUITS ROM implementation Universal Programmer UV Eraser 18 COMBINATIONAL CIRCUITS Combinational PLDs Programming Software (Programmable Logic Devices) Examples (free download) ATMEL : WinCUPL software SPLDs Simple Programmable Logic Devices (16V8, 20V8, 22V10) ATF22LV10ZQZ CPLDs Complex Programmable Logic Devices ATF15xxBE family ATV750B XILINX : Xilinx ISE Design Suite (Schematics, VHDL, Verilog) CPLDs Complex Programmable Logic Devices XC95xx family FPGAs Field Programmable Gate Arrays Virtex, Spartan,.. 19 The End 20 .
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