coverstory By Brian Dipert, Technical Editor Programmable-Programmable-

he umbrella term “logic devices” subdivides into several categories: discrete logic, simple and logiclogic Tcomplex PLDs, FPGAs, and standard- and cus- tom-cell ASICs. FPGAs, SPLDs/PALs, and CPLDs are all programmable-logic devices, although their inter- nal architecture implementations differ. Programmable-logic devices are the fastest growing segment of the logic-device family, for two funda- directorydirectory mental reasons. For one thing, their ever-increasing per-device logic-gate count “gathers up”functions that might otherwise spread over a number of discrete-log- ic and memory chips, improving end-system size, power consumption, performance, reliability, and cost. Equally important, you can in a matter of seconds or THE SECOND ANNUAL EDN PLD minutes configure and, in many cases, reconfigure these devices at your workstation or in the system-as- DIRECTORY HIGHLIGHTS THE sembly line. This capability provides powerful flexi- bility to react to last-minute design changes, to pro- ARCHITECTURES AVAILABLE FOR YOUR totype ideas before implementation, and to meet time-to-market deadlines driven by both customer NEXT DESIGN. FIND OUT WHAT’S NEW, need and competitive pressures. Programmable-logic devices lack the long lead- WHAT’S OBSOLETE, AND WHAT’S times, up-front NRE charges, minimum-order quan- tities, and inventory complexity of ASICs. As per-gate EVOLVEDEVOLVED ININ PALS,PALs, PLDS,PLDS, ANDAND FPGAFPGAS.S. cost decreases and the number of gates per component increases, programmable-logic devices are making sig- nificant inroads into gate-array-ASIC territory. Sys- AND CHECK THIS OUT: tem designers and manufacturers are only beginning WE’VE POSTED COMPREHENSIVE to explore and exploit in-system reprogrammability, either to correct errors and upgrade functions once the TABLES OF DEVICES AND FEATURES end system is in users’ hands or to use a fixed number IN THE WEB VERSION OF THIS of logic gates to implement multiple functions. This ARTICLE AT technique is known as “.” The programmable-logic industry is relatively www.ednmag.com young and highly varied. Just as companies use pro- grammable logic’s flexibility to differentiate them- selves, a number of semiconductor vendors have de- veloped unique PLDs and FPGAs to address an intersection of performance, power, integration, and cost targets. This diversity is perhaps the most com- plex challenge facing you, because, in many cases, you must deeply understand each programmable-logic ar- chitecture before you can select one that meets your needs. The market leaders are increasingly driving de- facto industry standardization, thus simplifying the se- lection task. Highly complex programmable-logic architectures rely extensively on design-automation software to pro- duce optimum results for end-system parameters. Pri- Image by Chinsoo Chung

36 edn | August 30, 2001 www.ednmag.com FPGAs

Actel ...... 38 oritizing these parameters depends on the applica- language approaches provide the additional bene- tion. Often, for example, designs targeting low pow- fit of enabling design reuse. Yet, just as with high- Agere Systems...... 38 er, high performance, or minimal gate count differ level versus assembly-language software develop- ...... 40 significantly from each other. Ideal design-automa- ment, high-level logic design decreases development ...... 42 tion software: time but produces lower performance and less effi- ● isolates you from the internal device-architec- cient gate usage. QuickLogic ...... 42 ture details, Another technique that has become more popu- Triscend...... 44 ● enables you to prioritize your design goals and lar over the last few years involves leveraging the al- ...... 44 optimizes the software’s operation based on ready-completed designs, or IP (intellectual prop- the order you choose, erty), of another company instead of designing your PALs & PLDs ● efficiently uses silicon resources, own circuits. The convergence of accelerating sili- ● requires little to no manual intervention, con gate count, increasing system functions and Altera ...... 46 ● quickly compiles and recompiles a design, and standardization, and faster time-to-market require- Atmel ...... 48 ● minimizes or eliminates timing and pinout ments is driving this approach. Perhaps the biggest changes between compilations. IP hurdles still to overcome are legal rather than ....48 The technical superiority of a programmable-log- technical, although robust test and verification ic vendor’s silicon products and the comprehen- suites and core interoperability among vendors and Technology (ICT) ...... 50 siveness of the vendor’s documentation are not the among silicon architectures are important. ...... 50 only determinants of the vendor’s success. Equally Although “pure” programmable-logic devices STMicroelectronics ...... 52 important are the depth and breadth of the com- dominate industry shipments, this fast-moving pany’s internally developed and third-party soft- product category is evolving in several intriguing di- Xilinx...... 52 ware-tool support. rections. Vendors historically known as program- Burgeoning amounts of on-chip RAM and sin- mable-logic suppliers are adding ASIC-plus-pro- Embedded programmable- gle-die ASIC/programmable-logic hybrid devices, grammable-logic hybrid devices to their portfolios logic cores along with predictable Moore’s Law integration in an attempt to optimally address the complicated trends, are contributing to the explosion of effective task of balancing power, performance, and cost. gate counts. These factors are finally making a real- ASIC vendors and foundries, too, are developing hy- ...... 54 ity of the long-held vision of systems on chips. To brid-device capabilities, as are standard-product Adaptive Silicon ...... 54 exploit silicon capability in a time frame that still suppliers, such as network- manufactur- Agere Systems...... 56 meets time-to-market requirements, many design- ers. And IP developers are now offering not only ers are turning from traditional low-level state-ma- “soft” logic cores that implement specific functions Atmel ...... 56 chine and schematic-entry synthesis to high-level in programmable logic but also “hard” embedded Integrated Circuit languages, such as VHDL and , and even to programmable-logic cores that can implement any Technology (ICT) ...... 56 traditional software languages, such as C. These new function you desire.

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Actel Atmel QuickLogic OTHER COMPANIES MEN- Philips 1-408-739-1010 1-408-441-0311 1-408-990-4000 TIONED IN THIS ARTICLE www.philips.com www.actel.com www.atmel.com www.quicklogic.com ARM Enter No. 322 Enter No. 326 Enter No. 330 www.arm.com www.philips.com Chartered Semiconductor TSMC (Taiwan Semicon- Adaptive Silicon Cypress Semiconductor STMicroelectronics www.csminc.com ductor Manufacturing Co) 1-408-399-8900 1-408-943-2600 1-781-861-2650 Chip Express www.tsmc.com www.adaptivesilicon.com www.cypress.com www.st.com www.chipexpress.com UMC Enter No. 323 Enter No. 327 Enter No. 331 Clear Logic www.umc.com www.clear-logic.com Agere Systems Integrated Circuit Tech- Triscend IBM SUPER INFO NUMBER 1-610-712-6011 nology (ICT) 1-650-968-8668 www..com For more information on www.agere.com 1-408-434-0678 www.triscend.com LSI Logic the products available Enter No. 324 www.ictpld.com Enter No. 332 www.lsilogic.com from all of the vendors list- Enter No. 328 MIPS Technologies ed in this box, go to www.mips.com Altera Xilinx www.ednmag.com, click 1-408-544-7000 Lattice Semiconductor 1-408-559-7778 Motorola www.mot.com on the Reader Service link, www.altera.com 1-503-268-8000 www.xilinx.com and enter no. 334. Enter No. 325 www.latticesemi.com Enter No. 333 Enter No. 329 www.national.com www.ednmag.com August 30, 2001 | edn 37 programmable-logicdirectory FPGAs

ACTEL result in the parts’ use in your system board, and, because antifuse You probably know Actel AT A GLANCE high-volume consumer creation is irreversible, in-system recon- as an antifuse-based-FPGA ୴ Actel’s antifuse products. figuration is impossible. In response to supplier, but the company technology delivers The company’s first- customers’ requests for a more flexible is broadening its focus to numerous benefits at generation PLICE (pro- FPGA technology (in the lab, the manu- include other programma- the expense of limited grammable low-imped- facturing line, and the field) that retains ble-logic technologies, as flexibility. ance circuit element) anti- antifuse’s fundamental benefits, Actel well as IP. Four main ୴ The company’s sec- fuse-technology approach first partnered with and then acquired device families form the ond-generation anti- employs a metal-to-metal Gatefield Corp and its ProASIC line of fuse structure doesn’t foundation of today’s Actel interconnect structure flash-memory-based FPGAs. consume substrate product line: the 3.3V SX, area. comprising polysilicon and In addition to being onboard-pro- ϩ the closely related 2.5V SX- ୴ Flash memory a diffused N region, sep- grammable and -reprogrammable, A and eX, and the 5V MX. builds on antifuse arated by a high-imped- ProASIC devices use an extremely fine- Actel also offers the flash- strengths and, accord- ance oxide-nitride-oxide grained three-input, one-output logic memory-based ProASIC ing to the company, is barrier. Applying high volt- cell. Actel claims that this logic cell not FPGA architecture and an finally ramping into age during programming only provides you with an intuitive SRAM-based embedded production. ruptures this barrier. The ASIC-prototyping vehicle, but also FPGA called VariCore PLICE antifuse structures, delivers a smooth learning curve for (see “Embedded programmable-logic which reside on the same base layer as budding FPGA designers who are cores”). And, by the end of 2001, the active circuit elements, consume die already experienced with ASICs and company hopes to begin sampling its area that could otherwise find use in their design tools. ProASIC also brings first flexible-interface BridgeFPGA constructing additional logic blocks, embedded-SRAM and FIFO capabilities devices. embedded memory arrays, and other to Actel’s arsenal—features missing Antifuse technology delivers low- circuits. from all but a few of the company’s anti- impedance—therefore, low-power and As a result, beginning with the SX fuse FPGAs. high-speed—signal interconnection family, Actel has migrated to a second- Actel’s Libero and Designer tool sets and more robust immunity to high- generation-technology approach that support antifuse FPGAs, and several radiation operating environments than locates antifuses directly between metal variants supply multiple combinations other configuration technologies pro- layers, above the logic. Whereas MX- of device and family, design entry, syn- vide. Actel devices are available in both series FPGAs use a relatively generic thesis, simulation, placement and rout- standard commercial- and extended- multiplexer-plus-register , ing, and programming support. The temperature options and in screened SX, SX-A, and eX devices employ a sea- Silicon Explorer II verification and high-reliability, radiation-tolerant, and of-modules ratio of two logic struc- logic-analysis tool enables you to radiation-hardened versions. tures: C-cells and R-cells. C-cells con- observe and analyze internal device Actel’s parts are also nonvolatile. tain a dual-level, two-input multiplexer nodes without, in most cases, iterating Unlike SRAM-based FPGAs, they structure plus input-inversion capabili- your design. The Silicon Sculptor sin- require no separate memory to store ty, and the company claims that the C- gle-site and multisite device program- their configuration data, and their func- cells can implement more than 4000 mer supports programming of FPGA tions are available immediately upon functions of five inputs. R-cells contain prototypes right at your PC. For system power-up. The single-chip multiple-function flip-flops with nu- ProASIC FPGAs, the vendor-supplied nature of antifuse FPGAs also makes merous signal-input, clocking, reset, tools include ASICmaster (for place- them nearly impossible to reverse-engi- and clear options. ment and routing) and Memorymaster neer or clone. This characteristic The high voltage necessary to config- (for embedded-memory-function gen- becomes increasingly important as ure an antifuse FPGA usually means that eration). IP comes both from Actel and decreasing costs and higher capacities you program it before installing it on from the company’s strategic partners.

AGERE SYSTEMS GAs sold into the digital-communica- Agere Systems, formerly Lucent Tech- AT A GLANCE tions market, Agere’s product-line and nologies (and before that, AT&T Micro- ୴ FPGAs focus on networking needs. technology focus in this area isn’t a big electronics), first entered the FPGA busi- ୴ Logic-structure innovations require syn- surprise. ness as an alternative supplier of Xilinx’s thesis support or core-generator Within each product family (Orca Se- XC3000 FPGAs, which Agere referred to intercession. ries 2, 3, and 4), multiple product gener- as its ATT3000 series. From those hum- ୴ Hybrid devices handle high-speed inter- ations exist. These subdivisions reflect ble beginnings, the company has made faces, and the latest architecture hints at different manufacturing-process tech- significant progress in establishing its CPU-integration plans. nologies and, sometimes, corresponding own identity as a programmable-logic differences in core and I/O voltages. Se- vendor and taking advantage of its inter- parent company’s telecommunications ries 2 devices group four four-input LUTs nal FPGA and ASIC capabilities. Given its heritage and the high percentage of FP- and four registers into each PFU (pro-

38 edn | August 30, 2001 www.ednmag.com programmable-logicdirectory FPGAs grammable function unit).As in Xilinx’s, cron-drawn (0.13-micron-effective) pro- ic blocks and gives a glimpse of the com- and unlike Altera’s architecture, each LUT cess that provides abundant metal layers. pany’s probable future CPU-integration grouping can alternatively serve as a syn- The company employs these layers— plans. chronous or an asynchronous, single- or along with other uses—to create a dedi- In 1996, both Actel and Lucent an- dual-port, RAM or ROM block. Each cated clock-distribution network nounced their intentions to produce hy- PFU also contains eight tristate buffers throughout the chip. Active repeaters brid ASIC-plus-FPGA devices. Lucent’s for implementing internal bus structures. prevent signal-quality and performance promise turned into reality in May 1998, Enhancements with Series 3 include degradation across long routes and mul- when the company introduced its first the SLIC (supplemental-logic-and-inter- tiple pass-gate interconnect elements. FPSC (field-programmable system chip). connect cell), an upgraded version of the Agere’s ASIC division also offers the Se- The Orca Series 3-based OR3TP12 com- tristate-buffer structure that now also ries 4 programmable-logic structure as bines an 18ϫ18 PLC (programmable- supports an as-much-as-10-bit decoder an embedded core (see “Embedded pro- logic-cell) array and an ASIC-housed, and PAL-like AND-OR-INVERT logic.A grammable-logic cores”). 64-bit, 66-MHz PCI core. This core in- built-in microprocessor interface enables Regardless of its logic density, each Se- terconnects via two 64ϫ32-bit master FI- parallel programming and configuration ries 4 device includes six general-purpose FOs and two 64ϫ16-bit target FIFOs. read-back and provides a glueless con- and two application-specific PLLs. Lu- The follow-on OR3LP26B doubles both nection to i960 and PowerPC CPUs. The cent supplements its FPGAs’ previous- the amount of on-chip FPGA logic and PCM (programmable clock manager), a generation LUT-derived embedded- the ASIC-to-FPGA interconnect band- PLL variant, enables adjustment of input memory capability with dedicated width, and the ORT4622 replaces the PCI clock phase and duty cycle. The size of 512ϫ18-bit, quad-port (two read, two core with a four-channel, 622-Mbps, full- each Series 3 PFU, which now includes write) discrete RAM blocks, including duplex synchronous interface with built- eight four-input LUTs and nine registers, built-in write-port arbitration, a FIFO, a in CDR. The first Orca Series 4-based hy- more than doubles that of Series 2 PFUs. multiplier, and CAM logic. Series 4 I/O brid chips, the ORT8850 series, are deriv- Lucent supplies 5 (3C), 3.3 (3T), and buffers’ optional LVDS terminating re- atives of the ORT4622 that include an 2.5V (3L) variants of the architecture. sistors are on-chip. Like previous-gener- eight-channel, 850-Mbps CDR macro. Agere’s Series 4 devices focus attention ation Orca architectures beginning with The ORT82G5 is a 1.25-, 2.5-, or 3.125- on signal routing. The company based Series 2, Series 4 devices are partially re- Gbps backplane-interface FPSC, and the this decision upon recognition that de- configurable. Lucent revamped the log- ORLI10G is a 10-Gbps line-interface de- lays in this area—not in logic—are in- ic-cell structure with modular, hybrid de- vice. Lucent’s Orca Foundry back-end creasingly defining the upper limit of de- sign in mind.An on-chip,ARM-derived, software handles placement and routing sign performance. Agere fabricates its multimaster peripheral bus both simpli- for all of the company’s FPGAs and initial Series 4 devices with a 0.16-mi- fies the interconnection of multiple log- ASIC-plus-FPGA devices.

ALTERA successor, targets moderate- vides larger and more numerous EABs For legal and marketing rea- AT A GLANCE density and -performance (embedded array blocks) and flexible I/O sons, you’ll never find the ୴ Aggressive migra- designs that require no on- buffers that support numerous protocols acronym “FPGA” in any of tions to smaller lithog- chip memory or esoteric and electrical standards. As with Xilinx’s raphy processes have Altera’s literature, even enabled lower prices, packaging. Altera eliminat- chips, Altera’s devices’ EABs are the key though the rest of the world higher gate counts, ed the Flex 10K PLLs and factors behind the vendor’s claims of ex- knows the chips as FPGAs. reduced power, and decreased the amount of ponentially growing gate counts. If you Altera prefers to call its parts higher speeds. global signal routing on can use all that memory, great. If not, you “LUT-based programma- ୴ Copper intercon- Flex 6000 from that on the won’t come close to squeezing into one ble-logic devices.” A long- nect strives to keep Flex 10K. Instead, the Flex chip the design sizes that Altera’s mar- line, routing-dominated internal logic delays 6000 substitutes dedicated keting indicates are possible. Apex 20KE FPGA architecture provides from falling behind local LAB-to-LAB and enables you to use the EABs for imple- timing predictability; in devices’ I/O-buffer per- LAB-to-I/O-buffer inter- menting not only single- and dual-port addition, Altera’s routing formance capabilities. connect. The Acex 1K fam- RAM and FIFOs, but also very small ୴ Hybrid chips with approach enables on-chip industry-standard ASIC- ily is a Flex 10KE variant CAMs. Apex 20KC migrates the Apex redundancy, particularly housed CPU cores, built on a smaller lithogra- 20KE architecture to a process employ- during the early stages of along with a soft CPU phy process that is opti- ing low-impedance copper-interconnect process and device produc- core, are finally here. mized for low cost. Like Flex lines for all metal layers. tion, to improve yields. 6000, Acex 1K comes in Development of Altera’s CPU-inclu- From the Flex 8000 and follow-on Flex smaller gate counts and with packaging sive hybrid chips took longer than 10K architectural foundations,Altera has options that are more restricted and less expected, but Altera is now sampling its taken its FPGA product line in several di- expensive than its Apex 20K and other ARM-based Excalibur XA devices, built rections, all based on a common, essen- Altera big brothers. on an Apex 20K foundation, with MIPS- tially unchanged LAB (logic-array- Apex 20K includes as many as four on- based XM parts soon to follow. Combine block) structure. Flex 6000, the Flex 8000 chip PLLs. The device family also pro- Apex 20KE with eight to 18 channels of

40 edn | August 30, 2001 www.ednmag.com programmable-logicdirectory FPGAs

ASIC-housed CDR circuitry and slight- buffers, and you have the latest Altera ar- and partner-developed cores. The same ly modify the logic block structure, and chitecture, Apex II. Max1 software you’d use to design with you have the Mercury family, supporting Altera has also developed an optimized Altera’s CPLDs also supports Acex 1K data-throughput speeds of 125 Mbps to 8- and 16-bit RISC processor it calls Nios, and Flex FPGAs. For Acex 2K and Apex 1.25 Gbps. And double up the RAM-to- which the company aims to have reside devices, you’ll want to fire up Altera’s ESB (embedded-system- block) ratio in in FPGA logic as a soft core instead of in more advanced Quartus II development- Apex 20KC; increase the number of ASIC gates. Over time, Altera plans to tool environment, along with the Signal- PLLs; and speed up, increase the number port Nios to all of its FPGA architectures, Tap logic analyzer. of, and make more flexible the I/O along with its other internally developed

ATMEL plement distributed on-chip the CPU. An integrated design-tool en- Atmel’s two FPGA architec- AT A GLANCE memory arrays, FIFOs, or vironment lets you develop software tures, the AT6000 and new- ୴ Second-generation other SRAM-derived func- and hardware in parallel, simulating er AT40K families, both of- FPGAs have multiplica- tions. However, at the point and co-verifying the multiple pieces of fer dynamic partial-re- tion in mind. at which four logic-block your design. programming capabilities ୴ An 8-bit AVR con- clusters (each containing 16 The latest spin on the FPSLIC archi- that the company defined troller makes system-on- logic blocks) intersect, you’ll tecture, AT49S, is a single-chip, dual-die chip designs a reality. with reconfigurable-com- find a 128-bit dedicated device with a specially designed, non- ୴ A security-minded puting applications in architecture spin makes RAM array. This approach is volatile-memory array. Containing two mind. The two families’ design duplication an intermediary step be- data buses, one going to the system and logic structures are quite difficult. tween the small, 16-bit, the other running only within the pack- different, though, and the LUT-derived memory ar- age between the memory and AT49K,the AT40K devices include fea- rays and the much larger Secure FPSLIC’s memory also includes a tures that broaden their applicability to dedicated SRAM blocks in other vendors’ security bit. Once you set this bit, the chip general-purpose designs. architectures. Atmel has also come up will respond only to a full-chip-erase AT6000 logic cells consist of several with an interesting packaging twist: The command. You must set the security bit fixed-function logic gates plus a register. parts are pinout-compatible with some to initiate memory-to-AT49K commu- In AT40K FPGAs, you find the more Xilinx XC4000 offerings, conceptually of- nication. The approach doesn’t com- common LUT-plus-register combina- fering you an alternative silicon source pletely eliminate the security threat; al- tion but with a twist. Instead of a single for your designs. though the external bit-stream trace four-input LUT, Atmel pairs each flip- AT40K is also the silicon foundation between memory and AT49K is no flop with dual three-input LUTs, a com- for Atmel’s FPSLIC (field-programma- longer present, stripping back the mul- bination that, in some cases (if the de- ble system-level-integration-circuit) tidie package lid exposes the internal bus sign tools take advantage of it), offers devices. These hybrid parts contain for probing. However,Atmel’s tactic is an greater design flexibility. Also, ahead of both an FPGA array and an ASIC- example of low-cost security that, in the LUTs is a dedicated two-input AND housed AVR RISC microcontroller, many cases, will be good enough to foil gate. Combined with diagonal routing, with data and program memory and the efforts of would-be thieves. Atmel’s this logic tweak enables AT40K FPGAs comprehensive peripherals. Atmel has ASIC group includes the AT40K pro- to better support the matrix-multiplica- focused on optimizing the intercom- grammable-logic structure in its IP port- tion operation so common in DSP func- munication link between the CPU and folio, with FPSLIC as the proof of con- tions. FPGA array, enabling the FPGA array cept (see “Embedded programmable- Unlike with some FPGAs, you can’t al- to, for example, implement hardware- logic cores”). ternatively use the AT40K LUTs to im- accelerated coprocessor functions for

QUICKLOGIC Logic has also been the most enthusias- aggressive about rolling out correspon- Antifuse advocate QuickLogic has, since tic about embracing the hybrid ASIC- ding devices. its earliest pASIC 1 architecture, em- plus-FPGA approach and the most The company builds its pASIC 2 and ployed ViaLink, a metal-to-metal anti- 3 product families on lithographies fuse technology, above the logic grid. smaller than those of the original pASIC Only recently has Actel begun to match AT A GLANCE 1 technology, with correspondingly high- ViaLink’s advantages. QuickLogic’s chips ୴ Logic cells promote design flexibility. er logic counts, lower operating voltages, have all of the inherent antifuse advan- ୴ Embedded standard products integrate and higher speeds. The pASIC parts em- tages (see the Actel entry under RAM and system-interface modules. ploy a novel logic cell comprising two six- “FPGAs”), including the availability of ୴ ASIC-housed DSP, PCI, Fibre Channel input AND gates, four two-input AND extended-temperature and military- and SERDES functions are now available, gates, multiple two-to-one multiplexers, screened device variants. Of all the pro- and MIPS CPUs are on the horizon. and a D flip-flop. The logic cell’s numer- grammable-logic manufacturers, Quick- ous inputs allow it to implement—in one

42 edn | August 30, 2001 www.ednmag.com programmable-logicdirectory FPGAs logic level—functions that in other ap- add embedded-RAM blocks, and Quick- as many as eight SERDES data channels proaches might require multiple per- PCI parts embed PCI cores alongside and two clock channels, all bus-LVDS for formance-sapping logic cells. Multiple various sizes of user-programmable log- high-current and long-signal-drive ca- logic-cell outputs allow the synthesis and ic gates. The company offers numerous pability.And, like Altera, QuickLogic has place-and-route software to pack unre- PCI-core flavors: 32- and 64-bit; 33-, licensed the MIPS32 4Kc core (with lated logic functions into one cell, maxi- 66-, and 75-MHz; and master and slave. product availability slated for this year) mizing silicon use. A high-performance, beefy set of FIFOs and an option for the MIPS64 5Kc. QuickLogic’s newest FPGA architec- connects the PCI core to your design’s Design-software support comes from ture, Eclipse, focuses first on improving logic. QuickFC employs ASIC logic to QuickLogic’s Quick-Works for PCs and the I/O buffers. These buffers now con- construct a Fibre Channel encoder/de- QuickTools for workstations. QuickLogic tain input, output, and output-enable coder with data rates as fast as 2.5 Gbps was one of the first programmable-logic registers and support a variety of volt- and a 32-bit synchronous-FIFO system companies to embrace synthesis-based ages, including differential standards, on interface. design and bundle compilers with its tool a per-bank basis with eight I/O banks per QuickLogic turned to the Eclipse ar- set. The online WebAsic program enables chip. QuickLogic has also doubled the chitecture to implement its next ESP you to upload your design’s bit-stream file number of registers in each logic cell and families. QuickDSP uses ASIC gates to and receive free samples from QuickLog- added a multiplexer and now provides as implement dynamically reprogramma- ic; North American customers can receive many as six outputs. Eclipse also has four ble dedicated-arithmetic circuits that the samples in as little as 24 hours. The com- PLLs, a beefed-up clock- and control- company calls ECUs (embedded com- pany also supplies the QuickPro desktop signal network, and multiple embedded putational units). Each ECU can imple- device , and various PCI-de- dual-port-RAM blocks. ment several single-pass asynchronous velopment boards. And, for QuickDSP The pASIC FPGAs are the foundation and registered functions (8ϫ8-bit mul- devices, the QuickFilter tool lets you cre- of the company’s QuickRAM, QuickPCI, tiply, 16-bit add, or accumulate with car- ate and analyze digital-filter designs. The and QuickFC devices, the first few in a se- ry); multiple passes through the ECU tool then generates coefficients, computes ries of the company’s ESPs (embedded support the common multiply-accumu- magnitude and phase responses, and cre- standard products). QuickRAM chips late function. QuickSD devices integrate ates stimulus test files.

TRISCEND mable-logic cells translate to as many as Triscend originally intended the pro- 40,000 ASIC gates. E5 devices provide AT A GLANCE grammable-logic arrays on its E5 and A7 two dedicated DMA channels, and an ୴ Configurable logic that once targeted CSOCs (configurable systems on chip) to on-chip breakpoint unit provides de- only microcontroller peripherals now has implement only customer-specific mi- bugging capability. broader general-purpose use. croprocessor peripherals. However, re- Triscend’s long-delayed A7 family ୴ ARM- and 8051-based hybrid-chip fami- cent revisions of both Triscend’s brings the CSOC concept to the 32-bit- lies address 8- and 32-bit computing FastChip tools and its partners’ design processor world. In this case, the CPU needs. software enable the arrays’ use as gener- core is the ARM7TDMI, and A7 CSOCs ୴ SuperH-based devices are on the hori- al-purpose programmable logic. High- also feature an ASIC-housed memory zon. lights of the E5 family include a per- controller, four-channel DMA controller, formance-accelerated 8051 microcon- JTAG interface, 16-input interrupt con- troller core and as much as 64 kbytes of troller, dual timer/counters, dual serial agreement forged with Hitachi in Janu- on-chip, dedicated system RAM. Ac- ports, and watchdog timer, and other cir- ary 2001, SuperH-based CSOCs are now cording to the company, 3200 program- cuits. Based on a joint-development on Triscend’s road map.

XILINX logic block) comprises two four-input Since Xilinx’s founding in 1984, the LUT- LUTs, a three-input LUT, and two regis- AT A GLANCE plus-register combination has been a ters. I/O buffers also contain multiple reg- ୴ consistent element in its devices, but the Increased LUT and register integration isters to ease setup-time restrictions and within each logic block matches the pace of logic cell and peripherals have evolved to boost clock-to-valid-output speeds. Xilinx’s technology progression. over the years. Xilinx also briefly flirted ୴ Virtex brought embedded discrete- Over time, this product family has un- with antifuse-based FPGAs.An architec- memory arrays to the company’s FPGA dergone several process migrations, with ture for reconfigurable computing has product line. corresponding voltage decreases, growth faded into the sunset, but Xilinx has res- ୴ Foundry-friendly Virtex-EM FPGAs were in per-chip logic capacity, and higher per- urrected some portions of the techniques the first to incorporate copper routing, and formance.Although XC4000 devices con- this architecture pioneered in the com- PowerPC-based hybrid chips are on the tain no large embedded-RAM blocks, you pany’s latest product families. way. can reconfigure the LUTs for use as dis- Each XC4000-series CLB (configurable tributed-RAM arrays.

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ASIC-replacement Spartan and Spar- amount of discrete SRAM, leading to an tinues this trend with Virtex II, which of- tan-XL parts trace their lineage back to exponentially higher gate count that you fers eight LUTs and eight registers per the XC4000E. Spartan is a follow-on to can’t exploit unless your design relies CLB. With all of that available metal, Xi- Xilinx’s first stab at less expensive FPGAs, heavily on embedded memory. linx boosted the amount of long-line, the XC5200, which, like Altera’s Flex 6000 Virtex-E parts also double the number LUT-to-LUT, and CLB-to-CLB routing. and 8000, didn’t support embedded of on-chip DLLs to eight and incorporate The company includes dedicated 18-bit, memory. Spartan forgoes the XC4000E’s a more-than-300-Mbps-per-pin, chip- fast-multiplier logic, which it claims can parallel-interface-configuration option to-chip, buffered, double-data-rate com- perform more than 600 billion 8-bit mul- and dedicated, on-chip, wired-AND de- munication protocol that the company tiply-accumulate operations/sec. Virtex code and comes only in low-cost plastic calls SelectLink.Virtex-EM further bloats II also adds Digitally Controlled Imped- packaging. Xilinx offers both 5 and 3.3V the memory-to-logic proportion (at four ance Technology. This feature provides versions of the first-generation Spartan gates per SRAM bit). This device family optional internal termination resistors, architecture. marks the emergence of copper routing whose values automatically match those Compared with the baby steps that at the upper two metal layers. The cop- of the external reference resistors you preceded it, the XC4000-to-Virtex tran- per routing provides power and low-la- supply (two resistors for each of the eight sition was a giant leap forward in archi- tency clock distribution throughout the I/O blocks on a device). tecture. Xilinx found that front-end syn- chip.Virtex also provides the foundation Xilinx has finally embraced the ASIC- thesis tools rarely take advantage of the for the Spartan II family, which migrates plus-FPGA concept and plans to by the three-input LUT. The Virtex logic block to a smaller lithography and focuses on end of 2001 introduce Virtex II Pro parts eliminates it, switching to a combination a lower cost packaging subset. Unlike the with integrated IBM PowerPC CPU of four four-input LUTs and four regis- redesign that marked the XC4000E-to- cores. Design support for Xilinx’s FPGAs ters. Xilinx supplements the distributed Spartan transformation, Spartan II re- comes from the Alliance tool set, which LUT memory with multiple 4-kbit dual- tains almost all of Virtex’s features interfaces to third-party front-end design port discrete-SRAM arrays. For a third Xilinx’s latest Virtex II family, another software, and from the full-featured level of memory, Virtex provides high- copper-enhanced architecture, incorpo- Foundation suites. In line with the par- speed, flexible I/O buffers to—among rates discrete-RAM blocks that include tially reprogrammable capabilities of Vir- other things—interface to external parity and are 4.5 times larger than those tex devices, Xilinx has also developed a SRAM and DRAM. First-generation Vir- in Virtex. Virtex II adds support for two portfolio of Java-based software products tex devices contain four DLLs. The sec- new block-RAM operating modes. In that enable chip programming and re- ond-generation Virtex-E and Virtex-EM moving from XC4000 to Virtex, Xilinx programming at the design bench, on the devices don’t alter the Virtex logic-cell doubled the per-logic-block number of manufacturing line, and in the field. structure but dramatically boost the LUTs and registers. The company con-

PALs & PLDs ALTERA and exceeding the device’s core operating In the late 1980s, Altera pioneered the AT A GLANCE voltage for no-glue system interfacing. concept of the CPLD, a device with nu- ୴ Over the years, Altera has only slightly In an attempt to radically grow the merous logic blocks, each consisting of fine-tuned its Max 7000 flagship CPLD- macrocell capacity of its CPLDs, Altera a PAL- or SPLD-like group of macrocells. product line. introduced the Max 9000 family in 1994. These logic blocks interconnected to each ୴ Hierarchical routing can’t keep up with This CPLD architecture migrates from a other and the outside world via a fully or Moore’s Law and comes with timing trade- monolithic logic-block-to-logic-block partially populated switch matrix. Al- offs. interconnect matrix to a multistage ap- ୴ Relaxed and restricted testing, along tera’s early CPLDs used PROM or proach. This approach is reminiscent of with plastic packaging, lead to low-cost EPROM cells as switch-configuration el- Altera devices. the company’s Flex devices and more ements, but the company’s Max devices generally of any segmented routing have migrated to in-system-program- FPGA. The advantage of a hierarchical mable EEPROM technology. counts. Along the way, Altera has fine- interconnect structure is that, because it Max 7000 is the primary workhorse of tuned the Max 7000 in many ways. Per- is distributed throughout the device, it today’s Altera CPLD-product line, and haps the most significant is the addition doesn’t exponentially grow with increas- the architecture has remained essential- of in-system programming beginning ing macrocell and, therefore, logic-block ly unchanged through multiple process with the 5V S series. The 3.3 and 2.5V count, as a global matrix tends to do. evolutions. Smaller semiconductor lith- variants also include this in-system pro- The disadvantage of a hierarchical ap- ographies often translate not only to low- gramming. Altera is also particularly proach, though, is that pin-to-pin and er cost per macrocell but also to higher proud of its Multivolt I/O technique, in logic-block-to-logic-block timing de- speed, lower operating voltage and pow- which the I/O buffers drive output and pend on placement and are therefore un- er consumption, and higher macrocell handle input voltages both lower than predictable. Performance predictability

46 edn | August 30, 2001 www.ednmag.com programmable-logicdirectory PALs & PLDs and the ability to more easily implement Altera’s introduction of its Max Design-tool support comes from Al- logic circuits with many product terms 3000A product family may be—at least tera’s MaxϩPlus II development soft- and comparatively fewer registers have partially—a response to the aggressive ware, which is available in both single- always been key advantages of PALs and prices of products from CPLD-replace- and floating-node versions and for mul- PLDs over FPGAs. Search the Web ver- ment vendor Clear Logic. Compared tiple operating systems. Altera’s tool sion of this article at www.ednmag.com with 3.3V Max 7000 devices, Altera tests sets—like tool sets from all of the vendors for Table 2 and note that the logic den- its Max 3000A parts to relaxed specifi- in this directory—come in multiple ver- sity of the Max 7000 family, which has cations, allowing higher power con- sions; support various families of prod- undergone aggressive cost reductions, sumption. The company offers the parts ucts and devices within each product now comes close to matching that of the with fewer packaging options, and the family; and offer multiple design-entry, largest Max 9000 device and at a lower 3000A doesn’t support all of the Max simulation, synthesis, fitting, and pro- price per macrocell. 7000 features. gramming options.

ATMEL ation’s pinout and performance through Atmel specializes in both industry-stan- multiple design iterations. AT A GLANCE dard devices and backward-compatible Other ATF1500 features include in- ୴ supersets of common PALs and CPLDs. Atmel’s 22V10 superset squeezes addi- system programming, individual I/O- tional logic onto a low-pin-count device. The vendor’s 16V8, 20V8, and 22V10 buffer selection, enable capability, op- ୴ An increased number of logic-block parts come in multiple power, voltage, inputs improves probability of pinout- and tional latch modes for the macrocell and package variants. If you need to performance-locking. flip-flops, independent combinatorial squeeze additional logic into a 22V10 ୴ An enhanced switch matrix augments and registered options for macrocell out- pinout, consider the ATF750; the ATV- larger-macrocell-count CPLDs. puts and feedback terms, and three glob- 2500B delivers even more logic capacity al clock inputs. Atmel offers conversion in a 44-pin footprint. tools that automatically migrate designs With the ATF1500 series,Atmel has Al- claims that this series can handle designs originally targeting other vendors’archi- tera’s Max 7000 architecture in the bull’s that wouldn’t fit into competitors’ de- tectures. The company also provides de- eye. By beefing up both the number of vices with comparable macrocell counts. sign-software options that support Abel, inputs (40) into each logic block and the Enhanced connectivity also means that schematic-, and VHDL-synthesis design- global-routing switch matrix, the vendor you can more easily maintain your cre- entry alternatives.

CYPRESS SEMICONDUCTOR cludes all of the logic necessary to create The Ultra37000 family, like Atmel’s AT A GLANCE dual-port memory or a synchronous ATF1500 CPLDs, builds on an Altera ୴ Cypress’ traditional-looking Ultra37000 FIFO. Cypress also includes PLL circuit- Max 7000 foundation with some aggres- CPLD has nontraditional timing specifica- ry that can multiply (as much as 43 and 1 sive assertions. These claims include no tions. 266 MHz) or divide (as little as /16) an in- fan-out delays, no expander delays, no ୴ SRAM-based chips beef up the internal coming 25- to 133-MHz clock. This cir- additional delays for I/O pins versus ded- memory, sometimes include the configura- cuitry can also de-skew and phase-shift icated pins, no penalty for using the full tion chip, and form the foundation of com- the clock. The FPGA-reminiscent I/O 16 product terms per macrocell, and no munications-focused hybrids. buffers support numerous electrical pro- ୴ delay for local product-term steering or Low-cost, high-quality design software tocols, have programmable slew rates completes the picture. sharing. There’s also no additional delay and bus hold and contain multiple ded- through the programmable interconnect icated registers. Some Delta39K versions matrix, because all signals from all scheme. Because the SRAM’s already combine the CPLD and a configuration macrocells route through the matrix. The there for device-configuration memory, flash memory in a dual-die, single-chip device specifications reflect this fact. Cypress includes substantially more for package. Available in both 5 and 3.3V variants, the your use. Each 16-macrocell logic block Cypress reduced the cost of Delta 39K devices range from 32 to 512 macrocells, is nearly identical to those of the Ul- to develop the Quantum 38K family. The are in-system-reprogrammable, and tra37000, including 36 inputs from the company eliminated the single-port clus- come in a variety of packages. interconnect matrix. Groups of eight log- ter memory and dedicated FIFO logic, With its Delta39K architecture, Cy- ic blocks combine to form a logic-block along with the embedded PLL, and sim- press switched from EEPROM to SRAM cluster, which also contains two 8-kbit plified the I/O buffers. Delta 39K also to take advantage of SRAM’s high degree single-port-RAM arrays. forms the foundation of the company’s of logic compatibility and leading-edge- Outside each logic-block cluster and ASIC-plus-programmable-logic PSI lithography status. Attempting to blend closely connected to multiple sets of (programmable-serial-interface) chips, the best aspects of CPLDs and FPGAs, global-routing tracks is an additional 4 which consolidate SERDES capability. Delta39K uses a hierarchical-routing kbits of specialty SRAM. This SRAM in- Signaling speeds are 200 Mbps to 1.5 or

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2.5 Gbps per serial link, and the family time upgrades for Warp, which supports tem-reprogrammable version includes a provides a maximum duplex serial band- the entire Cypress product line and in- programming kit and a demo board. The width of 12 Gbps. Supported standards cludes VHDL and Verilog synthesis, a fi- $495 Warp Professional adds a flow man- include PCI, SONET, Gigabit Ethernet, nite-state-machine editor (for Win- ager, a block diagram editor, and a lan- Fibre Channel and InfiniBand. dows), a static timing analyzer and guage assistant, and $2995 Warp Enter- The company is proud of its silicon dynamic timing simulator, fitter soft- prise adds a Code2Graphics HDL (which also includes several SPLDs), but ware, and reference documentation. You converter, source-level behavioral simu- it’s also pleased with its software. For $99, can order and download Warp from Cy- lation, a debugger, and testbench-gener- you get free technical support and life- press’ Web site. The $175 Warp 2 in-sys- ation capability.

INTEGRATED CIRCUIT TECHNOLOGY (ICT) a multipurpose flip-flop that can imple- ICT’s fortunes lie in the low-gate-count AT A GLANCE ment buried register functions. Input and end of the programmable-logic business, ୴ Proprietary variants of industry-standard I/O cells also contain registers. where other suppliers fear to tread. ICT’s PALs target designs requiring low power On the other end of the complexity PEEL devices replace 20- and 24-pin PALs and greater flexibility. spectrum are ICT’s TPAs (tiny PEEL ar- with alternatives that have supersets of ୴ A PLA and multiple registers create an rays). These small, low-power devices will functions. Factors that differentiate the unconventional CPLD. become available for sampling by the end ୴ company’s devices include low standby Tiny PEEL arrays aim to fill a niche of 2001. ICT is also pursuing embedded- between discrete logic chips and today’s and active power consumption, addi- PLD technology, based on SRAM instead low-end PALs, with embedded PLDs acting tional device inputs, additional macrocell as their on-ASIC equivalent. of EEPROM (see “Embedded program- product terms, and additional register mable-logic cores”). The company’s Place functions. Speeds are as fast as 5 nsec, development software is free to qualified with most devices in the 15- to 25-nsec ray structure is a PLA, allowing full sum- users. It includes an architectural editor, range. of-products logic functions to feed—in a logic compiler, a waveform simulator, a Higher complexity, proprietary PEEL groups of four—each logic-control cell. documentation utility, and a program- arrays employ an architecture that The four-input (plus clock, preset, reset, mer interface. Separate fitters are also squeezes maximum logic density into 24- and register-type signals), three-output available should you prefer to use third- to 44-pin packages. The central logic-ar- logic cell contains three multiplexers and party front-end tools.

LATTICE SEMICONDUCTOR each ispLSI 5000 logic block also con- Lattice first differentiated itself from the AT A GLANCE tains 32 macrocells. The input-to-macro- competition by bringing in-system pro- ୴ In-system programming remains cell ratio is actually lower than that of gramming to PALs. Before this advance- Lattice’s key corporate-marketing motto. some other CPLD architectures. ment, PALs were based on less flexible ୴ Mach 4A overlaps SuperFast and Lattice’s SuperBig ispLSI 8000 archi- ROM, PROM, EPROM, and fuse tech- SuperWide CPLDs but adds a timing twist. tecture switches from a global to a dual- ୴ SPLDs, programmable switch and pro- nologies. In the CPLD arena, the com- level hierarchical routing matrix, with lo- grammable analog devices complete the pany divides its products into SuperFast, large product line. cal routing interconnecting six groups of SuperWide, and SuperBig categories. The 20 macrocells. Lattice calls these groups ispLSI 2000 family ranges from 32 to 192 Megablocks, and global routing stitches macrocells; comes in 2.5, 3.3, and 5V state. Additional product terms and reg- together the Megablocks. Each logic variants; and specifies propagation delays ister redefinition require use of the prod- block comprises 20 macrocells and has 44 as fast as 3 nsec.At first glance, this prod- uct-term sharing array and incur a tim- inputs. The ispLSI 8000 devices also con- uct range might seem to overlap with the ing penalty. With Mach 4A, on the other tain an embedded 108-line tristate bus. lower end of the Mach 4A device family, hand, Lattice guarantees near-ispLSI I/O buffers include flip-flops for option- which Lattice adopted when it took over 2000 speeds with as many as 20 product al registered input, output, and bidirec- Vantis, but dig a little deeper into the terms per macrocell—a feature the com- tional control. specifications. pany calls Speed-Locking. In addition to the previously men- You can achieve the highest ispLSI The ispLSI 5000 family also overlaps tioned programmable-analog devices, 2000 performance when each macrocell Mach 4A, this time at the Mach 4A’s Lattice offers a series of SPLDs and consumes no more than four product higher macrocell counts. This family is the logic-deficient—compared with terms and when the corresponding reg- notable for the wide 68-input fan-in to CPLDs—but routing-rich ispGDX pro- isters bypass the XOR gates at their in- each logic block. This specification grammable-interconnect architecture. puts and remain in their default D-type sounds impressive until you realize that For you fans of nondigital design, the

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company also sells ispPAC programma- to obtain ispExpert Compiler for Lattice- ming pioneer, Lattice also supplies a va- ble analog chips. Lattice’s PC design soft- developed architectures and DesignDi- riety of programming software, source ware, ispDesignExpert, comes in numer- rect Summit for the Mach4A. In line with code, and hardware to help you get your ous variants. For workstations, you need its heritage as the in-system-program- design up and running.

STMICROELECTRONICS processor buses. You can program PSDs Waferscale Integration’s PSDs (Pro- AT A GLANCE either offboard using a PROM program- grammable System Devices), now part of ୴ Memory-plus-logic hybrid chips began mer, onboard under system-processor STMicroelectronics, began with a simple with the vision of preserving microcon- control, or via a JTAG interface. premise: Combine EPROM with logic to troller ports while expanding code memory Smaller lithographies have boosted re-create port pins lost when you couple ୴ Latest variants combine multiple memo- read and write speeds, as well as reduced an 8-bit microcontroller with a conven- ry types and increase programmable-logic operating voltages and currents. So- tional memory. From those humble be- versatility. called “zero-power” variants employ ad- ୴ Support for 8- and 16-bit processors is ginnings, the product line has expanded dress-transition detection and other de- now supplemented with DSP-targeted in many directions. For example, the chips, and development tools speed your sign techniques to further reduce power company now offers in-system-pro- time to market. consumption in standby modes. The lat- grammable and -reprogrammable flash est PSD, the DSM2180F3, mates with memory, including a separate boot array, Analog Devices’ ADSP-218x DSPs and instead of EPROM. more flexible, useful for general-purpose includes eight 16-kbyte flash-memory PSDs also now combine in one chip functions, not just port re-creation, and sectors. STMicroelectronics supplies log- nonvolatile-code, nonvolatile-data (EE- the same part, after design-specific con- ic- design tools, device programmers, PROM), and volatile-data (SRAM) par- figuration, can bolt to numerous 8- and and evaluation boards for all its PSD de- titions. The integrated logic has become 16-bit embedded-controller and -micro- vices.

XILINX equally robust software support, which Just as Altera is a CPLD vendor that lat- AT A GLANCE has been a key focus for the product line er added FPGAs to its product portfolio, ୴ Xilinx’s second-generation architecture since the Xilinx acquisition. Xilinx is an FPGA supplier that subse- makes inroads into CPLD applications. The company has two interesting— quently bought and developed several ୴ Acquired CPLDs keep their cool and and free—software products. The Inter- CPLD-product families. Available in 2.5, strive for a perfect fit. net-based WebFitter tool accepts designs 3.3, and 5V versions, XC9500 devices ୴ Hit the Web for free software and other in VHDL, Verilog, ABEL, EDIF (elec- comprise 36 to 288 macrocells and in- stuff. tronic-design-interoperability format), corporate a fairly mainstream global- and XNF (Xilinx Netlist Format). The routing architecture. One of the parts’ combines low power, high performance, tool includes competitive architecture- most notable characteristics is that and design flexibility. The parts deliver design file-conversion utilities. WebFit- they’re based on flash memory, not EE- standby power of less than 100 µA with- ter provides links to fitting, timing, and PROM. The vendor claims that this set- out the need for special power-down bits log files; targeted-device data sheets; on- up results in lower cost and higher re- or pins that negatively affect device per- line price quotes; simulation and device- programming-cycle capabilities. (Most formance. Pin-to-pin propagation delays programming files; online tutorials; and applications have little need for this re- are as low as 5 nsec for the 32-macrocell complete online help. The downloadable programming-cycle feature.) device, and macrocell counts range from WebPack-ISE modules include Abel and In mid-1999, Xilinx purchased Philips’ 32 to 384. HDL synthesis, entry-level-simulation PAL and CPLD product lines. The ac- As with ICT’s PEEL arrays, Xilinx’s and testbench generation, schematic and quired devices included a 22V10, a range XPLA3 incorporates a 36348 PLA full- graphical-state-diagram entry, fitting of 32- to 128-macrocell, low-power but programmable-AND/programmable- and place-and-route algorithms, and de- otherwise-conventional CPLDs and two OR structure. Along with a variable- vice-programming utilities.WebPack ISE high-macrocell-count, SRAM-based function multiplexer and foldback supports both the XC9500 and Cool- CPLDs conceptually similar to Cypress NAND logic, this combination concep- Runner CPLD product lines as well as the Semiconductor’s Delta39K devices. Go- tually delivers robust Virtex V300E, Virtex II (to 300,000 ing forward, Xilinx is enthused about the and device fitting. However, all of this sil- gates), and complete Spartan-II FPGA CoolRunner XPLA3 architecture, which icon potential will go to waste without families.

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ACTEL design process to explicitly specify the fi- Actel has chosen a conventional logic-cell AT A GLANCE nal physical layout. Actel recommends approach, consisting of dual three-input that you obtain and use a separate pro- ୴ Embedded programmable logic enables LUTs feeding a register, for the VariCore grammable-logic-optimized synthesis Actel to partner with ASIC companies that it embedded FPGA architecture it acquired competes against with its FPGAs. compiler for the portion of your design when it purchased Prosys Technology in ୴ Conventional logic-cell structure is pro- that goes into VariCore. 2000. Reflecting the fact that FPGA com- grammable-logic-synthesis-friendly. The architecture arranges both the pilers are tuned for the more common ୴ Multiple logic-array configurations logic structures and the routing between four-input LUT structure, the Actel log- address numerous space, power, and per- them in a hierarchical manner. Actel be- ic cell can optionally but less efficiently formance constraints. lieves that this approach offers flexibility, group the two three-input LUTs into one predictability in timing and logic usage, four-LUT equivalent. and faster place-and-route times. The A review of Actel’s VariCore data sheet PEG layouts on 0.18-micron process vendor claims that a design with 70% reveals some curious omissions: hard- technologies. You can orient these mul- three-LUT usage on a 4ϫ4-PEG FPGA ware multipliers or other arithmetic-op- ti-PEG arrangements in square, rectan- completely compiles on a 500-MHz PC timized structures, three-state buffers or gular, and even L-shaped structures. in about nine minutes and that designs bidirectional buses, and partial-reconfig- According to Actel, the ideal VariCore routinely and easily use close to 100% of uration capability. The embedded FPGA shape is square, because it minimizes the the functional groups. Each multi-PEG arrangement does, however, include internal delays within the FPGA core. array also contains JTAG circuitry and a built-in vertical-carry chains that op- However, in some applications, a differ- BIST interface but not a BIST controller. tionally connect to one of the three LUT ent-shaped core provides a more efficient Because of the fixed silicon cost of inputs. Each functional group contains implementation at the physical level. overhead circuitry, Actel doesn’t antici- four pairs of three-input LUTs and four Also, each of the PEG blocks with exter- pate offering single-PEG arrays, at least registers. The registers share common nal edges provides 48 inputs and outputs at the 0.18-micron-process generation. control inputs (enable, preset, reset, and per horizontal edge and 32 inputs and PEG arrays can also include optional cas- clock). outputs per vertical edge.A 2ϫ2-PEG ar- cadable RAM blocks of 9 kbits each with The next level of hierarchy is the PEG ray offers a maximum of 640 inputs and both 9- and 18-bit data-interface options (programmable-embedded-gate) array, outputs, whereas a 4ϫ1 equivalent con- and built-in FIFO flag logic. You might an 8ϫ8 matrix of functional groups that tains 704 inputs and outputs. use these RAM structures, for example, Actel estimates represents a multiple-de- The VariCore place-and-route soft- as bridges between ASIC and FPGA log- sign average of 2500 ASIC gates, exclud- ware is parameterized to support multi- ic running at different bus widths and ing RAM. Actel, along with partners ple PEG-matrix sizes and orientations, clock speeds. The company’s future plans Chartered, TSMC, and UMC, initially thereby not forcing the HDL source code also include offering its ProASIC flash plans to offer 2ϫ1, 2ϫ2, 4ϫ2, and 4ϫ4 that you develop at the beginning of the FPGA technology in embedded-IP form.

ADAPTIVE SILICON and ALU-level-mapping capabilities. The Adaptive Silicon’s approach to embed- AT A GLANCE interface between programmable- and ded programmable logic employs an ୴ MSA 2500’s ALU-based logic cell is par- standard-cell partitions comprises a PLC ALU-based logic cell whose heritage ex- ticularly efficient at implementing arith- (programmable-logic-core) control tends back to the days when some of the metic-dominated circuits. structure in the programmable partition ୴ company’s founders were employed by Adaptive Silicon strives to make as few (along with an application-circuit inter- changes as possible to your ASIC design National Semiconductor and developed flow. face) and a matching PLC adapter in the the CLay (Configurable Logic Array) ୴ LSI Logic is ready for production, with ASIC partition. The vendor has 0.18-mi- and NAPA (National Adaptive Process- TSMC and other as-yet-unnamed partners cron test chips in-house from initial part- ing Architecture) FPGAs. The funda- waiting in the wings. ner and investor LSI Logic (which calls its mental building block of Adaptive’s implementation of Adaptive Silicon’s MSA (multiscale-array) 2500 is an en- technology the LiquidLogic core) and hanced 74LS181 4-bit ALU with a mod- 16 Quad Blocks form a Hex Block. TSMC. ular carry-look-ahead scheme and op- Adaptive Silicon estimates that each Adaptive Silicon’s Millennium PLC tional output registering. Four ALUs Hex Block represents an average of 1500 design flow is ASIC-designer-friendly. group to form a Quad Block that con- ASIC gates. The company points out that The synthesis tool set for the program- nects to other Quad Blocks by signal the logic cell can also implement more mable-logic partitions is the same one routing and ALU-control resources, and generic LUT-like functions via both gate- you use for standard-cell-targeted logic:

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Synopsys’ Design Compiler or an equiv- pin test-access port, and multiplexed test ing models, and the like.Adaptive Silicon alent. Adaptive Silicon relies on Design- and data I/O signals. The programma- supports partner LSI Logic’s CoreWare Ware libraries that it developed to per- ble-logic core comprehends full-chip design flow, including the layout-versus- form the necessary translation and scan BIST to ensure programming in- schematic, transistor-level check before architectural optimization of VHDL or tegrity, quiescent power testing, and full- tape-out, even though a dynamically Verilog source code. The registers in each speed testing. configured programmable-logic parti- logic cell, with scan chains throughout Both Adaptive Silicon and competitor tion uses few of the available transistors. the array, aid in silicon verification. Actel strive to seamlessly integrate their The MSA 2500 pricing scheme includes Adaptive Silicon and its ASIC partners embedded FPGA partitions into your a technology-licensing fee that can be as tailor the PLC adapter for each applica- chip’s layout, functional verification, and little as $300,000 and volume-dependent tion with a soft macro that manages the static-timing-analysis flows, with GDS II per-chip royalties. programming and test interfaces, a five- floor-planning layout frames, SDF tim-

AGERE SYSTEMS Among the numerous IP cores available Agere Systems has a multipronged strat- to you from the ASIC division is a Series AT A GLANCE egy for addressing its customers’ needs 4 FPGA macrocell building block com- ୴ Field- and mask-programmable logic for design flexibility. As discussed in the prising 800 logic cells.You can either ful- provides options for different stages in your FPGA section of this directory, the com- ly embed the FPGA macrocell or leave products’ life cycles. pany offers both “pure” programmable- one of the four sides open to external I/O ୴ The Series 4 FPGA core forms the pro- logic devices and ASIC-plus-program- buffers. Integration of multiple embed- grammable foundation of many of Agere’s mable-logic hybrid devices. Mask- ded FPGA blocks is possible, and if FPGA hybrid chips and is available for use in your programmable versions of the company’s logic doesn’t meet your cost or perform- custom designs. ୴ FPGAs give you a cost-reduction path ance requirements and you don’t require Laser-programmable-logic cores might not be user-configurable, but they tend to once your design reaches high produc- ultimate flexibility, you might instead be be more silicon-efficient and offer higher tion volumes. interested in employing the laser-pro- performance than FPGAs, all other factors Agere acts as both a standard product grammable embedded logic cores that being equal. supplier and, through its ASIC group, a Agere offers via a licensing agreement more general-purpose silicon foundry. with Chip Express.

ATMEL version of article at www. As a provider of both FPGAs and ASICs, ednmag.com shows that a AT A GLANCE Atmel (along with Agere Systems) is a range of logic-cell counts and ୴ Embedded cores bring programmable logic to your rarity among programmable-logic sup- associated RAM-array sizes ASICs. ୴ Fine-grained logic-cell and routing structures lead to a pliers. The company not only produces are possible, a reflection of the high degree of design flexibility. FPGAs and FPGA-plus-ASIC hybrid fine-grained AT40K FPGA ar- ୴ FPSLIC (field-programmable system-level-integration- chips of its own, but also supplies em- chitecture that the company circuit) devices are proof of concept of Atmel’s hybrid bedded programmable-logic cores for envisioned embedding from capabilities. your ASIC designs. Table 3 at the Web the beginning.

INTEGRATED CIRCUIT TECHNOLOGY (ICT) company wants you to scatter small PLAs PLA vendor ICT hopes to migrate its AT A GLANCE across the ASIC. programmable AND/OR PAL technolo- ୴ ICT brings timing predictability to the With its embedded cores, ICT is mov- gy to the world of IP cores. The compa- world of embedded programmable logic. ing away from the EEPROM-based tech- ny points out that the portions of a de- ୴ Exponentially growing routing-matrix nology it uses in its stand-alone chips to- sign most likely to change, such as state sizes make the approach uneconomical ward an approach employing SRAM to with large logic densities. machines, control-signal translation, and ୴ SRAM-based configuration allows for store configuration-bit values. Embrac- address decoders, are ideal applications low cost and maximum foundry portability. ing SRAM in this manner enables the for PLAs. ICT isn’t trying to convince company to leverage the most advanced customers to embed large chunks of processes at multiple ASIC vendors and product-term-based logic on their chips. cost-prohibitive, particularly in a glob- foundries. Such an approach would quickly become al-routing-matrix structure. Instead, the

56 edn | August 30, 2001 www.ednmag.com ACRONYMS Abel: Advanced Boolean programmable read-only MSA: multiscale array RQFP: power quad flatpack Equation Language memory MIPS: millions of instructions per RTL: register-transfer level AGP: accelerated graphics port EPROM: erasable programmable second SDF: standard data format ALU: arithmetic-logic unit read-only memory NA: not applicable SDH: synchronous digital ASIC: application-specific inte- ESB: embedded system block NAPA: National Adaptive hierarchy grated circuit ESP: embedded standard Processing Architecture SERDES: serializer/deserializer BGA: ball-grid array product NRE: nonrecurring engineering SLIC: supplemental-logic-and- BIST: built-in self-test FBGA: fine-pitch ball-grid array PAL: interconnect cell BLVDS: bus low-voltage FC: fibre channel PBGA: plastic ball-grid array SMPTE: Society of Motion differential signaling FCBGA: flip-chip ball-grid array PBGAM: plastic ball-grid array, Picture and Television Engineers BQFP: bumpered quad flatpack FEC: forward error correction multilayer SOIC: small-outline integrated CABGA: ceramic ball-grid array FG: fine-pitch ball-grid array PCI: Peripheral Component circuit CAM: content-addressable FIFO: first in/first out Interconnect SONET: synchronous-optical memory FPBGA: fine-pitch ball-grid array PCM: programmable clock network CDIP: ceramic dual inline FPGA: field-programmable gate manager SOP: small-outline package package array PDIP: plastic dual inline package SPLD: simple programmable- CDR: clock and data recovery FPSC: field-programmable sys- PECL: positive emitter-coupled logic device CG: plastic ball-grid array tem chip logic SQFP: shrink quad flatpack CLay: configurable logic array FPSLIC: field-programmable sys- PEG: programmable embedded SQFP2: power shrink quad CLB: configurable logic block tem-level integration circuit gate flatpack CLCC: ceramic leadless chip GTL: Gunning transceiver logic PFU: programmable function SRAM: static random-access carrier HDL: hardware-description unit memory CPGA: ceramic pin-grid array language PGA: pin-grid array SSOP: shrink small-outline CPLD: complex programmable- HQ: high-heat-dissipation quad PLA: programmable-logic array package logic device flatpack PLC: programmable-logic core SSTL: stub-series-terminated CPU: HSTL: high-speed transceiver PLCC: plastic leaded chip carrier logic CQFP: ceramic quad flatpack logic PLD: programmable-logic device TPA: tiny PEEL arrays

CS: chip scale IEEE: Institute of Electrical and (product-term-based) TPD: propagation-delay time CSOC: configurable system on Electronics Engineers PLICE: programmable low- TQ: thin quad flatpack chip I/O: input/output impedance circuit element TQFP: thin quad flatpack CSP: chip-scale package IP: intellectual property PLL: phase-locked loop TSSOP: thin shrink small-outline DIP: dual in-line package ISP: in-system programmable PROM: programmable read-only package DLL: digital delay-locked loop JTAG: Joint Test Action Group memory UART: universal asynchronous DMA: direct-memory access LAB: logic-array block PQ: plastic quad flatpack receiver-transmitter DRAM: dynamic random-access LQFP: low-profile quad flatpack PQFP: plastic quad flatpack VHDL: very-high-speed integrat- memory LUT: look-up table PSD: programmable system ed-circuit hardware-description DSP: digital-signal processor LVCMOS: low-voltage comple- device language DVB: digital-video broadcasting mentary metal-oxide semicon- PSI: programmable serial VQFP: very thin quad flatpack EAB: embedded array block ductor interface VTQFP: very thin quad flatpack EBGA: enhanced ball-grid array LVDS: low-voltage differential QDR: quad data rate XAUI: extended attachment-unit ECU: embedded computational signaling QFP: quad flatpack interface unit LVPECL: low-voltage positive RAM: random-access memory XNF: Xilinx Netlist Format EDIF: electronic-design-interop- emitter-coupled logic RISC: reduced-instruction-set erability format LVTTL: low-voltage transistor-to- EEPROM: electrically erasable transistor logic ROM: read-only memory

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