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UNIT-III Design of Combinational Circuits Using Programmable Logic Devices (Plds)

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UNIT-III Design of Combinational Circuits Using Programmable Logic Devices (Plds) UNIT-III Design of combinational circuits using Programmable Logic Devices (PLDs) PLA- Programmable logic array: • The PLA consists of two programmable planes AND and OR . The AND plane consists of programmable interconnect along with AND gates. • The OR plane consists of programmable interconnect along with OR gates. • Each of the inputs can be connected to an AND gate with any of the other inputs by connecting the crossover point of the vertical and horizontal interconnect lines in the AND gate programmable interconnect. • Initially, the crossover points are not electrically connected, but configuring the PLA will connect particular cross over points together. • The AND gate is seen with a single line to the input. This view is by convention, but this also means that any of the inputs (vertical lines) can be connected. Hence, for four PLA inputs, the AND gate also has four inputs. The single output from each of the AND gates is applied to an OR gate programmable inter connect. EXAMPLES: Steps to program PLA: Step I: Find the Boolean Function from the truth table. A B C Y1 Y2 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 1 1 1 1 0 0 0 1 1 1 1 1 Y1=AC+BC Y2=AC+A’BC’ STEP II: Identify the number of input buffers. Number of variables=number of input buffers=3. STEP III: Implementation of the Boolean function in PLA. PROGRAMMABLE ARRAY LOGIC (PAL) • The first programmable device was the programmable array logic (PAL) developed by Monolithic Memories Inc(MMI). • The Programmable Array Logic or PAL is similar to PLA, but in a PAL device only AND gates are programmable. The OR array is fixed by the manufacturer. • This makes PAL devices easier to program and less expensive than PLA. On the other hand, since the OR array is fixed, it is less flexible than a PLA device • The PAL device has n input lines which are fed to buffers/inverters.Buffers/inverters are connected to inputs of AND gates through programmable links. Outputs of AND gates are then fed to the OR array with fixed connections. EXAMPLES X=F(A,B,C)=∑m(2,3,6,7) Y= F(A,B,C)= ∑m(0,2,3,5) Z= F(A,B,C)= ∑m(1,6,7) Complex Programmable Logic Devices (CPLDs) • CPLDs were pioneered by Altera, first in their family of chips called Classic EPLDs, and then in three additional series, called MAX 5000, MAX 7000 and MAX 9000. • The CPLD is the complex programmable Logic Device which is more complex than the SPLD. • This is build on SPLD architecture and creates a much larger design. Consequently, the SPLD can be used to integrate the functions of a number of discrete digital ICs into a single device and the CPLD can be used to integrate the functions of a number of SPLDs into a single device. • CPLD architecture is based on a small number of logic blocks and a global programmable interconnect. • Instead of relying on a programming unit to configure chip , it is advantageous to be able to perform the programming while the chip is still attached to its circuit board. • This method of programming is known is called In-System programming (ISP). It is not usually provided for PLAs (or) PALs , but it is available for the more sophisticated chips known as Complex programmable logic device. • • The CPLD consists of a number of logic blocks or functional blocks, each of which contains a macrocell and either a PLA or PAL circuit arrangement. • • In the diagram eight logic blocks are shown. The building block of the CPLD is the macro-cell, which contains logic implementing disjunctive normal form expressions and more specialized logic operations. • • The macro cell provides additional circuitry to accommodate registered or nonregistered outputs, along with signal polarity control. • • Polarity control provides an output that is a true signal or a complement of the true signal. • • The actual number of logic blocks within a CPLD varies ,the more logic blocks available, the larger the design that can be configured. • • In the center of the design is a global programmable interconnect. • • This interconnect allows connections to the logic block macrocells and the I/O cell arrays (the digital I/O cells of the CPLD connecting to the pins of the CPLD package). • • The programmable interconnect is usually based on either array-based interconnect or multiplexer-based interconnect. • Multiplexer-based interconnect uses digital multiplexers connected to each of the macrocell inputs within the logic blocks. • Specific signals within the programmable interconnect are connected to specific inputs of the multiplexers. • It would not be practical to connect all internal signals within the programmable interconnect to the inputs of all multiplexers due to size and speed of operation considerations. FIELD PROGRAMMABLE GATE ARRAYS • The concept of FPGA was emerged in 1985 with the XC2064TM FPGA family from Xilinx . • The “FPGA is an integrated circuit that contains many (64 to over 10,000) identical logic cells that can be viewed as standard components.” • The individual cells are interconnected by a matrix of wires and programmable switches. • Unlike CPLDs (Complex Programmable Logic Devices) FPGAs contain neither AND nor OR planes. • The FPGA architecture consists of configurable logic blocks, configurable I/O blocks, and programmable interconnect. • Also, there will be clock circuitry for driving the clock signals to each logic block, and additional logic resources such as ALUs, memory, and decoders may be available. • The two basic types of programmable elements for an FPGA are Static RAM and anti-fuses. • Each logic block in an FPGA has a small number of inputs and one output. • A look up table (LUT) is the most commonly used type of logic block used within FPGAs. • There are two types of FPGAs.(i) SRAM based FPGAs and (ii) Anti-fuse technology based(OTP). Every FPGA consists of the following elements. • Configurable logic blocks(CLBs) • Configurable input output blocks(IOBs) • Two layer metal network of vertical and horizontal lines for interconnecting the CLBS. Which are called Programmable Interconnects. An individual CLB is made up of several logic blocks. A lookup table (LUT) is a characteristic feature of an FPGA. An LUT stores a predefined list of logic outputs for any combination of inputs: LUTs with four to six input bits are widely used. Standard logic functions such as multiplexers (mux), full adders (FAs) and flip-flops are also common. The number and arrangement of components in the CLB varies by device; the simplified example in Figure 2 contains two three-input LUTs (1), an FA (3) and a D-type flip-flop (5), plus a standard mux (2) and two muxes, (4) and (6), that are configured during FPGA programming. Overview of Look Up Tables (LUT) One of the features which make FPGA families differ from each other is their logic resource. For example, each CLB of Spartan-II FPGAs (PDF) is comprised of two slices, each with two LUTs. The Spartan 6 (PDF) has two slices with four LUTs each. Internally, LUTs comprise of 1-bit memory cells (programmable to hold either ‘0’ or ‘1’) and a set of multiplexers. One value among these SRAM bits will be available at the LUT’s output depending on the value(s) fed to the control line(s) of the multiplexer(s). The number of inputs available for a LUT determine its size. In general, a LUT with n inputs is seen to comprise of 2n single-bit memory cells followed by a 2n:1 multiplexer or its equivalent (say, two 2n-1:1 muxes followed by one 2:1 mux). 2-Input Look up table (LUT’s): A specific example of a 2-input LUT comprising of 4 SRAM bits and a 4:1 mux is as shown in Figure 2a. Next, Figure 2b shows its equivalent architecture but represents a 4:1 mux as a tree of 2:1 muxes. 3-Input Look up table (LUT’s): Suppose we want to realize a Boolean Function of four input variables A, B, C and D using a 3-input LUT. Here, let the output become high only when any of the two input variables are one. The truth table corresponding to this is shown below. While realizing this function using an FPGA, A, B, C, and D will be the inputs to LUT. Next, the values of the output variable for each of their combination (available in the last column of the truth table) will be stored in the SRAM cells. Now, if ABCD = 0101, then the output of the LUT, Y, will take the value of 1 as the content of the sixth memory cell makes its way to the output pin. Here, two 3-input LUTs share the same set of three lower-significant inputs (B, C, and D). The output from any one of these LUTs is routed onto the Y output bit (shown by a red discontinuous line) using a 2:1 mux whose select line will be our fourth variable, A (MSB).In this illustration, the last 2:1 mux is considered to be the multiplexer present within the slice constituting the CLB. Implementing a 4-input Boolean function using a combination of 3-input LUTs and a Mux Introduction to Verilog HDL High-level language constructs to describe the functionality and connectivity of the circuit • Can describe a design at some levels of abstraction. An HDL might describe the layout of the wires, resistors and transistors on an Integrated Circuit (IC) chip, i.
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