University of Texas at El Paso DigitalCommons@UTEP Open Access Theses & Dissertations 2013-01-01 Asynchronous Logic Design With Increased Fault Tolerance And Optimized For Subthreshold Operation Ivan Santos University of Texas at El Paso,
[email protected] Follow this and additional works at: https://digitalcommons.utep.edu/open_etd Part of the Computer Engineering Commons, and the Electrical and Electronics Commons Recommended Citation Santos, Ivan, "Asynchronous Logic Design With Increased Fault Tolerance And Optimized For Subthreshold Operation" (2013). Open Access Theses & Dissertations. 1727. https://digitalcommons.utep.edu/open_etd/1727 This is brought to you for free and open access by DigitalCommons@UTEP. It has been accepted for inclusion in Open Access Theses & Dissertations by an authorized administrator of DigitalCommons@UTEP. For more information, please contact
[email protected]. ASYNCHRONOUS LOGIC DESIGN WITH INCREASED FAULT TOLERANCE AND OPTIMIZED FOR SUBTHRESHOLD OPERATION IVAN SANTOS Department of Electrical and Computer Engineering APPROVED: Eric MacDonald, Ph.D., Chair David A. Roberson, Ph.D. John Moya, Ph.D. Benjamin C. Flores, Ph.D. Dean of the Graduate School Copyright © by Ivan Santos 2013 Dedication This thesis is dedicated to my beloved family. ASYNCHRONOUS LOGIC DESIGN WITH INCREASED FAULT TOLERANCE AND OPTIMIZED FOR SUBTHRESHOLD OPERATION by IVAN SANTOS, B. S. E. E. THESIS Presented to the Faculty of the Graduate School of The University of Texas at El Paso in Partial Fulfillment of the Requirements for the Degree of MASTER OF SCIENCE Department of Electrical and Computer Engineering THE UNIVERSITY OF TEXAS AT EL PASO December 2013 Acknowledgements I owe my most sincere gratitude to my graduate research advisor Dr.