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  • Gigaplane-XB: Extending the Ultra Enterprise Family
    Gigaplane-XB: Extending the Ultra Enterprise Family Alan Charlesworth ([email protected]), Andy Phelps, Ricki Williams, Gary Gilbert Sun Microsystems, Inc. Abstract The Gigaplane-XB interconnect of the Starfire system extends the range of Sun’s Ultra Enterprise SMP server family by 4x. It uses multi-level address and data routers to provide 167 million global snoops per second, and 10,667 MBps of uniform-memory-access band- width. The use of point-to-point routers allows the system to be dynamically reconfigured into multiple hardware-protected operating system domains, with hot-swappable boards. Comparisons are made with the bus-based technology of the smaller family members. 1. Introduction Table 1 compares the memory-port architectures of cur- rent microprocessors. A combination of a 16-byte wide When a new processor debuts, we hear mostly about its data path, a 100 MHz system clock, and separate address SPECint95 and SPECfp95 performance. It is probably and data paths has made Sun’s Ultra Port Architecture more important to know how well a processor’s power is (UPA) among the highest-bandwidth memory ports. The balanced its memory bandwidth and latency. From a sys- UPA is used across all Sun’s UltraSPARC systems: from tem designer’s perspective, the main reason to have an desktop workstations to the 64-processor Starfire instruction set architecture is to get the opportunity to (UltraEnterprise/High Performance Computing 10000) engineer into the processor chip a good interconnect server. architecture. Table 1. Memory-port characteristics. Max Data Separate Data Peak data Instruction set Interconnect Current CPU Port width address duty bandwidth architecture architecture model MHz (bytes) and data? factor (MBps) SPARC UPA [9] UltraSPARC-II 100 16 Yes 100% 1,600 Alpha See [3] 21164 88 16 Yes 100% 1,408 Mips Avalanche [18] R10000 100 8 No 84% 840 PA-RISC Runway [1] PA-8000 120 8 No 80% 768 PowerPC See [2] PPC 604 67 8 Yes 100% 533 Pentium Pro/II See [5] Pentium Pro/II 67 8 Yes 100% 533 2.
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  • Hieroglyphs for the Information Age: Images As a Replacement for Characters for Languages Not Written in the Latin-1 Alphabet Akira Hasegawa
    Rochester Institute of Technology RIT Scholar Works Theses Thesis/Dissertation Collections 5-1-1999 Hieroglyphs for the information age: Images as a replacement for characters for languages not written in the Latin-1 alphabet Akira Hasegawa Follow this and additional works at: http://scholarworks.rit.edu/theses Recommended Citation Hasegawa, Akira, "Hieroglyphs for the information age: Images as a replacement for characters for languages not written in the Latin-1 alphabet" (1999). Thesis. Rochester Institute of Technology. Accessed from This Thesis is brought to you for free and open access by the Thesis/Dissertation Collections at RIT Scholar Works. It has been accepted for inclusion in Theses by an authorized administrator of RIT Scholar Works. For more information, please contact [email protected]. Hieroglyphs for the Information Age: Images as a Replacement for Characters for Languages not Written in the Latin- 1 Alphabet by Akira Hasegawa A thesis project submitted in partial fulfillment of the requirements for the degree of Master of Science in the School of Printing Management and Sciences in the College of Imaging Arts and Sciences of the Rochester Institute ofTechnology May, 1999 Thesis Advisor: Professor Frank Romano School of Printing Management and Sciences Rochester Institute ofTechnology Rochester, New York Certificate ofApproval Master's Thesis This is to certify that the Master's Thesis of Akira Hasegawa With a major in Graphic Arts Publishing has been approved by the Thesis Committee as satisfactory for the thesis requirement for the Master ofScience degree at the convocation of May 1999 Thesis Committee: Frank Romano Thesis Advisor Marie Freckleton Gr:lduate Program Coordinator C.
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  • NESO LT Core Block Diagram NESO LT CPU Type I.MX 257 Core Class ARM 926
    TECHNICAL SPECIFICATION SOLUTIONS THAT COMPLETE! NESO LT Single Board Computer CPU RS-485 CAN NESO LT core Block Diagram NESO LT CPU Type i.MX 257 Core Class ARM 926 ARM 9 Single Board Computer Driver Core Clock 400 MHz 24V/Digital Out i.MX25 4-pole Molex Features 16 KB for Instruktion and data caches Step Down Converter RTC Accuracy: +/- 30 ppm at 25°C GPIO2 DISP0 DAT0 Display RGB Memory 40-pole FFC PMIC Power TSC NAND Flash 256MByte NAND Flash RAM Standard 128 MByte DDR-SDRAM PWM-1 Backlight Battery GPIO-2 Driver Micro SD Card Slot 4 bit MicroSD (HC) CR1220 Operating Systems Battery Supported OS Windows CE 6.0, Linux Yocto PCT Interface RTC RC 1 I2C-3 6-pole FFC Communication Interfaces Digital I/O 1x Digital Out (0.7 A) RS-232 UART-1 Transceiver USBPHY1 Internal USB Network 1x 10/100 Mbit/s Ethernet (RJ-45) 5-pole STL RS-232/RS-485 RS-485 / CAN Fieldbus 1x RS-485 (Half 1x CAN (ISO/DIS 12-pole Molex RS-485 UART-3 duplex) 11898) Transceiver USB-OTG USBPHY1 RS-232 1x RS-232 (RX/TX/CTS/RTS) Flex Type AB CAN CAN Synchronous SPI (10 MBit/s) up to 12 chip selects; I²C, Keypad Keypad USB Serial Interfaces Matrix keypad up to 8 x 8 USBPHY2 20-pole JST Port Type A High-Speed USB 2.0 1x 12 Mbit/s Full Speed Host Micro-SD-Card 1x 480 Mbit/s High Speed OTG ESDHC2 Internal Audio Connector 10-pole Molex Audio Speaker output 1x speaker (connector), 1.0 W RMS (8Ω) UART-4 Audio I2C-2 S/PDIF AUDMUX Expansion Audio Internal 1x speaker connectors parallel to external Codec SPI1 30-pole FFC ESDHC2 output, Line In, Line Out, MIC In owire_LINE Display and Touch Line Out Display Interface TTL up to 24 bit (RGB) Audio EIM SDRAM Touch Interface 4-wire analog resistive; PCAP I²C 2x Speaker Amplifier 2-pole JST NAND Backlight Interface 42.5 mA Backlight drives EMI NANDF Flash Device Dimensions RJ-45 Ethernet W x H x D 113.8 x 18.0 x 47.3 mm FEC Jack Phy Weight 51g Power Supply Supply Voltage Nom.
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  • IO-Link Instead of Fieldbus
    APPLICATIONS SENSOR TECHNOLOGY IO-Link Instead of Fieldbus Laempe Mössner Sinto GmbH uses IO-Link in a new core shooter machine and achieves shorter cycle times with Turck’s QR24-IOL IO-Link encoder “When I first read about it, I thought: please don’t add the few manufacturers of core shooters worldwide. The another fieldbus system. Today I know that IO-Link isn’t machines produce sand cores for metal casting. If, for a fieldbus but quite the opposite. In many areas, example, the casting of an engine block is required, IO-Link means for us the end of bus systems because it cores are placed inside the casting mold to later makes communication simple once again,” explains produce the cavities of the engine. The cores are “shot” Tobias Lipsdorf, controller programmer at foundry from a binder sand mixture with compressed air into a machinery manufacturer Laempe Mössner Sinto mold – the core box – at a high speed between 0.3 and GmbH. When the engineer talks about the IO-Link 0.5 seconds. The mold mixture is then hardened in the intelligent communication standard, you get a sense of closed core box using process gas or heat and can then genuine enthusiasm – so too with his colleague Andre be removed. After casting, the binder loses its hard- Klavehn, who is responsible for the electrical planning. ness due to the heat from the filled melt. The cores The two of them jointly redesigned the electrical disintegrate, the sand can be removed from the cast, planning of the new machine generation and imple- leaving behind the required internal contour.
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  • Active@ UNDELETE Documentation
    Active @ UNDELETE Users Guide | Contents | 2 Contents Legal Statement.........................................................................................................5 Active@ UNDELETE Overview............................................................................. 6 Getting Started with Active@ UNDELETE.......................................................... 7 Active@ UNDELETE Views And Windows...................................................................................................... 7 Recovery Explorer View.......................................................................................................................... 8 Logical Drive Scan Result View..............................................................................................................9 Physical Device Scan View......................................................................................................................9 Search Results View...............................................................................................................................11 File Organizer view................................................................................................................................ 12 Application Log...................................................................................................................................... 13 Welcome View........................................................................................................................................14 Using
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  • (12) United States Patent (10) Patent No.: US 8,965,180 B2 Knight Et Al
    USOO89651 80B2 (12) United States Patent (10) Patent No.: US 8,965,180 B2 Knight et al. (45) Date of Patent: *Feb. 24, 2015 (54) SYSTEMS AND METHODS FOR 21/4884 (2013.01); H04N 2 1/84 (2013.01); CONVERTING INTERACTIVE MULTIMEDIA H04L 65/602 (2013.01); G1 I B2220/2562 CONTENT AUTHORED FOR DISTRIBUTION (2013.01) VIAA PHYSICAL MEDIUM FOR USPC .......................................................... 386/282 ELECTRONIC DISTRIBUTION (58) Field of Classification Search USPC ......... 386/278, 279, 280, 281, 282,283, 284, (75) Inventors: Anthony David Knight, San Jose, CA 386/285, 290 (US); Ian Michael Lewis, Oxfordshire See application file for complete search history. (GB); Andrew Maurice Devitt, London (GB) (56) References Cited (73) Assignee: Rovi Guides, Inc., Santa Clara, CA (US) U.S. PATENT DOCUMENTS 4,838,843. A 6, 1989 Westhoff (*) Notice: Subject to any disclaimer, the term of this 5,313,881 A 5/1994 Morgan patent is extended or adjusted under 35 U.S.C. 154(b) by 66 days. (Continued) This patent is Subject to a terminal dis FOREIGN PATENT DOCUMENTS claimer. EP O865.362 B1 T 2003 (21) Appl. No.: 13/182,376 JP 2001344828 12/2001 (Continued) (22) Filed: Jul. 13, 2011 OTHER PUBLICATIONS (65) Prior Publication Data Apple Inc., "iTunes Extra iTunes LP Development: Template How US 2012/OO 14674 A1 Jan. 19, 2012 To v1.1”. Jan. 26, 2010, 58 pgs. (Continued) Related U.S. Application Data Primary Examiner — Tat Chio (60) Provisional application No. 61/364,001, filed on Jul. (74) Attorney, Agent, or Firm — Ropes & Gray LLP 13, 2010. (57) ABSTRACT (51) Int.
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  • Sun Ultratm 5 Workstation Just the Facts
    Sun UltraTM 5 Workstation Just the Facts Copyrights 1999 Sun Microsystems, Inc. All Rights Reserved. Sun, Sun Microsystems, the Sun logo, Ultra, PGX, PGX24, Solaris, Sun Enterprise, SunClient, UltraComputing, Catalyst, SunPCi, OpenWindows, PGX32, VIS, Java, JDK, XGL, XIL, Java 3D, SunVTS, ShowMe, ShowMe TV, SunForum, Java WorkShop, Java Studio, AnswerBook, AnswerBook2, Sun Enterprise SyMON, Solstice, Solstice AutoClient, ShowMe How, SunCD, SunCD 2Plus, Sun StorEdge, SunButtons, SunDials, SunMicrophone, SunFDDI, SunLink, SunHSI, SunATM, SLC, ELC, IPC, IPX, SunSpectrum, JavaStation, SunSpectrum Platinum, SunSpectrum Gold, SunSpectrum Silver, SunSpectrum Bronze, SunVIP, SunSolve, and SunSolve EarlyNotifier are trademarks, registered trademarks, or service marks of Sun Microsystems, Inc. in the United States and other countries. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. in the United States and other countries. Products bearing SPARC trademarks are based upon an architecture developed by Sun Microsystems, Inc. UNIX is a registered trademark in the United States and other countries, exclusively licensed through X/Open Company, Ltd. OpenGL is a registered trademark of Silicon Graphics, Inc. Display PostScript and PostScript are trademarks of Adobe Systems, Incorporated, which may be registered in certain jurisdictions. Netscape is a trademark of Netscape Communications Corporation. DLT is claimed as a trademark of Quantum Corporation in the United States and other countries. Just the Facts May 1999 Positioning The Sun UltraTM 5 Workstation Figure 1. The Ultra 5 workstation The Sun UltraTM 5 workstation is an entry-level workstation based upon the 333- and 360-MHz UltraSPARCTM-IIi processors. The Ultra 5 is Sun’s lowest-priced workstation, designed to meet the needs of price-sensitive and volume-purchase customers in the personal workstation market without sacrificing performance.
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  • Active @ UNDELETE Users Guide | TOC | 2
    Active @ UNDELETE Users Guide | TOC | 2 Contents Legal Statement..................................................................................................4 Active@ UNDELETE Overview............................................................................. 5 Getting Started with Active@ UNDELETE........................................................... 6 Active@ UNDELETE Views And Windows......................................................................................6 Recovery Explorer View.................................................................................................... 7 Logical Drive Scan Result View.......................................................................................... 7 Physical Device Scan View................................................................................................ 8 Search Results View........................................................................................................10 Application Log...............................................................................................................11 Welcome View................................................................................................................11 Using Active@ UNDELETE Overview................................................................. 13 Recover deleted Files and Folders.............................................................................................. 14 Scan a Volume (Logical Drive) for deleted files..................................................................15
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  • Dell EMC Poweredge T340 Technical Guide
    Dell EMC PowerEdge T340 Technical Guide Regulatory Model: E60S Regulatory Type: E60S001 Dec. 2020 Rev. A07 Notes, cautions, and warnings NOTE: A NOTE indicates important information that helps you make better use of your product. CAUTION: A CAUTION indicates either potential damage to hardware or loss of data and tells you how to avoid the problem. WARNING: A WARNING indicates a potential for property damage, personal injury, or death. © 2018 - 2020 Dell Inc. or its subsidiaries. All rights reserved. Dell, EMC, and other trademarks are trademarks of Dell Inc. or its subsidiaries. Other trademarks may be trademarks of their respective owners. 1 Product Overview Topics: • Introduction • New technologies Introduction The Dell EMC PowerEdge T340 is the reliable, easy to manage, and scalable 1-socket tower server for growing businesses and remote offices/ branch offices. New technologies The PowerEdge T340 equipped with Intel® Xeon® E-2100 and E-2200 product family processors support to help run applications faster and support for full-feature remote management (iDRAC9). The T340 is versatile enough to address many customer segments and workloads. Target workloads include ● Small and medium businesses and organizations: Collaboration/sharing productivity applications, databases, web serving, backup/recovery, and mail and messaging. ● ROBO: Applications and workloads specific to the particular industry, e.g. Retail, Healthcare, Finance, Education, etc. The following table shows the list of new technologies offered by the PowerEdge T340: New Technologies Detailed Descriptions Intel® C246 series chipset Please refer to the chipset section for details. Intel® Xeon® processor E- 2100 and E-2200 Product The Intel® processor that works with Intel® C246 series Family chipset.
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  • SUPPORTING the CHINESE, JAPANESE, and KOREAN LANGUAGES in the OPENVMS OPERATING SYSTEM by Michael M. T. Yau ABSTRACT the Asian L
    SUPPORTING THE CHINESE, JAPANESE, AND KOREAN LANGUAGES IN THE OPENVMS OPERATING SYSTEM By Michael M. T. Yau ABSTRACT The Asian language versions of the OpenVMS operating system allow Asian-speaking users to interact with the OpenVMS system in their native languages and provide a platform for developing Asian applications. Since the OpenVMS variants must be able to handle multibyte character sets, the requirements for the internal representation, input, and output differ considerably from those for the standard English version. A review of the Japanese, Chinese, and Korean writing systems and character set standards provides the context for a discussion of the features of the Asian OpenVMS variants. The localization approach adopted in developing these Asian variants was shaped by business and engineering constraints; issues related to this approach are presented. INTRODUCTION The OpenVMS operating system was designed in an era when English was the only language supported in computer systems. The Digital Command Language (DCL) commands and utilities, system help and message texts, run-time libraries and system services, and names of system objects such as file names and user names all assume English text encoded in the 7-bit American Standard Code for Information Interchange (ASCII) character set. As Digital's business began to expand into markets where common end users are non-English speaking, the requirement for the OpenVMS system to support languages other than English became inevitable. In contrast to the migration to support single-byte, 8-bit European characters, OpenVMS localization efforts to support the Asian languages, namely Japanese, Chinese, and Korean, must deal with a more complex issue, i.e., the handling of multibyte character sets.
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  • Comptia A+ Acronym List Core 1 (220-1001) and Core 2 (220-1002)
    CompTIA A+ Acronym List Core 1 (220-1001) and Core 2 (220-1002) AC: Alternating Current ACL: Access Control List ACPI: Advanced Configuration Power Interface ADF: Automatic Document Feeder ADSL: Asymmetrical Digital Subscriber Line AES: Advanced Encryption Standard AHCI: Advanced Host Controller Interface AP: Access Point APIPA: Automatic Private Internet Protocol Addressing APM: Advanced Power Management ARP: Address Resolution Protocol ASR: Automated System Recovery ATA: Advanced Technology Attachment ATAPI: Advanced Technology Attachment Packet Interface ATM: Asynchronous Transfer Mode ATX: Advanced Technology Extended AUP: Acceptable Use Policy A/V: Audio Video BD-R: Blu-ray Disc Recordable BIOS: Basic Input/Output System BD-RE: Blu-ray Disc Rewritable BNC: Bayonet-Neill-Concelman BSOD: Blue Screen of Death 1 BYOD: Bring Your Own Device CAD: Computer-Aided Design CAPTCHA: Completely Automated Public Turing test to tell Computers and Humans Apart CD: Compact Disc CD-ROM: Compact Disc-Read-Only Memory CD-RW: Compact Disc-Rewritable CDFS: Compact Disc File System CERT: Computer Emergency Response Team CFS: Central File System, Common File System, or Command File System CGA: Computer Graphics and Applications CIDR: Classless Inter-Domain Routing CIFS: Common Internet File System CMOS: Complementary Metal-Oxide Semiconductor CNR: Communications and Networking Riser COMx: Communication port (x = port number) CPU: Central Processing Unit CRT: Cathode-Ray Tube DaaS: Data as a Service DAC: Discretionary Access Control DB-25: Serial Communications
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  • 3. System Management Bus
    Input/Output Systems and Peripheral Devices 1 3. SYSTEM MANAGEMENT BUS This laboratory work presents the System Management Bus (SMBus). After an over- view of SMBus, bit and data transfers are described, the bus arbitration procedure is present- ed, the differences between SMBus and the I2C bus are highlighted, and several command protocols are detailed. Next, the Intel SMBus controller is presented, including its registers and commands, as well as its use with I2C devices. The applications aim to detect the devices connected to the computer’s SMBus, read the contents of SPD memories present in the sys- tem, and decode the contents of these memories. 3.1. Overview of SMBus System Management Bus (SMBus) is a simple serial bus with only two signal lines. This bus can be used for communication between various system devices and between these devices and the rest of a system. The operating principles of SMBus are similar to those of the I2C bus. There are, however, several differences between the two buses, differences which will be presented later. SMBus represents a control bus for system management and power management op- erations. A system may use the SMBus to transfer messages to and from various devices in- stead of using individual control lines, which allows to reduce pin count and interconnection wires. A device may use the SMBus to provide manufacturer information, provide the device model number, report different types of errors, accept control parameters, and return the de- vice status. SMBus was initially proposed by Intel as a link between an intelligent battery, a charger for the battery and a microcontroller that communicates with the rest of the system.
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