EE 372 Digital Logic Families

Deborah Won Department of Electrical and Computer Engineering California State University, Los Angeles

Winter 2015 Outline

Digital Logic Definition

Digital IC Design Issues

Bipolar Transistor Logic Families

CMOS circuits e.g., the AND operation A B Y = A · B 0 0 0 0 1 0 1 0 0 1 1 1

Digital Logic

Digital logic = Binary arithmetic performed by transistor circuits. The output represents whether a particular condition, or input state, is TRUE or FALSE. Digital Logic

Digital logic = Binary arithmetic performed by transistor circuits. The output represents whether a particular condition, or input state, is TRUE or FALSE. e.g., the AND operation A B Y = A · B 0 0 0 0 1 0 1 0 0 1 1 1 → acts like a transistor control voltage.

Remember: We can get a transistor to act like an ON/OFF switch by forcing the transistor to operate either in its 1. saturation region 2. cutoff region

Logic Gate

These inputs A and B are actually the input voltage applied to the base of a transistor (or gate for MOS transistor) 2. cutoff region

Logic Gate

These inputs A and B are actually the input voltage applied to the base of a transistor (or gate for MOS transistor) → acts like a transistor control voltage.

Remember: We can get a transistor to act like an ON/OFF switch by forcing the transistor to operate either in its 1. saturation region Logic Gate

These inputs A and B are actually the input voltage applied to the base of a transistor (or gate for MOS transistor) → acts like a transistor control voltage.

Remember: We can get a transistor to act like an ON/OFF switch by forcing the transistor to operate either in its 1. saturation region 2. cutoff region A digital IC which produces a logical state (“0” or “1”) at the output based on the logical state of the inputs.

Elementary Logic Functions

A Y NOT gate (or inverter) 0 1 1 0

What is a gate? Elementary Logic Functions

A Y NOT gate (or inverter) 0 1 1 0

What is a gate? A digital IC which produces a logical state (“0” or “1”) at the output based on the logical state of the inputs. Elementary Logic Functions

A B Y A B Y 0 0 0 0 0 1 AND 0 1 0 NAND 0 1 1 1 0 0 1 0 1 1 1 1 1 1 0 0 0 0 0 0 1 0 1 1 0 1 0 OR NOR 1 0 1 1 0 0 1 1 1 1 1 0 0 0 0 0 0 1 0 1 1 0 1 0 XOR XNOR 1 0 1 1 0 0 1 1 0 1 1 1 Important Boolean Algebra Identities

1. A + 0 = A 2. A + A¯ = 1 3. A · 0 = 0 4. A · 1 = A 5. A · A = A 6. A · A¯ = 0 7. Associative Law for Addition A + (B + C) = (A + B) + C 8. Associative Law for Multiplication A(BC) = (AB)C 9. DeMorgan’s Theorem for Addition A + B = A¯B¯ 10. DeMorgan’s Theorem for Multiplication ABC = A¯ + B¯ + C¯ Outline

Digital Logic Definition

Digital IC Design Issues

Bipolar Transistor Logic Families

CMOS circuits I many circuits can be etched on the same silicon wafer

I the silicon wafer is divided and cut into “chips” (ICs)

I the chips are protected inside electrically insulating but heat-conducting packages (usually ceramic or plastic)

I the input and output lines are connected to bonding pads which are electrically connected to pins on the package

I these pins are the chip’s connection to the outside world

I different chips can have pins in different arrangements

IC Packaging

I digital logic is made up of transistors which are fabricated (made) in silicon I the silicon wafer is divided and cut into “chips” (ICs)

I the chips are protected inside electrically insulating but heat-conducting packages (usually ceramic or plastic)

I the input and output lines are connected to bonding pads which are electrically connected to pins on the package

I these pins are the chip’s connection to the outside world

I different chips can have pins in different arrangements

IC Packaging

I digital logic is made up of transistors which are fabricated (made) in silicon

I many circuits can be etched on the same silicon wafer I the chips are protected inside electrically insulating but heat-conducting packages (usually ceramic or plastic)

I the input and output lines are connected to bonding pads which are electrically connected to pins on the package

I these pins are the chip’s connection to the outside world

I different chips can have pins in different arrangements

IC Packaging

I digital logic is made up of transistors which are fabricated (made) in silicon

I many circuits can be etched on the same silicon wafer

I the silicon wafer is divided and cut into “chips” (ICs) I the input and output lines are connected to bonding pads which are electrically connected to pins on the package

I these pins are the chip’s connection to the outside world

I different chips can have pins in different arrangements

IC Packaging

I digital logic is made up of transistors which are fabricated (made) in silicon

I many circuits can be etched on the same silicon wafer

I the silicon wafer is divided and cut into “chips” (ICs)

I the chips are protected inside electrically insulating but heat-conducting packages (usually ceramic or plastic) I these pins are the chip’s connection to the outside world

I different chips can have pins in different arrangements

IC Packaging

I digital logic is made up of transistors which are fabricated (made) in silicon

I many circuits can be etched on the same silicon wafer

I the silicon wafer is divided and cut into “chips” (ICs)

I the chips are protected inside electrically insulating but heat-conducting packages (usually ceramic or plastic)

I the input and output lines are connected to bonding pads which are electrically connected to pins on the package I different chips can have pins in different arrangements

IC Packaging

I digital logic is made up of transistors which are fabricated (made) in silicon

I many circuits can be etched on the same silicon wafer

I the silicon wafer is divided and cut into “chips” (ICs)

I the chips are protected inside electrically insulating but heat-conducting packages (usually ceramic or plastic)

I the input and output lines are connected to bonding pads which are electrically connected to pins on the package

I these pins are the chip’s connection to the outside world IC Packaging

I digital logic is made up of transistors which are fabricated (made) in silicon

I many circuits can be etched on the same silicon wafer

I the silicon wafer is divided and cut into “chips” (ICs)

I the chips are protected inside electrically insulating but heat-conducting packages (usually ceramic or plastic)

I the input and output lines are connected to bonding pads which are electrically connected to pins on the package

I these pins are the chip’s connection to the outside world

I different chips can have pins in different arrangements I dual in-line packaging (DIP) I surface mount or small outline (SOIC, SOT, TSSOP, etc.) I quad flat package (QFP) I plastic leaded chip carrier (PLCC)

IC Packaging

I common packaging includes

Figure : Different types of IC packaging [Philips NXP, Digikey, Intersil] I surface mount or small outline (SOIC, SOT, TSSOP, etc.) I quad flat package (QFP) I plastic leaded chip carrier (PLCC)

IC Packaging

I common packaging includes

I dual in-line packaging (DIP)

Figure : Different types of IC packaging [Philips NXP, Digikey, Intersil] I quad flat package (QFP) I plastic leaded chip carrier (PLCC)

IC Packaging

I common packaging includes

I dual in-line packaging (DIP) I surface mount or small outline (SOIC, SOT, TSSOP, etc.)

Figure : Different types of IC packaging [Philips NXP, Digikey, Intersil] I plastic leaded chip carrier (PLCC)

IC Packaging

I common packaging includes

I dual in-line packaging (DIP) I surface mount or small outline (SOIC, SOT, TSSOP, etc.) I quad flat package (QFP)

Figure : Different types of IC packaging [Philips NXP, Digikey, Intersil] IC Packaging

I common packaging includes

I dual in-line packaging (DIP) I surface mount or small outline (SOIC, SOT, TSSOP, etc.) I quad flat package (QFP) I plastic leaded chip carrier (PLCC)

Figure : Different types of IC packaging [Philips NXP, Digikey, Intersil] Digital IC 7400 Series

7400 2-input NAND 7402 2-input NOR 7404 Hex Inverter 7408 2-input AND 7420 4-input NAND etc...... Pinout diagrams We will talk more about “sequential logic” in the next lecture.

Timing Issues

I gates have propagation delays

I this can lead to glitches

I glitches occur when different inputs to downstream logic gates change at different times due to differences in transmission times, causing the output to change before the inputs are actually ready. Timing Issues

I gates have propagation delays

I this can lead to glitches

I glitches occur when different inputs to downstream logic gates change at different times due to differences in transmission times, causing the output to change before the inputs are actually ready. We will talk more about “sequential logic” in the next lecture. Noise margins

I Input must be above a certain level (VIH ) in order for the circuit to “see” the input as “HIGH”; i.e., if vin ≥ VIH ⇒ vin will be considered “HIGH”

I Input must be below a certain level (VIL) in order for the circuit to “see” the input as “LOW”; i.e., if vin ≤ VIL ⇒ vin will be considered “LOW”

I Output is guaranteed to be above a certain voltage level (VOH ) when it is a logic HIGH. i.e., if output is supposed to be HIGH, then vout ≥ VOH I Output is guaranteed to be below a certain voltage level (VOL) when it is a logic LOW. i.e., if output is supposed to be LPOW, then vout ≤ VOL Noise margins, continued Other design issues

I fanout = number of gate inputs (from same logic family) that can be connected to a single output and stay within current ratings; e.g., for TTL subfamilies, a typical fan-out is 10. Outline

Digital Logic Definition

Digital IC Design Issues

Bipolar Transistor Logic Families

CMOS circuits - consumes more power and is noisier than current - noise immunity improved by using zener diodes. Useful for industrial applications (noisy environments), but slower than TTL - not many applications - not many applications

Bipolar Transistor Logic Families

1. TTL = transistor-transistor logic 2. ECL = emitter-coupled logic 3. RTL = resistor-transistor logic

4. DTL = diode-transistor logic

5. HTL = high-threshold logic 6. HTNL = high-noise immunity logic Bipolar Transistor Logic Families

1. TTL = transistor-transistor logic 2. ECL = emitter-coupled logic 3. RTL = resistor-transistor logic - consumes more power and is noisier than current 4. DTL = diode-transistor logic - noise immunity improved by using zener diodes. Useful for industrial applications (noisy environments), but slower than TTL 5. HTL = high-threshold logic - not many applications 6. HTNL = high-noise immunity logic - not many applications I → prevent transistor from fully saturating when put in ON state

I → reduce circuit R values → τ = RC is smaller. But increases power consumption I moderate power consumption

I High Power TTL: for applications such as driver circuits. I Low Power TTL: slower operating speed, but lower power b/c larger R values are used.

TTL

I moderate speed Limited by

I time to discharge base: In saturation, in order to turn transistor OFF, must remove charge from base I time to discharge wiring and transistor capacitances via circuit resistances I moderate power consumption

I High Power TTL: for applications such as driver circuits. I Low Power TTL: slower operating speed, but lower power b/c larger R values are used.

TTL

I moderate speed Limited by

I time to discharge base: In saturation, in order to turn transistor OFF, must remove charge from base I time to discharge wiring and transistor capacitances via circuit resistances

I → prevent transistor from fully saturating when put in ON state

I → reduce circuit R values → τ = RC is smaller. But increases power consumption TTL

I moderate speed Limited by

I time to discharge base: In saturation, in order to turn transistor OFF, must remove charge from base I time to discharge wiring and transistor capacitances via circuit resistances

I → prevent transistor from fully saturating when put in ON state

I → reduce circuit R values → τ = RC is smaller. But increases power consumption I moderate power consumption

I High Power TTL: for applications such as driver circuits. I Low Power TTL: slower operating speed, but lower power b/c larger R values are used. (but this increases power)

TTL, continued

I Schottky TTL (S-TTL) = transistor with a Schottky diode connected between its base and collector

I high-speed applications I prevents transistor saturation (via Schottky diode) I lower resistor values can be used TTL, continued

I Schottky TTL (S-TTL) = transistor with a Schottky diode connected between its base and collector

I high-speed applications I prevents transistor saturation (via Schottky diode) I lower resistor values can be used (but this increases power) What is this circuit? NOT gate (inverter)

TTL logic gates What is this circuit? NOT gate (inverter)

TTL logic gates What is this circuit? NOT gate (inverter)

TTL logic gates What is this circuit? NOT gate (inverter)

TTL logic gates NOT gate (inverter)

TTL logic gates

What is this circuit? TTL logic gates

What is this circuit? NOT gate (inverter) NAND gate

TTL logic gates

What is this circuit? TTL logic gates

What is this circuit? NAND gate ECL = Emitter Coupled Logic

I xtors’ emitters are connected together

I no xtors are in saturation

I ⇒ highest speed logic family, but can cause ringing at output

I good for high speed applications (e.g., data transmission, radar signal processing)

I use negative voltage supply ⇒ consumes a lot of power

I more susceptible to noise MOSFET (Metal-Oxide Semiconductor Field Effect Transistors)

I n-MOS

I p-MOS MOSFET: nMOS

I n-MOS

Figure : Circuit symbols for nMOS transistor. The two are equivalent.

I vGS > VT → current flows through channel ⇒ transistor is ON I vGS < VT → no channel for current to flow ⇒ transistor is OFF I VT is the threshold voltage p p VT = VT 0 + γ( VSB + 2φF − 2φF ) MOSFET (Metal-Oxide Semiconductor Field Effect Transistors)

Figure : Circuit symbols for nMOS transistor. The two are equivalent.

I vGS > VT → current flows through channel ⇒ transistor is ON I vGS < VT → no channel for current to flow ⇒ transistor is OFF I VT is the threshold voltage ? Don’t worry about the equation; just realize it depends upon the device physics and will be different for each device. ? VT typically 1 - 3V MOSFET: pMOS

I p-MOS

Figure : Circuit symbols for pMOS transistor. The two are equivalent.

I vGS < VT → current flows through channel ⇒ transistor is ON I vGS > VT → no channel for current to flow ⇒ transistor is OFF Look at Table 15.4 p. 840 for a summary of the comparison between different logic families.

CMOS = Complementary Metal Oxide Semiconductor

I use nMOS and pMOS FETs together to create digital logic functions

I nMOS transistors are used to bring output low when appropriate

I pMOS transistors are used to bring output high when appropriate CMOS = Complementary Metal Oxide Semiconductor

I use nMOS and pMOS FETs together to create digital logic functions

I nMOS transistors are used to bring output low when appropriate

I pMOS transistors are used to bring output high when appropriate Look at Table 15.4 p. 840 for a summary of the comparison between different logic families. Outline

Digital Logic Definition

Digital IC Design Issues

Bipolar Transistor Logic Families

CMOS circuits MOS inverters

nMOS inverter

vGS = vin

and vGS must be > VT to turn ON vout = H for vin L

nMOS inverter OFF

vGS = vin

vin < VT ⇒ OFF nMOS inverter OFF

vGS = vin

vin < VT ⇒ OFF

vout = H for vin L ( H for vin L vout = L for vin H

Rl must be large enough that Vs − ISAT Rl is LOW

nMOS inverter ON

vGS = vin

vin > VT ⇒ ON Rl must be large enough that Vs − ISAT Rl is LOW

nMOS inverter ON

vGS = vin

vin > VT ⇒ ON

( H for vin L vout = L for vin H nMOS inverter ON

vGS = vin

vin > VT ⇒ ON

( H for vin L vout = L for vin H

Rl must be large enough that Vs − ISAT Rl is LOW nMOS inverters

Vs R l v out D v G in S

vGS = vin

Also represent by a digital logic table (where Qn represents the state of the transistor) vin Qn vout L (0) OFF H (+V) H (+V) ON L (0) vin Qp vout L (0) ON H (+V) H (+V) OFF L (0)

pMOS inverter

vGS = vin − V

and vGS must be < VT to turn ON pMOS inverter

vGS = vin − V

and vGS must be < VT to turn ON vin Qp vout L (0) ON H (+V) H (+V) OFF L (0) CMOS = Complementary Metal Oxide Semiconductor

I Notice that by themselves,

I an nMOS is only ON during 1 of the 2 output states (namely, when vout is LOW), and likewise, I a pMOS is only ON during 1 of the 2 output states (namely, when vout is HIGH).

I This means that for the nMOS the output is not actively pulled up for vout HIGH and

I the pMOS is not actively pulled down for vout LOW

vin QnMOS QpMOS vout L (0) OFF ON H (+V) H (+V) ON OFF L (0) CMOS Instead, we can pair nMOSes with pMOSes to get CMOS:

I nMOS transistors are used to bring output low when appropriate I pMOS transistors are used to bring output high when appropriate I Load resistors are not needed, since nMOS acts as RL when OFF (while pMOS is ON), and vice versa

vin QnMOS QpMOS vout L (0) OFF ON H (+V) H (+V) ON OFF L (0) V ⇒ noise margin of 2 before an output error will occur (as long as nMOS and pMOS xtors are matched, the input-output transfer function will be symmetric)

I Large output range: Can get output voltage to swing between close to 0V and close to +V

Advantages of CMOS

V I Noise immunity: vIN can range from 0 to 2 for one output V level (e.g., H) and from 2 to V for the other output level (e.g., L) I Large output range: Can get output voltage to swing between close to 0V and close to +V

Advantages of CMOS

V I Noise immunity: vIN can range from 0 to 2 for one output V level (e.g., H) and from 2 to V for the other output level V (e.g., L) ⇒ noise margin of 2 before an output error will occur (as long as nMOS and pMOS xtors are matched, the input-output transfer function will be symmetric) Advantages of CMOS

V I Noise immunity: vIN can range from 0 to 2 for one output V level (e.g., H) and from 2 to V for the other output level V (e.g., L) ⇒ noise margin of 2 before an output error will occur (as long as nMOS and pMOS xtors are matched, the input-output transfer function will be symmetric)

I Large output range: Can get output voltage to swing between close to 0V and close to +V I Q1 and Q3 form a complementary pair I Q2 and Q4 form a complementary pair I When Q1 is ON Q3 is OFF I When Q1 is OFF Q3 is ON I When Q2 is ON Q4 is OFF I When Q2 is OFF Q4 is ON

CMOS NAND Gate We can create logic functions with multiple inputs. For example, consider the 2-input NAND function. I When Q1 is ON Q3 is OFF I When Q1 is OFF Q3 is ON I When Q2 is ON Q4 is OFF I When Q2 is OFF Q4 is ON

CMOS NAND Gate We can create logic functions with multiple inputs. For example, consider the 2-input NAND function.

I Q1 and Q3 form a complementary pair I Q2 and Q4 form a complementary pair CMOS NAND Gate We can create logic functions with multiple inputs. For example, consider the 2-input NAND function.

I Q1 and Q3 form a complementary pair I Q2 and Q4 form a complementary pair I When Q1 is ON Q3 is OFF I When Q1 is OFF Q3 is ON I When Q2 is ON Q4 is OFF I When Q2 is OFF Q4 is ON CMOS NAND Gate

AB Q1 Q2 Q3 Q4 Y 0 0 ON ON OFF OFF 1 0 1 ON OFF OFF ON 1 1 0 OFF ON ON OFF 1 1 1 OFF OFF ON ON 0 ⇒ in order for output to be pulled down, both Q3 and Q4 must be ON I and since pMOSes are complementarily tied to inputs, in this situation, Q1 and Q2 will be OFF in that state, and can act as the Rl I pMOSes (Q1 and Q2) are in parallel ⇒ in order for output to be pulled up, either Q1 or Q2 can be ON I and since nMOSes are complementarily tied to inputs, in this situation, Q3 and Q4 will be OFF in those states, and can act as the Rl

CMOS NAND Gate

I nMOSes (Q3 and Q4) are in series I and since pMOSes are complementarily tied to inputs, in this situation, Q1 and Q2 will be OFF in that state, and can act as the Rl I pMOSes (Q1 and Q2) are in parallel ⇒ in order for output to be pulled up, either Q1 or Q2 can be ON I and since nMOSes are complementarily tied to inputs, in this situation, Q3 and Q4 will be OFF in those states, and can act as the Rl

CMOS NAND Gate

I nMOSes (Q3 and Q4) are in series ⇒ in order for output to be pulled down, both Q3 and Q4 must be ON I pMOSes (Q1 and Q2) are in parallel ⇒ in order for output to be pulled up, either Q1 or Q2 can be ON I and since nMOSes are complementarily tied to inputs, in this situation, Q3 and Q4 will be OFF in those states, and can act as the Rl

CMOS NAND Gate

I nMOSes (Q3 and Q4) are in series ⇒ in order for output to be pulled down, both Q3 and Q4 must be ON I and since pMOSes are complementarily tied to inputs, in this situation, Q1 and Q2 will be OFF in that state, and can act as the Rl ⇒ in order for output to be pulled up, either Q1 or Q2 can be ON I and since nMOSes are complementarily tied to inputs, in this situation, Q3 and Q4 will be OFF in those states, and can act as the Rl

CMOS NAND Gate

I nMOSes (Q3 and Q4) are in series ⇒ in order for output to be pulled down, both Q3 and Q4 must be ON I and since pMOSes are complementarily tied to inputs, in this situation, Q1 and Q2 will be OFF in that state, and can act as the Rl I pMOSes (Q1 and Q2) are in parallel I and since nMOSes are complementarily tied to inputs, in this situation, Q3 and Q4 will be OFF in those states, and can act as the Rl

CMOS NAND Gate

I nMOSes (Q3 and Q4) are in series ⇒ in order for output to be pulled down, both Q3 and Q4 must be ON I and since pMOSes are complementarily tied to inputs, in this situation, Q1 and Q2 will be OFF in that state, and can act as the Rl I pMOSes (Q1 and Q2) are in parallel ⇒ in order for output to be pulled up, either Q1 or Q2 can be ON CMOS NAND Gate

I nMOSes (Q3 and Q4) are in series ⇒ in order for output to be pulled down, both Q3 and Q4 must be ON I and since pMOSes are complementarily tied to inputs, in this situation, Q1 and Q2 will be OFF in that state, and can act as the Rl I pMOSes (Q1 and Q2) are in parallel ⇒ in order for output to be pulled up, either Q1 or Q2 can be ON I and since nMOSes are complementarily tied to inputs, in this situation, Q3 and Q4 will be OFF in those states, and can act as the Rl CMOS NOR Gate

AB Q1 Q2 Q3 Q4 Y 0 0 ON ON OFF OFF 1 0 1 ON OFF OFF ON 0 1 0 OFF ON ON OFF 0 1 1 OFF OFF ON ON 0 CMOS NOR Gate

AB Q1 Q2 Q3 Q4 Y 0 0 ON ON OFF OFF 1 0 1 ON OFF OFF ON 0 1 0 OFF ON ON OFF 0 1 1 OFF OFF ON ON 0 CMOS NOR Gate

AB Q1 Q2 Q3 Q4 Y 0 0 ON ON OFF OFF 1 0 1 ON OFF OFF ON 0 1 0 OFF ON ON OFF 0 1 1 OFF OFF ON ON 0 CMOS Analog Switch

I also called a CMOS transmission gate

¯ A A QnMOS QpMOS OUT 0 1 OFF OFF open (OUT is floating) 1 0 ON ON OUT = IN Digital Complexity

Class # of equiva- Examples lent gates Small-scale inte- 1-10 elementary logic gates, flip-flops gration (SSI) Medium-scale in- 10 − 100 e.g., counters, decoders, small tegration (MSI) memories Large-scale inte- 100-1,000 larger memories, microproces- gration (LSI) sors Very large-scale > 1, 000 microprocessors, large memo- integration (VLSI) ries Ultra large-scale > 10, 000 very computationally demanding integration (ULSI) microprocessors