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EE 372 Digital Logic Families EE 372 Digital Logic Families Deborah Won Department of Electrical and Computer Engineering California State University, Los Angeles Winter 2015 Outline Digital Logic Definition Digital IC Design Issues Bipolar Transistor Logic Families CMOS circuits e.g., the AND operation A B Y = A · B 0 0 0 0 1 0 1 0 0 1 1 1 Digital Logic Digital logic = Binary arithmetic performed by transistor circuits. The output represents whether a particular condition, or input state, is TRUE or FALSE. Digital Logic Digital logic = Binary arithmetic performed by transistor circuits. The output represents whether a particular condition, or input state, is TRUE or FALSE. e.g., the AND operation A B Y = A · B 0 0 0 0 1 0 1 0 0 1 1 1 ! acts like a transistor control voltage. Remember: We can get a transistor to act like an ON/OFF switch by forcing the transistor to operate either in its 1. saturation region 2. cutoff region Logic Gate These inputs A and B are actually the input voltage applied to the base of a transistor (or gate for MOS transistor) 2. cutoff region Logic Gate These inputs A and B are actually the input voltage applied to the base of a transistor (or gate for MOS transistor) ! acts like a transistor control voltage. Remember: We can get a transistor to act like an ON/OFF switch by forcing the transistor to operate either in its 1. saturation region Logic Gate These inputs A and B are actually the input voltage applied to the base of a transistor (or gate for MOS transistor) ! acts like a transistor control voltage. Remember: We can get a transistor to act like an ON/OFF switch by forcing the transistor to operate either in its 1. saturation region 2. cutoff region A digital IC which produces a logical state (“0” or “1”) at the output based on the logical state of the inputs. Elementary Logic Functions A Y NOT gate (or inverter) 0 1 1 0 What is a gate? Elementary Logic Functions A Y NOT gate (or inverter) 0 1 1 0 What is a gate? A digital IC which produces a logical state (“0” or “1”) at the output based on the logical state of the inputs. Elementary Logic Functions A B Y A B Y 0 0 0 0 0 1 AND 0 1 0 NAND 0 1 1 1 0 0 1 0 1 1 1 1 1 1 0 0 0 0 0 0 1 0 1 1 0 1 0 OR NOR 1 0 1 1 0 0 1 1 1 1 1 0 0 0 0 0 0 1 0 1 1 0 1 0 XOR XNOR 1 0 1 1 0 0 1 1 0 1 1 1 Important Boolean Algebra Identities 1. A + 0 = A 2. A + A¯ = 1 3. A · 0 = 0 4. A · 1 = A 5. A · A = A 6. A · A¯ = 0 7. Associative Law for Addition A + (B + C) = (A + B) + C 8. Associative Law for Multiplication A(BC) = (AB)C 9. DeMorgan’s Theorem for Addition A + B = A¯B¯ 10. DeMorgan’s Theorem for Multiplication ABC = A¯ + B¯ + C¯ Outline Digital Logic Definition Digital IC Design Issues Bipolar Transistor Logic Families CMOS circuits I many circuits can be etched on the same silicon wafer I the silicon wafer is divided and cut into “chips” (ICs) I the chips are protected inside electrically insulating but heat-conducting packages (usually ceramic or plastic) I the input and output lines are connected to bonding pads which are electrically connected to pins on the package I these pins are the chip’s connection to the outside world I different chips can have pins in different arrangements IC Packaging I digital logic is made up of transistors which are fabricated (made) in silicon I the silicon wafer is divided and cut into “chips” (ICs) I the chips are protected inside electrically insulating but heat-conducting packages (usually ceramic or plastic) I the input and output lines are connected to bonding pads which are electrically connected to pins on the package I these pins are the chip’s connection to the outside world I different chips can have pins in different arrangements IC Packaging I digital logic is made up of transistors which are fabricated (made) in silicon I many circuits can be etched on the same silicon wafer I the chips are protected inside electrically insulating but heat-conducting packages (usually ceramic or plastic) I the input and output lines are connected to bonding pads which are electrically connected to pins on the package I these pins are the chip’s connection to the outside world I different chips can have pins in different arrangements IC Packaging I digital logic is made up of transistors which are fabricated (made) in silicon I many circuits can be etched on the same silicon wafer I the silicon wafer is divided and cut into “chips” (ICs) I the input and output lines are connected to bonding pads which are electrically connected to pins on the package I these pins are the chip’s connection to the outside world I different chips can have pins in different arrangements IC Packaging I digital logic is made up of transistors which are fabricated (made) in silicon I many circuits can be etched on the same silicon wafer I the silicon wafer is divided and cut into “chips” (ICs) I the chips are protected inside electrically insulating but heat-conducting packages (usually ceramic or plastic) I these pins are the chip’s connection to the outside world I different chips can have pins in different arrangements IC Packaging I digital logic is made up of transistors which are fabricated (made) in silicon I many circuits can be etched on the same silicon wafer I the silicon wafer is divided and cut into “chips” (ICs) I the chips are protected inside electrically insulating but heat-conducting packages (usually ceramic or plastic) I the input and output lines are connected to bonding pads which are electrically connected to pins on the package I different chips can have pins in different arrangements IC Packaging I digital logic is made up of transistors which are fabricated (made) in silicon I many circuits can be etched on the same silicon wafer I the silicon wafer is divided and cut into “chips” (ICs) I the chips are protected inside electrically insulating but heat-conducting packages (usually ceramic or plastic) I the input and output lines are connected to bonding pads which are electrically connected to pins on the package I these pins are the chip’s connection to the outside world IC Packaging I digital logic is made up of transistors which are fabricated (made) in silicon I many circuits can be etched on the same silicon wafer I the silicon wafer is divided and cut into “chips” (ICs) I the chips are protected inside electrically insulating but heat-conducting packages (usually ceramic or plastic) I the input and output lines are connected to bonding pads which are electrically connected to pins on the package I these pins are the chip’s connection to the outside world I different chips can have pins in different arrangements I dual in-line packaging (DIP) I surface mount or small outline (SOIC, SOT, TSSOP, etc.) I quad flat package (QFP) I plastic leaded chip carrier (PLCC) IC Packaging I common packaging includes Figure : Different types of IC packaging [Philips NXP, Digikey, Intersil] I surface mount or small outline (SOIC, SOT, TSSOP, etc.) I quad flat package (QFP) I plastic leaded chip carrier (PLCC) IC Packaging I common packaging includes I dual in-line packaging (DIP) Figure : Different types of IC packaging [Philips NXP, Digikey, Intersil] I quad flat package (QFP) I plastic leaded chip carrier (PLCC) IC Packaging I common packaging includes I dual in-line packaging (DIP) I surface mount or small outline (SOIC, SOT, TSSOP, etc.) Figure : Different types of IC packaging [Philips NXP, Digikey, Intersil] I plastic leaded chip carrier (PLCC) IC Packaging I common packaging includes I dual in-line packaging (DIP) I surface mount or small outline (SOIC, SOT, TSSOP, etc.) I quad flat package (QFP) Figure : Different types of IC packaging [Philips NXP, Digikey, Intersil] IC Packaging I common packaging includes I dual in-line packaging (DIP) I surface mount or small outline (SOIC, SOT, TSSOP, etc.) I quad flat package (QFP) I plastic leaded chip carrier (PLCC) Figure : Different types of IC packaging [Philips NXP, Digikey, Intersil] Digital IC 7400 Series 7400 2-input NAND 7402 2-input NOR 7404 Hex Inverter 7408 2-input AND 7420 4-input NAND etc... ... Pinout diagrams We will talk more about “sequential logic” in the next lecture. Timing Issues I gates have propagation delays I this can lead to glitches I glitches occur when different inputs to downstream logic gates change at different times due to differences in transmission times, causing the output to change before the inputs are actually ready. Timing Issues I gates have propagation delays I this can lead to glitches I glitches occur when different inputs to downstream logic gates change at different times due to differences in transmission times, causing the output to change before the inputs are actually ready. We will talk more about “sequential logic” in the next lecture. Noise margins I Input must be above a certain level (VIH ) in order for the circuit to “see” the input as “HIGH”; i.e., if vin ≥ VIH ) vin will be considered “HIGH” I Input must be below a certain level (VIL) in order for the circuit to “see” the input as “LOW”; i.e., if vin ≤ VIL ) vin will be considered “LOW” I Output is guaranteed to be above a certain voltage level (VOH ) when it is a logic HIGH.
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