1.Design a Three Input NAND Gate Using Diode Logic and a Transistor Inverter

1.Design a three input NAND gate using diode logic and a transistor inverter.

The below Figure shows the circuit diagram for a three input LS-TTL NAND gate(74LS00). We know that NAND function can be obtained by inverting the output of a diode AND gate. The circuit is basically divided it into three functional parts. They are

• Diode AND gate and input protection • Phase splitter • Output stage The below Figure shows the circuit diagram for a two input LS-TTL NAND gate(74LS00). We know that NAND function can be obtained by inverting the output of a diode AND gate. The circuit is basically divided it into three functional parts. They are

• Diode AND gate and input protection • Phase splitter • Output stage

As shown in figure diodes D1X and D1Y and resistor R1 forms a diode AND gate. The Clamp diodes D2X and D2Y at the input are used as protective diodes. These diodes protect the circuit from large negative transients on input lines. The transistor Q2 acts as an inerter. The Q2 alongwith the surrounding resistors form a phase splitter that controls the output stage. The diode AND gate and the phase splitter, thus represents the NAND function. Depending on whether the diode AND gate produces a “low” or a “high” voltage at VA, Q2 is either cut off or turned on.

FUNCTION TABLE:

X Y Z VA Q2 Q3 Q4 Q5 Q6 VOUT LOW LOW LOW LOW OFF ON ON OFF OFF HIGH LOW LOW HIGH LOW OFF ON ON OFF OFF HIGH

LOW HIGH LOW LOW OFF ON ON OFF OFF HIGH

LOW HIGH HIGH LOW OFF ON ON OFF OFF HIGH

HIGH LOW LOW LOW OFF ON ON OFF OFF HIGH

HIGH LOW HIGH LOW OFF ON ON OFF OFF HIGH HIGH HIGH LOW LOW OFF ON ON OFF OFF HIGH HIGH HIGH HIGH HIGH ON OFF OFF ON ON LOW

The output stage has two transistors, Q4 and Q5, only one of which is on at any time The TTL output stage is sometimes called a totem-pole or push-pull output Similar to the p- channel and n-channel transistors in CMOS, Q4 and Q5 provide active pull-up and pull-down to the HIGH and LOW states, respectively. The functional operation of the TTL NAND gate is summarized in above Figure.

The gate does indeed perform the NAND function, with the truth table and logic symbol shown in (b) and (c) TTL NAND gates can be designed with any desired number of inputs simply by changing the number of diodes in the diode AND gate in the figure.

It is important to note that all the transistors used are schottky clamped transistors. The circuit uses a darlington pair (Q3 and Q4) to provide shorter output rise time when switching from OFF to ON. The transistor Q6 connected in series regulates the current flow into the base of Q and helps in turning Q5 OFF rapidly.

However, when the TTL output is changing from HIGH to LOW or vice versa, there is a short time when both transistors may be ON. The purpose of R5 is to limit the amount of current that flows from VCC to ground. 2.Explain sinking current and sourcing current of TTL o/p.which of the parameters decide the fanout and how?

SINKING AND SOURCING CURRENTS

The definitions of sinking and sourcing currents are shown in below Figure. A device output is said to sink current when current flows from the power supply, through the load, and through the device output to ground as in below figure.

When a TTL input is driven LOW by the output of another TTL gate. Transistor Q5 in the driving gate is ON, and thereby provides a path to ground for the current flowing out of the diode in the driven gate. When current flows into a TTL output in the LOW state, as in the case, the output is said to sinking current.

The output is said to source current when current flows from the power supply, out of the device output, and through the load to ground as in below fig.

When a TTL input is driven HIGH by the output of another TTL gate. Transistor Q4 in the driving gate is ON, enough to supply the small amount of leakage current flowing through reverse biased diodes in the driven gate. When current flows out of a TTL output in the HIGH state, as in the case, the output is said to sourcing current.

3. Explain the following terms with reference to TTL logic

1.logic levels 2. DC noise margin 3.Low state unit load 4. High state fanout

1.Logic Levels

The TTL device manufacturers specify the four voltage parameters in the datasheet. They are:

VIH(min)-High-Level Input Voltage: It is the minimum voltage level required for a logical 1 at an input. Any voltage below this level will not be accepted as a HIGH by the logic circuit.

VIL(max)-Low-Level Input Voltage: It is the maximum voltage level required for a logical 0 at an input. Any voltage above this level will not be accepted as a LOW by the logic circuit.

VOH(min)-High-Level Output Voltage: It is the minimum voltage level required for a logical 1 for an output under defined load conditions.

VOL(max)-Low-Level Output Voltage: It is the maximum voltage level required for a logical 0 for an output under defined load conditions.

2.NOISE MARGINS:

In practice due to unwanted signal called noise, sometimes, the voltage at the input drops below VIH(min) or rise above VIL(max) , which produces unpredictable operation. Noise margin is classified into two types. They are: 1.High state DC Noise Margin(VNH)-It is the difference between the high level output voltage and high level input voltage.

VNH = VOH(min) - VIH(min)=0.4

2. Low state DC Noise Margin(VNL)-It is the difference between the low level input voltage and low level output voltage.

VNH = VIL(max) - VOL(max)=0.4

These two are illustrated in below figure.

FANOUT

The fan-out of a logic gate is the number of inputs that the gate can drive without exceeding its worst-case loading specifications. The fan-out depends not only on the characteristics of the output, but also on the inputs that it is driving. Fan-out must be examined for both possible output states, HIGH and LOW.

The maximum LOW-state output current IOLmax for TTL gate is 8mA.The maximum LOW state input current IILmax is -0.4mA. Therefore, the LOW-state fanout or low state unit load for TTL is 20.

IOLmax 8mA LOW state unit load= / / = / /= 20 IILmax −0.4mA

Also the maximum HIGH-state output current IOHmaxC is -400µA. The maximum HIGH state input current IIHmax is 20µA. Hence the HIGH-state fanout is also 20 i.e., The HIGH-state and LOW-state fan-outs of a gate are not necessarily equal. In general, the overall fanout of a gate is the minimum of its HIGH state and LOW-state fanouts, i.e., 20.

IOHmax −400µA HIGH state fan-out = / / = / /= 20 . IIHmax 20µA

4.What is meant by tri-state logic? Draw the circuit of tri-state TTL logic and explain its functions.

In digital electronics three-state, tri-state, or 3-state logic allows an output port to assume a high impedance state, effectively removing the output from the circuit, in addition to the 0 and 1 logic levels.

Figure 9 shows a tri-state TTL inverter. When E is H, the gate is enabled and behaves like a normal inverter; when E is L, the gate output is disabled, and there is a high impedance looking into the output (the ouput is essentially open-circuited).

Figure 9: TTL tri-state inverter.

The operation of the tri-state inverter is summarised in the table. Enable Input Output L X Hi-Z H L H H H L

5.Draw the two input TTL NAND gate and explain its operation.

The below Figure shows the circuit diagram for a two input LS-TTL NAND gate(74LS00). We know that NAND function can be obtained by inverting the output of a diode AND gate. The circuit is basically divided it into three functional parts. They are

• Diode AND gate and input protection • Phase splitter • Output stage

FIG: The circuit diagram for a two-input LS-TTL NAND gate, 74LS00

FUNCTION TABLE:

X Y VA Q2 Q3 Q4 Q5 Q6 Z LOW LOW LOW OFF ON ON OFF OFF HIGH

LOW HIGH LOW OFF ON ON OFF OFF HIGH

HIGH LOW LOW OFF ON ON OFF OFF HIGH

HIGH HIGH HIGH ON OFF OFF ON ON LOW

Fig. TRUTH TABLE Fig. Logic symbol

(6 & 7). Draw the circuit of a 2-input TTL NOR gate and explain its functional behaviour.

The below Figure shows the circuit diagram for a two input LS-TTL NOR gate(74LS02). We know that NOR function can be obtained by inverting the output of a diode OR gate. The circuit is basically divided it into three functional parts. They are

• Diode OR gate and input protection • Phase splitter • Output stage

As shown in figure diodes D1X and D1Y and resistor R1 forms a diode OR gate. The Clamp diodes D2X and D2Y at the input are used as protective diodes. These diodes protect the circuit from large negative transients on input lines.

The transistors Q2X and Q2Y are acts as inverters. The Q2X and Q2Y alongwith the surrounding resistors form a phase splitter that controls the output stage. The diode OR gate and the phase splitter, thus represents the NOR function. Depending on whether the diode OR gate produces a “low” or a “high” voltage at VA, Q2X and Q2Y are either cut off or turned on. FUNCTION TABLE:

X Y VA Q2X Q2Y Q3 Q4 Q5 Q6 Z LOW LOW LOW OFF OFF ON ON OFF OFF HIGH LOW HIGH HIGH OFF ON OFF OFF ON ON LOW

HIGH LOW HIGH ON OFF OFF OFF ON ON LOW

HIGH HIGH HIGH ON ON OFF OFF ON ON LOW

Fig. TRUTH TABLE Fig. Logic symbol

The gate does indeed perform the NOR function, with the truth table and logic symbol shown in (b) and (c) TTL NOR gates can be designed with any desired number of inputs simply by changing the number of diodes in the diode OR gate in the figure.

However, when the TTL output is changing from HIGH to LOW or vice versa, there is a short time when both transistors may be ON. The purpose of R5 is to limit the amount of current that flows from VCC to ground. 8.Draw and explain the simple transistor logic inverter and its logic symbol and characteristics.

A bipolar junction transistor is a three-terminal device with regions and terminals base, collector and emitter. It has two junctions: base-collector junction and base-emitter junction. It is used as a current-controlled switch. The amount of base current decides the operating region of the transistor. It can be operated in three regions: 1. Cutoff 2. Active 3. Saturation In cutoff region, both the transistor junctions are reverse biased and only the reverse current, which is very small and practically negligible, flows in the transistor. In the saturation condition both the junctions are forward biased and the collector current is comparatively large and is controlled by the external resistance connected in the collector circuit. In the below figure the transistor is shown to be connected in common-emitter configuration. A square wave is applied between the base and emitter through a base resistance R1 and the output is taken between collector and emitter. Thus the output voltage VOUT is the voltage between the collector and emitter, i.e. VOUT is VCE.

WORKING:

Case 1: When input is HIGH : If the input to the transistor is high (+5V), the base emitter junction is forward biased and current flows through R1 into the base and the amount of current flowing through the base is sufficient to drive the transistor into saturation. In saturation condition, voltage between collector and emitter (VOUT) is VCE(sat) which is typically 0.3V.

Case 1: When input is LOW : If the input to the transistor is low (+0V), the base emitter junction is reverse biased and there is no current flows through R1 into the base and the amount of current flowing through the base is not sufficient to drive the transistor into saturation. In cutoff condition, voltage between collector and emitter (VOUT) is VCC.

ANALYSIS:

As per KVL :

VOUT=VCE=VCC-ICRC

In saturation the collector current is IC(sat) which is nearly equal to VCC /RC

Therefore VOUT= VCC-ICRC = VCC-(VCC /RC) RC

VOUT =0V(Ideally)

V OUT =0.3V(Practically)

In cutoff the collector current is IC(sat) which is equal to ‘0’

Therefore VOUT= VCC-ICRC = VCC-(0) RC

VOUT =VCC

Transfer characteristics :

9.Compare CMOS,TTL and ECL with reference to logic levels, noise margin, propagation delay and fanout.

COMPARISION OF LOGIC FAIMLIES

PARMAETER CM0S TTL ECL

FANOUT 20 20 25 PROPAGATION 70ns 10ns 0.75ns DELAY NOISE MARGIN 1.25V 0.4V 150mv

VOHmin 4.95v 2.4v -0.980v

VIHmin 3.5v 2.0v -1.105v

VOLmax 0.05v 0.4v -1.630v

VILmax 1.5v 0.8v -1.475v

10. Explain how CMOS / TTL interfacing can be achieved? Give the i/p and o/p levels of oltages and explain the same.

11.Draw the circuit diagram of basic CML gate and explain its operation.

(OR)

12.Draw the circuit diagram of basic ECL inverter/buffer and explain its operation with input low logic. Basic CML (ECL) Circuit:

The basic idea of current-mode logic or emitter coupled logic is illustrated by the inverter/buffer circuit in below Figure. This circuit has both an inverting output (OUT1) and a non inverting output (OUT2) Two transistors are connected as a differential amplifier with a common emitter resistor The supply voltages for this example are VCC=5.0v, VBB=4.0, and VEE=0 V, and the input LOW and HIGH levels are defined to be 3.6 and 4.4 V.

This circuit actually produces output LOW and HIGH levels that are 0.6 V higher (4.2 and 5.0 V), but this is corrected in real ECL circuits.

WORKING:

Case 1 : When VIN is HIGH, as shown in the figure, transistor Q1 is on, but not saturated, and transistor Q2 is OFF. This is true because of a careful choice of resistor values and voltage levels.Thus, VOUT2 is pulled to 5.0 V (HIGH) through R2, and it can be shown that the voltage drop across R1 is about 0.8 V so that VOUT1 is about 4.2 V (LOW).

Case 2 : When VIN is LOW, as shown in below Figure, transistor Q2 is on, but not saturated, and transistor Q1 is OFF. Thus, VOUT1 is pulled to 5.0 V through R1, and it can be shown that VOUT2 is about 4. 2 V.

FUNCTION TABLE:

INPUT Q1 Q2 OUT1 OUT2 LOW OFF ON HIGH LOW

HIGH ON OFF LOW HIGH

TRUTH TABLE:

INPUT OUT1(INVERTER) OUT2(BUFFER) 0 1 0 1 0 1

13.Design a transistor circuit of 2-input ECL NOR gate.Explain the operation with the help of function table.

WORKING:

Case 1 : A is Low and B is Low : When both input voltages are Low, then transistors Q1 and Q2 are off, and transistor Q2 is ON. This is true because of a careful choice of resistor values and voltage levels. Thus, VOUT1 is pulled to 5.0 V (HIGH) through R2, and it can be shown that the voltage drop across R1 is about 0.8 V so that VOUT2 is about 4.2 V (LOW).

Case 2 : A is Low and B is High : When A is low and B is high, then , transistor Q2 is on and Q1 is OFF, and transistor Q3 is also OFF.Thus, VOUT2 is pulled to 5.0 V (HIGH) through R2, and it can be shown that the voltage drop across R1 is about 0.8 V so that VOUT1 is about 4.2 V (LOW).

Case 3 : A is High and B is Low : When A is high and B is low, then , transistor Q1 is on and Q2 is OFF, and transistor Q3 is also OFF. Thus, VOUT2 is pulled to 5.0 V (HIGH) through R2, and it can be shown that the voltage drop across R1 is about 0.8 V so that VOUT1 is about 4.2 V (LOW).

Case 4 : A is high and B is high : When A is high and B is high, then , transistor Q1 is on and Q2 is ON, and transistor Q3 is also OFF. Thus, VOUT2 is pulled to 5.0 V (HIGH) through R2, and it can be shown that the voltage drop across R1 is about 0.8 V so that VOUT1 is about 4.2 V (LOW).

TRUTH TABLE:

A B OUT1(NOR) OUT2(OR) 0 0 1 0 0 1 0 1 1 0 0 1 1 1 0 1

FUNCTION TABLE:

A B Q1 Q2 Q3 OUT1 OUT2 LOW LOW OFF OFF ON HIGH LOW LOW HIGH OFF ON OFF LOW HIGH HIGH LOW ON OFF OFF LOW HIGH HIGH HIGH ON ON OFF LOW HIGH

LOGIC SYMBOL:

14.Draw the circuit diagram of two input 10K ECL OR gateand explain its operation.