DOCSLIB.ORG

1.Design a Three Input NAND Gate Using Diode Logic and a Transistor Inverter

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
1.Design a Three Input NAND Gate Using Diode Logic and a Transistor Inverter 1.Design a three input NAND gate using diode logic and a transistor inverter. The below Figure shows the circuit diagram for a three input LS-TTL NAND gate(74LS00). We know that NAND function can be obtained by inverting the output of a diode AND gate. The circuit is basically divided it into three functional parts. They are • Diode AND gate and input protection • Phase splitter • Output stage The below Figure shows the circuit diagram for a two input LS-TTL NAND gate(74LS00). We know that NAND function can be obtained by inverting the output of a diode AND gate. The circuit is basically divided it into three functional parts. They are • Diode AND gate and input protection • Phase splitter • Output stage As shown in figure diodes D1X and D1Y and resistor R1 forms a diode AND gate. The Clamp diodes D2X and D2Y at the input are used as protective diodes. These diodes protect the circuit from large negative transients on input lines. The transistor Q2 acts as an inerter. The Q2 alongwith the surrounding resistors form a phase splitter that controls the output stage. The diode AND gate and the phase splitter, thus represents the NAND function. Depending on whether the diode AND gate produces a “low” or a “high” voltage at VA, Q2 is either cut off or turned on. FUNCTION TABLE: X Y Z VA Q2 Q3 Q4 Q5 Q6 VOUT LOW LOW LOW LOW OFF ON ON OFF OFF HIGH LOW LOW HIGH LOW OFF ON ON OFF OFF HIGH LOW HIGH LOW LOW OFF ON ON OFF OFF HIGH LOW HIGH HIGH LOW OFF ON ON OFF OFF HIGH HIGH LOW LOW LOW OFF ON ON OFF OFF HIGH HIGH LOW HIGH LOW OFF ON ON OFF OFF HIGH HIGH HIGH LOW LOW OFF ON ON OFF OFF HIGH HIGH HIGH HIGH HIGH ON OFF OFF ON ON LOW The output stage has two transistors, Q4 and Q5, only one of which is on at any time The TTL output stage is sometimes called a totem-pole or push-pull output Similar to the p- channel and n-channel transistors in CMOS, Q4 and Q5 provide active pull-up and pull-down to the HIGH and LOW states, respectively. The functional operation of the TTL NAND gate is summarized in above Figure. The gate does indeed perform the NAND function, with the truth table and logic symbol shown in (b) and (c) TTL NAND gates can be designed with any desired number of inputs simply by changing the number of diodes in the diode AND gate in the figure. It is important to note that all the transistors used are schottky clamped transistors. The circuit uses a darlington pair (Q3 and Q4) to provide shorter output rise time when switching from OFF to ON. The transistor Q6 connected in series regulates the current flow into the base of Q and helps in turning Q5 OFF rapidly. However, when the TTL output is changing from HIGH to LOW or vice versa, there is a short time when both transistors may be ON. The purpose of R5 is to limit the amount of current that flows from VCC to ground. 2.Explain sinking current and sourcing current of TTL o/p.which of the parameters decide the fanout and how? SINKING AND SOURCING CURRENTS The definitions of sinking and sourcing currents are shown in below Figure. A device output is said to sink current when current flows from the power supply, through the load, and through the device output to ground as in below figure. When a TTL input is driven LOW by the output of another TTL gate. Transistor Q5 in the driving gate is ON, and thereby provides a path to ground for the current flowing out of the diode in the driven gate. When current flows into a TTL output in the LOW state, as in the case, the output is said to sinking current. The output is said to source current when current flows from the power supply, out of the device output, and through the load to ground as in below fig. When a TTL input is driven HIGH by the output of another TTL gate. Transistor Q4 in the driving gate is ON, enough to supply the small amount of leakage current flowing through reverse biased diodes in the driven gate. When current flows out of a TTL output in the HIGH state, as in the case, the output is said to sourcing current. 3. Explain the following terms with reference to TTL logic 1.logic levels 2. DC noise margin 3.Low state unit load 4. High state fanout 1.Logic Levels The TTL device manufacturers specify the four voltage parameters in the datasheet. They are: VIH(min)-High-Level Input Voltage: It is the minimum voltage level required for a logical 1 at an input. Any voltage below this level will not be accepted as a HIGH by the logic circuit. VIL(max)-Low-Level Input Voltage: It is the maximum voltage level required for a logical 0 at an input. Any voltage above this level will not be accepted as a LOW by the logic circuit. VOH(min)-High-Level Output Voltage: It is the minimum voltage level required for a logical 1 for an output under defined load conditions. VOL(max)-Low-Level Output Voltage: It is the maximum voltage level required for a logical 0 for an output under defined load conditions. 2.NOISE MARGINS: In practice due to unwanted signal called noise, sometimes, the voltage at the input drops below VIH(min) or rise above VIL(max) , which produces unpredictable operation. Noise margin is classified into two types. They are: 1.High state DC Noise Margin(VNH)-It is the difference between the high level output voltage and high level input voltage. VNH = VOH(min) - VIH(min)=0.4 2. Low state DC Noise Margin(VNL)-It is the difference between the low level input voltage and low level output voltage. VNH = VIL(max) - VOL(max)=0.4 These two are illustrated in below figure. FANOUT The fan-out of a logic gate is the number of inputs that the gate can drive without exceeding its worst-case loading specifications. The fan-out depends not only on the characteristics of the output, but also on the inputs that it is driving. Fan-out must be examined for both possible output states, HIGH and LOW. The maximum LOW-state output current IOLmax for TTL gate is 8mA.The maximum LOW state input current IILmax is -0.4mA. Therefore, the LOW-state fanout or low state unit load for TTL is 20. IOLmax 8mA LOW state unit load= / / = / /= 20 IILmax −0.4mA Also the maximum HIGH-state output current IOHmaxC is -400µA. The maximum HIGH state input current IIHmax is 20µA. Hence the HIGH-state fanout is also 20 i.e., The HIGH-state and LOW-state fan-outs of a gate are not necessarily equal. In general, the overall fanout of a gate is the minimum of its HIGH state and LOW-state fanouts, i.e., 20. IOHmax −400µA HIGH state fan-out = / / = / /= 20 . IIHmax 20µA 4.What is meant by tri-state logic? Draw the circuit of tri-state TTL logic and explain its functions. In digital electronics three-state, tri-state, or 3-state logic allows an output port to assume a high impedance state, effectively removing the output from the circuit, in addition to the 0 and 1 logic levels. Figure 9 shows a tri-state TTL inverter. When E is H, the gate is enabled and behaves like a normal inverter; when E is L, the gate output is disabled, and there is a high impedance looking into the output (the ouput is essentially open-circuited). Figure 9: TTL tri-state inverter. The operation of the tri-state inverter is summarised in the table. Enable Input Output L X Hi-Z H L H H H L 5.Draw the two input TTL NAND gate and explain its operation. The below Figure shows the circuit diagram for a two input LS-TTL NAND gate(74LS00). We know that NAND function can be obtained by inverting the output of a diode AND gate. The circuit is basically divided it into three functional parts. They are • Diode AND gate and input protection • Phase splitter • Output stage FIG: The circuit diagram for a two-input LS-TTL NAND gate, 74LS00 As shown in figure diodes D1X and D1Y and resistor R1 forms a diode AND gate. The Clamp diodes D2X and D2Y at the input are used as protective diodes. These diodes protect the circuit from large negative transients on input lines. The transistor Q2 acts as an inerter. The Q2 alongwith the surrounding resistors form a phase splitter that controls the output stage. The diode AND gate and the phase splitter, thus represents the NAND function. Depending on whether the diode AND gate produces a “low” or a “high” voltage at VA, Q2 is either cut off or turned on. FUNCTION TABLE: X Y VA Q2 Q3 Q4 Q5 Q6 Z LOW LOW LOW OFF ON ON OFF OFF HIGH LOW HIGH LOW OFF ON ON OFF OFF HIGH HIGH LOW LOW OFF ON ON OFF OFF HIGH HIGH HIGH HIGH ON OFF OFF ON ON LOW Fig. TRUTH TABLE Fig. Logic symbol The output stage has two transistors, Q4 and Q5, only one of which is on at any time The TTL output stage is sometimes called a totem-pole or push-pull output Similar to the p- channel and n-channel transistors in CMOS, Q4 and Q5 provide active pull-up and pull-down to the HIGH and LOW states, respectively.
Load more

Recommended publications
  • Transistors and Logic Gates
    Introduction to Computer Engineering CS/ECE 252, Spring 2013 Prof. Mark D. Hill Computer Sciences Department University of Wisconsin – Madison Chapter 3 Digital Logic Structures Slides based on set prepared by Gregory T. Byrd, North Carolina State University Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Transistor: Building Block of Computers Microprocessors contain millions of transistors • Intel Pentium II: 7 million • Compaq Alpha 21264: 15 million • Intel Pentium III: 28 million Logically, each transistor acts as a switch Combined to implement logic functions • AND, OR, NOT Combined to build higher-level structures • Adder, multiplexer, decoder, register, … Combined to build processor • LC-3 3-3 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Simple Switch Circuit Switch open: • No current through circuit • Light is off • Vout is +2.9V Switch closed: • Short circuit across switch • Current flows • Light is on • Vout is 0V Switch-based circuits can easily represent two states: on/off, open/closed, voltage/no voltage. 3-4 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. N-type MOS Transistor MOS = Metal Oxide Semiconductor • two types: N-type and P-type N-type • when Gate has positive voltage, short circuit between #1 and #2 (switch closed) • when Gate has zero voltage, open circuit between #1 and #2 Gate = 1 (switch open) Gate = 0 Terminal #2 must be connected to GND (0V). 3-5 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. P-type MOS Transistor P-type is complementary to N-type • when Gate has positive voltage, open circuit between #1 and #2 (switch open) • when Gate has zero voltage, short circuit between #1 and #2 (switch closed) Gate = 1 Gate = 0 Terminal #1 must be connected to +2.9V.
    [Show full text]
  • Lecture17 08 04 2010
    EE40 Lecture 17 Josh Hug 8/04/2010 EE40 Summer 2010 Hug 1 Logistics • HW8 will be due Friday • Mini-midterm 3 next Wednesday – 80/160 points will be a take-home set of design problems which will utilize techniques we’ve covered in class • Handed out Friday • Due next Wednesday – Other 80/160 will be an in class midterm covering HW7 and HW8 • Final will include Friday and Monday lecture, Midterm won’t – Design problems will provide practice EE40 Summer 2010 Hug 2 Project 2 • Booster lab actually due next week – For Booster lab, ignore circuit simulation, though it may be instructive to try the Falstad simulator • Project 2 due next Wednesday – Presentation details to come [won’t be mandatory, but we will ask everyone about their circuits at some point] EE40 Summer 2010 Hug 3 Project 2 • For those of you who want to demo Project 2, we’ll be doing demos in lab on Wednesday at some point – Will schedule via online survey EE40 Summer 2010 Hug 4 CMOS/NMOS Design Correction • (Sent by email) • My on-the-fly explanation was correct, but not the most efficient way – If your FET circuit is implementing a logic function with a bar over it, i.e. • 푍 = 퐴 + 퐵퐶 + 퐷 + 퐸퐹 퐺 + 퐻 – Then don’t put an inverter at the output, it just makes things harder and less efficient • Sorry, on-the-fly-explanations can be dicey EE40 Summer 2010 Hug 5 CMOS • CMOS Summary: – No need for a pull-up or pull-down resistor • Though you can avoid this even with purely NMOS logic (see HW7) – Greatly reduced static power dissipation vs.
    [Show full text]
  • A Vertical Resonant Tunneling Transistor for Application in Digital Logic Circuits
    1028 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 6, JUNE 2001 A Vertical Resonant Tunneling Transistor for Application in Digital Logic Circuits Jürgen Stock, Jörg Malindretos, Klaus Michael Indlekofer, Michael Pöttgens, Arno Förster, and Hans Lüth Abstract—A vertical resonant tunneling transistor (VRTT) has In this paper, we report on the fabrication of a vertical res- been developed, its properties and its application in digital logic onant tunneling transistor (VRTT) with low peak voltage and circuits based on the monostable-bistable transition logic element good peak current control by means of a Schottky gate. The (MOBILE) principle are described. The device consists of a small mesa resonant tunneling diode (RTD) in the GaAs/AlAs material asymmetric behavior of the current-voltage ( ) character- system surrounded by a Schottky gate. We obtain low peak voltages istics is analyzed and the transistors are characterized with re- using InGaAs in the quantum well and the devices show an excel- spect to their peak voltage, peak-to-valley ratio (PVR), peak cur- lent peak current control by means of an applied gate voltage. A rent density, and gate function. We demonstrate the switching self latching inverter circuit has been fabricated using two VRTTs functionality of a self latching inverter circuit consisting of two and the switching functionality was demonstrated at low frequen- cies. VRTTs. Index Terms—Monostable-bistable transition logic element (MOBILE), monostable-to-bistable transition, resonant tunneling II. DEVICE FABRICATION diode (RTD), resonant tunneling transistor. A. Layer Structure The epitaxial structure used to fabricate the VRTT device was I. INTRODUCTION grown by molecular beam epitaxy (MBE) on semi-insulating N recent years, several new memory and logic circuits based (100)-orientated GaAs substrate.
    [Show full text]
  • Universal Gate - NAND Digital Electronics 2.2 Intro to NAND & NOR Logic
    Universal Gate - NAND Digital Electronics 2.2 Intro to NAND & NOR Logic Universal Gate – NAND This presentation will demonstrate • The basic function of the NAND gate. • How a NAND gate can be used to replace an AND gate, an OR gate, or an INVERTER gate. • How a logic circuit implemented with AOI logic gates can Universal Gate – NAND be re-implemented using only NAND gates. • That using a single gate type, in this case NAND, will reduce the number of integrated circuits (IC) required to implement a logic circuit. Digital Electronics AOI Logic NAND Logic 2 More ICs = More $$ Less ICs = Less $$ NAND Gate NAND Gate as an Inverter Gate X X X (Before Bubble) X Z X Y X Y X Z X Y X Y Z X Z 0 0 1 0 1 Equivalent to Inverter 0 1 1 1 0 1 0 1 1 1 0 3 4 Project Lead The Way, Inc Copyright 2009 1 Universal Gate - NAND Digital Electronics 2.2 Intro to NAND & NOR Logic NAND Gate as an AND Gate NAND Gate as an OR Gate X X Y Y X X Z X Y X Y Y Z X Y X Y X Y Y NAND Gate Inverter Inverters NAND Gate X Y Z X Y Z 0 0 0 0 0 0 0 1 0 0 1 1 Equivalent to AND Gate Equivalent to OR Gate 1 0 0 1 0 1 1 1 1 1 1 1 5 6 NAND Gate Equivalent to AOI Gates Process for NAND Implementation 1.
    [Show full text]
  • Diode Logic). • Explain the Need for Introducing Transistors in the Output (DTL and TTL
    Lecture 02: Logic Families R.J. Harris & D.G. Bailey Objectives • Show how diodes can be used to form logic gates (Diode logic). • Explain the need for introducing transistors in the output (DTL and TTL). • Explain why Schottky transistors improve the speed of gates. • Describe the operating principles of CMOS logic gates. • Explain the definitions of noise margin, fanout, propagation delay, rise and fall time. Semester 2 - 2006 Digital Electronics Slide 2 Review of Previous Lecture • You can now: – Describe the important differences between analogue and digital signals. – Show how to represent more than two levels using digital signals. – Manipulate different codes for representing numbers and letters: • natural binary, signed binary, twos complement, offset binary, Gray codes, ASCII characters. – Show how to convert between binary and base 10. – Write down the logic symbols for • AND, OR, NOT, NAND and NOR gates. – Draw up a truth table to represent relationships between inputs and outputs of a logic circuit. Semester 2 - 2006 Digital Electronics Slide 3 Presentation Outline • Diode Transistor Logic • TTL • Schottky TTL • CMOS • Tristate logic outputs • Definitions: – Noise margin, fanout – Timing: rise and fall times, propagation delay – Power dissipation • Power supply decoupling Semester 2 - 2006 Digital Electronics Slide 4 Diode Logic – AND Gate • Recall that a diode behaves like a switch. – When the diode is forward biased, the switch is closed, allowing a current to flow through it. When reverse biased, it is like a switch that is turned off - no current flows. • First we shall look at an AND gate. – If either input A or input B goes low, it will forward bias the corresponding diode.
    [Show full text]
  • Digital IC Listing
    BELS Digital IC Report Package BELS Unit PartName Type Location ID # Price Type CMOS 74HC00, Quad 2-Input NAND Gate DIP-14 3 - A 500 0.24 74HCT00, Quad 2-Input NAND Gate DIP-14 3 - A 501 0.36 74HC02, Quad 2 Input NOR DIP-14 3 - A 417 0.24 74HC04, Hex Inverter, buffered DIP-14 3 - A 418 0.24 74HC04, Hex Inverter (buffered) DIP-14 3 - A 511 0.24 74HCT04, Hex Inverter (Open Collector) DIP-14 3 - A 512 0.36 74HC08, Quad 2 Input AND Gate DIP-14 3 - A 408 0.24 74HC10, Triple 3-Input NAND DIP-14 3 - A 419 0.31 74HC32, Quad OR DIP-14 3 - B 409 0.24 74HC32, Quad 2-Input OR Gates DIP-14 3 - B 543 0.24 74HC138, 3-line to 8-line decoder / demultiplexer DIP-16 3 - C 603 1.05 74HCT139, Dual 2-line to 4-line decoders / demultiplexers DIP-16 3 - C 605 0.86 74HC154, 4-16 line decoder/demulitplexer, 0.3 wide DIP - Small none 445 1.49 74HC154W, 4-16 line decoder/demultiplexer, 0.6wide DIP none 446 1.86 74HC190, Synchronous 4-Bit Up/Down Decade and Binary Counters DIP-16 3 - D 637 74HCT240, Octal Buffers and Line Drivers w/ 3-State outputs DIP-20 3 - D 643 1.04 74HC244, Octal Buffers And Line Drivers w/ 3-State outputs DIP-20 3 - D 647 1.43 74HCT245, Octal Bus Transceivers w/ 3-State outputs DIP-20 3 - D 649 1.13 74HCT273, Octal D-Type Flip-Flops w/ Clear DIP-20 3 - D 658 1.35 74HCT373, Octal Transparent D-Type Latches w/ 3-State outputs DIP-20 3 - E 666 1.35 74HCT377, Octal D-Type Flip-Flops w/ Clock Enable DIP-20 3 - E 669 1.50 74HCT573, Octal Transparent D-Type Latches w/ 3-State outputs DIP-20 3 - E 674 0.88 Type CMOS CD4000 Series CD4001, Quad 2-input
    [Show full text]
  • Digital Logic and Design (Course Code: EE222) Ltlecture 6: Lliogic Famili Es
    Indian Institute of Technology Jodhpur, Year 2018‐2019 Digital Logic and Design (Course Code: EE222) LtLecture 6: LiLogic Fam ilies Course Instructor: Shree Prakash Tiwari EilEmail: sptiwari@iitj .ac.i n Webpage: http://home.iitj.ac.in/~sptiwari/ Course related documents will be uploaded on http://home.iitj.ac.in/~sptiwari/DLD/ Note: The information provided in the slides are taken form text books Digital Electronics (including Mano & Ciletti), and various other resources from internet, for teaching/academic use only 1 Overview •Early families (DL, RTL) • TTL •Evolution of TTL family • CMOS family and its evolution 2 Logic families Diode Logic (DL) •simpp;lest; does not scale •NOT not possible (need = an active element) Resistor-Transistor Logic (RTL) • replace diode switch with a tittransistor switc h •can be cascaded = • large power draw 3 Logic families Diode-Transistor Logic (DTL) • essentially diode logic with transistor amplification • reduced power consumption •faster than RTL = DL AND gate Saturating inverter 4 Logic Families • The bipolar transistor as a logical switch TTL Bipolar Transistor-Transistor Logic (TTL) •First introduced by in 1964 (Texas Instruments) •TTL has shaped digital technology in many ways • Standard TTL family (e.g. 7400) is obsolete •Newer TTL families used (e.g. 74ALS00) 6 TTL Bipolar Transistor-Transistor Logic (TTL) Distinct features •Multi‐emitter transistors 7 TTL A Standard TTL NAND gate 8 TTL A standard TTL NAND gate with open collector output 9 TTL evolution Schottky series (74LS00) TTL •A major
    [Show full text]
  • Logic Families – Characteristics and Types Table of Content
    1 Module-1: Logic Families – Characteristics and Types Table of Content 1.1 Introduction 1.2 Logic families 1.3 Positive and Negative logic 1.4 Types of logic families 1.5 Characteristics of logic families 1.6 Evolution of logic families 1.7 Classification of logic families 1.8 Summary Learning Outcome: After completing this module, you will be able to 1. Understand need of logic digital ICs 2. Understand significance of logic families 3. Understand characteristics of logic families 4. Identify different types of logic families 5. Know about evolution of different logic families Digital Electronics Electronic Science 1. Logic families 2 1.1 Introduction The first logic circuit was developed using discrete circuit components. Using advance techniques, these complex circuits can be miniaturized and produced on a small piece of semiconductor material like silicon. Such a circuit is called integrated circuit (IC). Now-a-days, all the digital circuits are available in IC form. While producing digital ICs, different circuit configurations and manufacturing technologies are used. This results into a specific logic family. Each logic family designed in this way has identical electrical characteristics such as supply voltage range, speed of operation, power dissipation, noise margin etc. In this module, we discuss significance and types of logic families. The positive and negative logic and its significance are also discussed. In addition to this, different characteristics which are the key parameters in deciding the logic family for any circuit design are discussed in detail. The module is concluded with explanation of the brief history of the logic family in terms of discrete logic circuits.
    [Show full text]
  • Static CMOS Circuits
    Static CMOS Circuits • Conventional (ratio-less) static CMOS – Covered so far • Ratio-ed logic (depletion load, pseudo nMOS) • Pass transistor logic ECE 261 Krish Chakrabarty 1 Example 1 module mux(input s, d0, d1, output y); assign y = s ? d1 : d0; endmodule 1) Sketch a design using AND, OR, and NOT gates. ECE 261 Krish Chakrabarty 2 1 Example 1 module mux(input s, d0, d1, output y); assign y = s ? d1 : d0; endmodule 1) Sketch a design using AND, OR, and NOT gates. ECE 261 Krish Chakrabarty 3 Example 2 2) Sketch a design using NAND, NOR, and NOT gates. Assume ~S is available. ECE 261 Krish Chakrabarty 4 2 Example 2 2) Sketch a design using NAND, NOR, and NOT gates. Assume ~S is available. ECE 261 Krish Chakrabarty 5 Bubble Pushing • Start with network of AND / OR gates • Convert to NAND / NOR + inverters • Push bubbles around to simplify logic – Remember DeMorgan’s Law ECE 261 Krish Chakrabarty 6 3 Example 3 3) Sketch a design using one compound gate and one NOT gate. Assume ~S is available. ECE 261 Krish Chakrabarty 7 Example 3 3) Sketch a design using one compound gate and one NOT gate. Assume ~S is available. ECE 261 Krish Chakrabarty 8 4 Compound Gates • Logical Effort of compound gates ECE 261 Krish Chakrabarty 9 Example 4 • The multiplexer has a maximum input capacitance of 16 units on each input. It must drive a load of 160 units. Estimate the delay of the NAND and compound gate designs. H = 160 / 16 = 10 B = 1 N = 2 ECE 261 Krish Chakrabarty 10 5 NAND Solution ECE 261 Krish Chakrabarty 11 NAND Solution ECE 261 Krish Chakrabarty 12 6 Compound Solution ECE 261 Krish Chakrabarty 13 Compound Solution ECE 261 Krish Chakrabarty 14 7 Example 5 • Annotate your designs with transistor sizes that achieve this delay.
    [Show full text]
  • Design a 3-Input CMOS NAND Gate (PUN/PDN) with Fan-Out of 3. Total Output Load of the NAND Gate Is Equal to 15Ff and Μn/Μp = 2.5
    Tutorial on Transistor Sizing Problem #1 (Static CMOS logic): Design a 3-input CMOS NAND gate (PUN/PDN) with fan-out of 3. Total output load of the NAND gate is equal to 15fF and µn/µp = 2.5. For 0.35µm process technology tox = -9 -12 7.6*10 m, εox = 35*10 F/m. Compare the above design with that of a 3-input NOR (PUN/PDN) gate. State any benefits of one implementation over the other. For the sake of simplicity assume all capacitance is lumped and gate capacitance neglecting diffusion and wiring capacitance. Solution: Cox = εoxWL/ tox = 15fF. So W = 9.2µm. Leff = 0.35µm. Assuming output load is all gate capacitance. This is a simplifying assumption made for this problem. A more realistic approach would be to calculate the diffusion and wiring capacitances as well. Equivalent inverter for fan-out of 3 and µn/µp = 2.5 would result in: A B C 2.23 2.23 2.23 Wp = 2.5*Wn for equal rise and fall times. Also, Wp + Wn = 9.2/3 = 3.16µm for fan-out of 3. A 2.67 B Solving the above equations we have, 2.67 C 2.67 Wp = 2.23µm and Wn = 0.89µm. NAND implementation: NAND implementation Therefore, for the 3-ip NAND gate implementation, each PDN n-MOS transistor will be: 3*0.89µm = 2.67µm A and each p-MOS transistor in the PUN network will be: 2.23µm 6.69 B NOR implementation: 6.69 For a 3-ip NOR gate implementation, each PDN n-MOS transistor C will be: 0.89µm 6.69 A BC Each PUN p-MOS transistor will be 3*2.23µm = 6.69µm 0.89 0.89 0.89 Area comparison: NOR implementation Total gate area of NAND gate is: 3*(2.67+2.23)µm = 14.7µm Total gate area of NOR gate is: 3*(6.69+0.89) µm = 22.7µm Thus we infer that the NAND gate has less area and power compared to the NOR gate for identical loading and fan-out conditions and is the preferred implementation.
    [Show full text]
  • Hardware Abstract the Logic Gates References Results Transistors Through the Years Acknowledgements
    The Practical Applications of Logic Gates in Computer Science Courses Presenters: Arash Mahmoudian, Ashley Moser Sponsored by Prof. Heda Samimi ABSTRACT THE LOGIC GATES Logic gates are binary operators used to simulate electronic gates for design of circuits virtually before building them with-real components. These gates are used as an instrumental foundation for digital computers; They help the user control a computer or similar device by controlling the decision making for the hardware. A gate takes in OR GATE AND GATE NOT GATE an input, then it produces an algorithm as to how The OR gate is a logic gate with at least two An AND gate is a consists of at least two A NOT gate, also known as an inverter, has to handle the output. This process prevents the inputs and only one output that performs what inputs and one output that performs what is just a single input with rather simple behavior. user from having to include a microprocessor for is known as logical disjunction, meaning that known as logical conjunction, meaning that A NOT gate performs what is known as logical negation, which means that if its input is true, decision this making. Six of the logic gates used the output of this gate is true when any of its the output of this gate is false if one or more of inputs are true. If all the inputs are false, the an AND gate's inputs are false. Otherwise, if then the output will be false. Likewise, are: the OR gate, AND gate, NOT gate, XOR gate, output of the gate will also be false.
    [Show full text]
  • Chapter 6 - Combinational Logic Systems GCSE Electronics – Component 1: Discovering Electronics
    Chapter 6 - Combinational logic systems GCSE Electronics – Component 1: Discovering Electronics Combinational logic systems Learners should be able to: (a) recognise 1/0 as two-state logic levels (b) identify and use NOT gates and 2-input AND, OR, NAND and NOR gates, singly and in combination (c) produce a suitable truth table from a given system specification and for a given logic circuit (d) use truth tables to analyse a system of gates (e) use Boolean algebra to represent the output of truth tables or logic gates and use the basic Boolean identities A.B = A+B and A+B = A.B (f) design processing systems consisting of logic gates to solve problems (g) simplify logic circuits using NAND gate redundancy (h) analyse and design systems from a given truth table to solve a given problem (i) use data sheets to select a logic IC for given applications and to identify pin connections (j) design and use switches and pull-up or pull-down resistors to provide correct logic level/edge-triggered signals for logic gates and timing circuits 180 © WJEC 2017 Chapter 6 - Combinational logic systems GCSE Electronics – Component 1: Discovering Electronics Introduction In this chapter we will be concentrating on the basics of digital logic circuits which will then be extended in Component 2. We should start by ensuring that you understand the difference between a digital signal and an analogue signal. An analogue signal Voltage (V) Max This is a signal that can have any value between the zero and maximum of the power supply. Changes between values can occur slowly or rapidly depending on the system involved.
    [Show full text]