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Ratioed Logic Ratioed Logic 1 Digital IC EE141 Introduction Ratioed Logic design • Basic concept • Resistive load • Depletion NMOS • Pseudo NMOS • DCVSL logic • Pseudo NMOS logic effort Digital IC 2 Ratioed Logic VDD VDD VDD Resistive Depletion PMOS Load RL Load VT < 0 Load VSS F F F In1 In1 In1 In2 PDN In2 PDN In2 PDN In3 In3 In3 VSS VSS VSS (a) resistive load (b) depletion load NMOS (c) pseudo-NMOS Goal: to reduce the number of devices over complementary CMOS Digital IC 3 How to obtain a good load • What is a good load • Low power • VOL tend to zero • Charge time short (large charge current) • Memory address decoder match the structure • Low power when address hold the line • Change quickly when address content is changed Digital IC 4 Ratioed Logic design • Basic concept • Resistive load • Depletion NMOS • Pseudo NMOS • DCVSL logic • Pseudo NMOS logic effort Digital IC 5 Ratioed Logic-resistive load VDD • N transistors + Load Resistive • V = V Load OH DD RL • VOL = RPN F RPN + RL In1 • Assymetrical response In2 PDN In3 • Static power consumption • tpL= 0.69 RLCL VSS Digital IC 6 Resistive load • Could not be to low RPDN VOL = VDD RPDN + RL • In order to obtain wide range low noise margin， RL>>RPDN • Then resistive size should be adjust • Could not be to high • Then enough large current could give quick switch time, because t pLH = 0.69RLC L t pHL = 0.69(RL RPDN )CL • Decrease power consumption as soon as possible Digital IC 7 Ratioed Logic design • Basic concept • Resistive load • Depletion NMOS • Pseudo NMOS • DCVSL logic • Pseudo NMOS logic effort Digital IC 8 Active Loads VDD VDD Depletion PMOS Load VT < 0 Load VSS F F In1 In1 In2 PDN In2 PDN In3 In3 VSS VSS depletion load NMOS pseudo-NMOS Depletion load has negative threshold voltage Digital IC 9 Depletion NMOS load • It is reasonable when we assume the load transistor works at saturate state, just like a current source k 2 I = n,load V L 2 Tn • Practically, the load curve slant down • Load transistor’s source is connect with output, which VSB will effect threshold voltage of the transistor • Compared with resistive load, depletion load has smaller area • 40kΩ resistive load need 3200µm2(0.5um) which could occupy 1000 unit transistor Digital IC 10 Ratioed Logic design • Basic concept • Resistive load • Depletion NMOS • Pseudo NMOS • DCVSL logic • Pseudo NMOS logic effort Digital IC 11 Pseudo-NMOS ratios computing • PMOS’s source and substrate voltage is always zero，that means no body effect • Load transistor’s saturate current is k I = p (V − V )2 L 2 DD Tp pMOS load current is larger than that of nMOS Digital IC 12 Pseudo NMOS logic design rule • Static power k P =V I = p V (V −V )2 average dd low 2 dd dd T • Constrains should be regarded • ILshould be low in order to decrease power • VOL=ILRPDN should be lower in order to obtain effective low voltage • ILshould high in order to decrease tpLH=(CLVdd)/(2IL) • RPDNshould be small in order to decrease tpHL=0.69RPDNCL, Pull-down transistors should be wider ,but we can not benefit from both power and delay Digital IC 13 Pseudo-NMOS VTC 3.0 2.5 2.0 W/L = 4 p 1.5 [V] t u W/L = 2 o p V 1.0 W/L = 0.5 p W/Lp = 1 0.5 W/Lp = 0.25 0.0 0.0 0.5 1.0 1.5 2.0 2.5 Vin [V] Digital IC 14 Load curve analysis • Resistive load VDD −Vout I L = RL • More output voltage, lower charge current, which increase charge time • Ideally, constant current source • Charge current does not be decreased by output voltage Digital IC 15 Pseudo-NMOS NMOS ratioed logic • Pseudo-NMOS ratioed logic merits • N-fan-in needs N+1 transistors，with smaller area and parasitic capacity • Every input only connects with one transistor, which load capacity is smaller as front stage logic. • shortcoming • Static power，1mW per logic，50W consumption if chip has 100,000 such logic structure！ • application • Can not fit for large scale circuit • Only apply on high speed circuit • Only apply on 1-state on most output(such as address decoder) • Large fan-in Digital IC 16 Improved Loads VDD M1 Enable M2 M1 >> M2 F CL A B C D Adaptive Load Digital IC 17 Improved Loads (2) VDD VDD M1 M2 Out Out A A PDN1 PDN2 B B VSS VSS Differential Cascode Voltage Switch Logic (DCVSL) Digital IC 18 Ratioed Logic design • Basic concept • Resistive load • Depletion NMOS • Pseudo NMOS • DCVSL logic • Pseudo NMOS logic effort Digital IC 19 DCVSL Example Out 2.5 Out A B [V] 1.5 e g A B a t B B B B l o V A, B 0.5 A,B A A -0.5 0 0.2 0.4 0.6 0.8 1.0 Time [ns] XOR-NXOR gate Digital IC 20 Pseudo-nMOS Power • Pseudo-nMOS draws power whenever Y = 0 • Called static power P = I•VDD • A few mA / gate * 1M gates would be a problem • This is why nMOS went extinct! • Use pseudo-nMOS sparingly for wide NORs • Turn off pMOS when not in use en Y A B C Digital IC 21 Pass-Transistor Logic 22 Digital IC EE141 Introduction Pass- transistor logic outline • Pass-transistor principle • Pass-transistor VTC • How to solve pass-transistor threshold drop issue • Solution 1:Level Restoring Transistor Resistive issue • Solution 2: Single Transistor Pass Gate with VT=0 • Solution 3: Transmission Gate Complementary Pass- Transistor Logic • Transmission gate principle • Some issues of transmission gate • Resistive issue • Delay issue Digital IC 23 Pass-Transistor Logic B Out A Switch s t Out u p n Network B I B • N transistors • No static consumption Pass-transistor logic is a path, not a road connected with rail directly！ Digital IC 24 Example: AND Gate B A B F = AB 0 Digital IC 25 NMOS-Only Logic In 1.5µm/ 0.2 5 µm VDD x Out 3.0 0.5µm/0 .2 5µm In 0.5µm/ 0.2 5 µm Out 2.0 [V] x ， q NMOS keep “on” then e g a t l o V >V V GS t 1.0 q VDG=0,which means 0.0 NMOS always works in 0 0.5 1 1.5 2 Time [ns] the saturation state Digital IC 26 NMOS-only Switch C = 2.5 V C = 2.5 V M2 A = 2.5 V A = 2.5 V B Mn B M CL 1 V B does not pull up to 2.5V, but 2.5V - V TN Threshold voltage loss causes static power consumption NMOS has higher threshold than PMOS (body effect) Digital IC 27 The proper way of cascading pass gates • Weak for passing high voltage Vs = min{VG −VT ,VD} • Proper way of cascading pass transistors,which will not accumulate threshold drop Digital IC 28 Output of passing-transistor should not be connected with the gate of next stage Digital IC 29 Nonrestoring Tristate • Transmission gate acts as tristate buffer • Only two transistors • But nonrestoring • Noise on A is passed on to Y EN A Y EN Digital IC Slide 30 Tristate Inverter • Tristate inverter produces restored output • Violates conduction complement rule • Because we want a Z output A EN Y EN Digital IC Slide 31 Tristate Inverter • Tristate inverter produces restored output • Violates conduction complement rule • Because we want a Z output A A A EN Y Y Y EN EN = 0 EN = 1 Y = 'Z' Y = A Digital IC Slide 32 Gate-Level Mux Design • YSDSD=+10 (too many transistors) • How many transistors are needed? Digital IC Slide 33 Gate-Level Mux Design • YSDSD=+10 (too many transistors) • How many transistors are needed? 20 D1 S Y D0 D1 S 4 2 4 2 Y D0 4 2 2 Digital IC Slide 34 Transmission Gate Mux • Nonrestoring mux uses two transmission gates Digital IC Slide 35 Transmission Gate Mux • Nonrestoring mux uses two transmission gates • Only 4 transistors S D0 S Y D1 S Digital IC Slide 36 Inverting Mux • Inverting multiplexer • Use compound AOI22 • Or pair of tristate inverters • Essentially the same thing • Noninverting multiplexer adds an inverter D0 S D0 D1 S S D1 S S Y Y D0 0 S S S S Y D1 1 Digital IC Slide 37 4:1 Multiplexer • 4:1 mux chooses one of 4 inputs using two selects • Two levels of 2:1 muxes • Or four tristates S1S0 S1S0 S1S0 S1S0 D0 S0 S1 D0 0 D1 D1 1 0 Y Y 1 D2 0 D2 D3 1 D3 Digital IC Slide 38 Pass- transistor logic outline • Pass-transistor principle • Pass-transistor VTC • How to solve pass-transistor threshold drop issue • Solution 1:Level Restoring Transistor Resistive issue • Solution 2: Single Transistor Pass Gate with VT=0 • Solution 3: Transmission Gate Complementary Pass- Transistor Logic • Transmission gate principle • Some issues of transmission gate • Resistive issue • Delay issue Digital IC 39 Complementary Pass Transistor Logic A Pass-Transistor A F B Network B (a) A Inverse A Pass-Transistor F B B Network B B B B B B A A A B F=AB B F=A+B A F=A⊕ΒÝ (b) A A A B F=AB B F=A+B A F=A⊕ΒÝ AND/NAND OR/NOR EXOR/NEXOR Digital IC 40 Pass- transistor logic outline • Pass-transistor principle • Pass-transistor VTC • How to solve pass-transistor threshold drop issue • Solution 1:Level Restoring Transistor Resistive issue • Solution 2: Single Transistor Pass Gate with VT=0 • Solution 3: Transmission Gate Complementary Pass- Transistor Logic • Transmission gate principle • Some issues of transmission gate • Resistive issue • Delay issue Digital IC 41 Solution 1:Level Restoring Transistor V DD Level Restorer V DD M r B M 2 X A M n Out M 1 • Advantage: Full Swing • Restorer adds capacitance, takes away pull down current at X • Ratio problem Digital IC 42 Restorer Sizing 3.0 •Upper limit on restorer size •Pass-transistor pull-down 2.0 can have several transistors in W/L =1.75/0.25 [V] r stack e g W /L r =1.50/0.25 a t l o V 1.0 W/L =1.0/0.25 W /L r =1.25/0.25 r 0.0 0 100 200 300 400 500 Time [ps] Digital IC 43 pass- transistor logic outline • Pass-transistor principle • Pass-transistor VTC • How to solve pass-transistor threshold drop issue • Solution 1:Level Restoring Transistor Resistive issue • Solution 2: Single Transistor Pass Gate with VT=0 • Solution 3l: Transmission Gate Complementary Pass- Transistor Logic • Transmission gate principle • Some issues of transmission gate • Resistive issue
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