Chapter 10 Differential

 10.1 General Considerations

 10.2 Bipolar Differential Pair

 10.3 MOS Differential Pair

 10.4 Differential Amplifiers

 10.5 Common-Mode Rejection

 10.6 Differential Pair with Active Load

1 Audio Example

 An audio amplifier is constructed as above that takes a rectified AC as its supply and amplifies an audio signal from a microphone.

CH 10 Differential Amplifiers 2 “Humming” Noise in Audio Amplifier Example

 However, VCC contains a ripple from rectification that leaks to the output and is perceived as a “humming” noise by the user.

CH 10 Differential Amplifiers 3 Supply Ripple Rejection

vX  Avvin  vr

vY  vr

vX  vY  Avvin

 Since both node X and Y contain the same ripple, their difference will be free of ripple.

CH 10 Differential Amplifiers 4 Ripple-Free Differential Output

 Since the signal is taken as a difference between two nodes, an amplifier that senses differential signals is needed.

CH 10 Differential Amplifiers 5 Common Inputs to

vX  Avvin  vr

vY  Avvin  vr

vX  vY  0

 Signals cannot be applied in phase to the inputs of a differential amplifier, since the outputs will also be in phase, producing zero differential output.

CH 10 Differential Amplifiers 6 Differential Inputs to Differential Amplifier

vX  Avvin  vr

vY  Avvin  vr

vX  vY  2Avvin

 When the inputs are applied differentially, the outputs are 180° out of phase; enhancing each other when sensed differentially.

CH 10 Differential Amplifiers 7 Differential Signals

 A pair of differential signals can be generated, among other ways, by a transformer.  Differential signals have the property that they share the same average value (DC) to ground and AC values are equal in magnitude but opposite in phase.

CH 10 Differential Amplifiers 8 Single-ended vs. Differential Signals

CH 10 Differential Amplifiers 9 Example 10.3

 Determine the common-mode level at the output of the circuit shown in Fig. 10.3(b).

In the absence of signals,

VVVRIX Y  CC  C C

and where RRRCCC1  2

IC denotes the bias current of Q1 and Q2

Thus, VVRICM CC  C C

Interestingly, the ripple affects VCM but not the differential output.

CH 10 Differential Amplifiers 10 Differential Pair

 With the addition of a tail current, the circuits above operate as an elegant, yet robust differential pair.

CH 10 Differential Amplifiers 11 Common-Mode Response

VBE1  VBE 2 I I  I  EE C1 C 2 2 I V  V  V  R EE X Y CC C 2

To avoid saturation, the collector must not fall below the base voltages: I VRVEE  CCCCM2

CH 10 Differential Amplifiers 12 Example 10.4

 A bipolar differential pair employs a load resistance of 1 kΩ and a tail current of 1 mA. How close to VCC can VCM be chosen?

I VVR  EE CC CM C 2 0  5V

That is, VCM must remain below VCC by at least 0.5 V.

CH 10 Differential Amplifiers 13 Common-Mode Rejection

 Due to the fixed tail , the input common- mode value can vary without changing the output common- mode value.

CH 10 Differential Amplifiers 14 Differential Response I

IC1  I EE

IC2  0

VX VCC  RC I EE

VY VCC

CH 10 Differential Amplifiers 15 Differential Response II

IC2  I EE

IC1  0

VY VCC  RC I EE

VX VCC

CH 10 Differential Amplifiers 16 Differential Pair Characteristics

 None-zero differential input produces variations in output currents and voltages, whereas common-mode input produces no variations.

CH 10 Differential Amplifiers 17 Example 10.5

 A bipolar differential pair employs a tail current of 0.5 mA and a collector resistance of 1 kΩ. What is the maximum allowable base voltage if the differential input is large enough to

completely steer the tail current? Assume VCC=2.5V.

Because IEE is completely steered,

VRIVCC- C EE  2 at one collector.

To avoid saturation, VVB  2 .

CH 10 Differential Amplifiers 18 Small-Signal Analysis

I I  EE  I C1 2 I I  EE  I C 2 2

 Since the input to Q1 and Q2 rises and falls by the same amount, and their emitters are tied together, the rise in IC1 has the same magnitude as the fall in IC2.

CH 10 Differential Amplifiers 19 Virtual Ground

IC1  g m()  V   V P 

VP  0 IC2   g m()  V   V P  I  g V IICC2   1  0 C1 m gm()() V   V P  g m  V   V P IC 2  gmV

 For small changes at inputs, the gm’s are the same, and the respective increase and decrease of IC1 and IC2 are the same, node P must stay constant to accommodate these changes. Therefore, node P can be viewed as AC ground.

CH 10 Differential Amplifiers 20 Small-Signal Differential Gain

VX   g m  VR C V  g  VR  2g VR Y m C A  m C  g R v 2V m C VX   V Y  2 g m  VR C

 Since the output changes by -2gmVRC and input by 2V, the small signal gain is –gmRC, similar to that of the CE stage. However, to obtain same gain as the CE stage, power dissipation is doubled.

CH 10 Differential Amplifiers 21 Example 10.6

 Design a bipolar differential pair for a gain of 10 and a power budget of 1mW with a supply voltage of 2V.

VCC  2 V 1 mW I   0.5 mA EE 2 V

IC I EE / 2 0.25 mA 1 gm     VVTT 26 mV 104 

Av RC  1040  gm

CH 10 Differential Amplifiers 22 Example 10.7

 Compare the power dissipation of a bipolar differential pair with that of a CE stage if both circuits are designed for equal voltage gains, collector resistances, and supply voltages.

Differential pair CE stage

AVdiff  g m 1  2 R C AV CE  g m R C

gm1 2 R C g m R C I I EE  C 2VVTT

IIEE 2 C

PVIVID, diff C EE  2 C C PVIDCECC, 

CH 10 Differential Amplifiers 23 Large Signal Analysis

VVVVin1 in 2  BE 1  BE 2

IICC1 2 VVTT ln  ln IISS1 2

and IIIC1 C 2  EE

VVin1 in 2 IIIC2exp  C 2  EE VT I I  EE C2 VV 1 exp in1 in 2 VT VV I exp in1 in 2 EE V I  T C1 VV 1 exp in1 in 2 VT

CH 10 Differential Amplifiers 24 Example 10.8

 Determine the differential input voltage that steers 98% of the tail current to one .

IIC1 0  02 EE

VVin1 in 2  I EE exp VT

VVVin1 in 2  3  91  T 

We often say a differential input of 4VT is sufficient to turn one side of the bipolar pair nearly off.

CH 10 Differential Amplifiers 25 Input/Output Characteristics

VVRIout1 CC  C C 1 VV I exp in1 in 2 EE V VR  T CC C VV 1 exp in1 in 2 VT

VVRIout2 CC  C C 2 I VR  EE CC C VV 1 exp in1 in 2 VT VV 1 exp in1 in 2 V VVRI  T out1 out 2 C EE VV 1 exp in1 in 2 VT

VVin1 in 2  RIC EE tanh 2VT

CH 10 Differential Amplifiers 26 Example 10.9

 Sketch the output waveforms of the bipolar differential pair in Fig. 10.14(a) in response to the sinusoidal inputs shown in Figs.

10.14(b) and (c). Assume Q1 and Q2 remain in the forward active region.

Figure10.14 (a) CH 10 Differential Amplifiers 27 Example 10.9 (cont’d)

 The left column operates in linear region (small-signal), whereas the right column operates in nonlinear region (large-signal).

CH 10 Differential Amplifiers 28 Small-Signal Model

vin1 v 1  v P  v in 2  v  2

v1 v  2 gm1 v 1   g m 2 v  2 0  r1 r  2

With r1 r  2 and gm1 g m 2 v1  v  2

Since vin1  v in 2 , 2vin1 2 v 1 .

vP  v in1  v 1  0

CH 10 Differential Amplifiers 29 Half Circuits

vout1  vout 2  g m RC vin1  vin2

 Since VP is grounded, we can treat the differential pair as two CE “half circuits”, with its gain equal to one half circuit’s single-ended gain. CH 10 Differential Amplifiers 30 Example 10.10

 Compute the differential gain of the circuit shown in Fig. 10.16(a), where ideal current sources are used as loads to maximize the gain.

v  v out1 out 2  g r Figure10.16 (a) m O vin1  vin 2

CH 10 Differential Amplifiers 31 Example 10.11

 Figure 10.17(a) illustrates an implementation of the topology shown in Fig. 10.16(a). Calculate the differential voltage gain.

vout1 v out 2  gm r ON r OP  vin1 v in 2 Figure10.17 (a) CH 10 Differential Amplifiers 32 Extension of Virtual Ground

VX  0

 It can be shown that if R1 = R2, and points A and B go up and down by the same amount respectively, VX does not move. This property holds for any other node that appears on the axis of symmetry.

CH 10 Differential Amplifiers 33 Half Circuit Example I

Av  gm1 rO1 || rO3 || R1 

CH 10 Differential Amplifiers 34 Half Circuit Example II

Av  gm1 rO1 || rO3 || R1 

CH 10 Differential Amplifiers 35 Half Circuit Example III

R A   C v 1 RE  gm CH 10 Differential Amplifiers 36 Half Circuit Example IV

R A   C v R 1 E  2 gm CH 10 Differential Amplifiers 37 I/O Impedances

v1 v  2 iX   r1 r  2 i X vX  v1  v  2

 2r1 iX

vX vX Rin   2 r1 iX iX iX In a similar manner,

RRout 2 C

v CH 10 Differential Amplifiers X 38 MOS Differential Pair’s Common-Mode Response

I II  SS DD1 2 2 I VVVR   SS XYDDD 2

 Similar to its bipolar counterpart, MOS differential pair

produces zero differential output as VCM changes.

CH 10 Differential Amplifiers 39 Equilibrium Overdrive Voltage

I I  SS D 2 1 W 2  CVV   2 n oxL GS TH I VV   SS GS TH equil W  C n ox L

 The equilibrium overdrive voltage is defined as the overdrive voltage seen by M1 and M2 when both of them carry a current of ISS/2.

CH 10 Differential Amplifiers 40 Minimum Common-mode Output Voltage

I V  R SS  V V DD D 2 CM TH

 In order to maintain M1 and M2 in saturation, the common- mode output voltage cannot fall below the value above.  This value usually limits voltage gain.

CH 10 Differential Amplifiers 41 Example 10.15

 A MOS differential pair is driven with an input CM level of

1.6V. If ISS=0.5mA, VTH=0.5 V, and VDD=1.8 V, what is the maximum allowable load resistance?

I VRVVSS   DD D2 CM TH

VVVDD CM  TH RD  2 ISS  2.8 k 

CH 10 Differential Amplifiers 42 Differential Response

CH 10 Differential Amplifiers 43 Small-Signal Response

VP 0

ID1  g m  V,

ID2  g m  V

VX  V Y  2 g m R D  V

Av   g m R D

 Similar to its bipolar counterpart, the MOS differential pair exhibits the same virtual ground node and small signal gain.

CH 10 Differential Amplifiers 44 Power and Gain Tradeoff

 In order to obtain the same gain as a CS stage, a MOS differential pair must dissipate twice the amount of current. This power and gain tradeoff is also echoed in its bipolar counterpart.

CH 10 Differential Amplifiers 45 Example 10.16

 Design an NMOS differential pair for a voltage gain of 5 and a power budget of 2 mW subject to the condition that the stage following the differential pair requires an output CM level of at 2 least 1.6V. Assume μnCox=100 μA/V , λ=0, and VDD= 1.8 V.

Textbook 2 mW I  1  11 mA Error! SS 1.8 V I VVR SS 1.6 V CM, out DD D 2

RD 360 

For RD  360  ,

AIv5 W SS gm   2 n C ox RLD 360  2 W  1738 CH 10 Differential Amplifiers L 46 Example 10.17

 What is the maximum allowable input CM level in the previous

example if VTH=0.4 V?

To guarantee that M1 and M 2 operate in saturation, I VVRV SS  CM, in DD D2 TH

VVCM, out  TH . Thus,

VCM, in  2 V

CH 10 Differential Amplifiers 47 Example 10.18

 The common-source stage and the differential pair shown in Fig. 10.28 incorporate equal load . If the two circuits are designed for the same voltage gain and the same supply voltage, discuss the choice of (a) transistor dimensions for a given power budget, (b) power dissipation for given transistor dimensions.

(a) for same power budget,

IIIID1 SS  2 D 2  2 D 3 WW1 1 W 1  2  3 LLL2 2 3 1 2 3 W   g 2 C I m n ox D  L  (b) for same transistor dimensions, Figure10.28 IISS 2 D1

PPdiff  2 CS CH 10 Differential Amplifiers 48 MOS Differential Pair’s Large-Signal Response

Goal is to obtain ID1 - ID2

VVVVin1 GS 1  in 2  GS 2.

IIID1 D 2  SS 

2 ICWLVVD(1  2) n ox (  )( GS  TH ) .

2I VV  D  GS TH W  C n ox L

VVVVin1  in 2  GS 1  GS 2

2 ()II   W DD1 2  C n ox L

CH 10 Differential Amplifiers 49 MOS Differential Pair’s Large-Signal Response (cont’d)

2 (VVIIII )2  (   2 ) in1 in 2W D 1 D 2 D 1 D 2  C n ox L 2 (III  2 )  W SSDD1 2  C n ox L W 4IIICVV  2  (  )2 D1 D 2 SS n oxL in 1 in 2

2   W 2  16IIICVVD1 D 2  2 SS  n ox ( in 1  in 2 )  L 

  2 W 2  16IIIICVVD1 ( SS  D 1 )  2 SS  n ox ( in 1  in 2 )  L 

CH 10 Differential Amplifiers 50 MOS Differential Pair’s Large-Signal Response (cont’d)

  2 2W 2  16IIIICVVD1  16 SS D 1  2 SS  n ox ( in 1  in 2 )   0 L 

  2 ISS 1 2W 2  IICVVID1  4 SS  n ox ( in 1  in 2 )  2 SS  2 4 L 

  IVVSS in1 in 2 WW2   nCICVV ox4 SS   n ox ( in1  in 2 )  2 4 LL 

  IVVSS in2 in 1 WW2  ICICVVD2   n ox4 SS   n ox ( in 2  in 1 )  2 4 LL  ( the symmetry of the circuit)

1 W 4I I  I   C V V  SS  V V 2 D1 D2 n ox in1 in 2 W in1 in2 2 L  C n ox L

CH 10 Differential Amplifiers 51 Maximum Differential Input Voltage

Edge of Conduction ~0 ISS

+ + V V TH - - GS2

VVGS1  TH 2I SS 2I VVVVin1 in 2  2  GS  TH  VV  SS max W equil GS2 TH W  C  C n ox n ox L L

 There exists a finite differential input voltage that completely steers the tail current from one transistor to the other. This value is known as the maximum differential input voltage.

CH 10 Differential Amplifiers 52 Contrast Between MOS and Bipolar Differential Pairs

MOS Bipolar

 In a MOS differential pair, there exists a finite differential input voltage to completely switch the current from one transistor to the other, whereas, in a bipolar pair that voltage is infinite.

CH 10 Differential Amplifiers 53 The effects of Doubling the Tail Current

 Since ISS is doubled and W/L is unchanged, the equilibrium overdrive voltage for each transistor must increase by 2 to accommodate this change, thus Vin,max increases by 2 as well. Moreover, since ISS is doubled, the differential output swing will double.

CH 10 Differential Amplifiers 54 The effects of Doubling W/L

 Since W/L is doubled and the tail current remains unchanged, the equilibrium overdrive voltage will be lowered by 2 to accommodate this change, thus Vin,max will be lowered by as well. Moreover, the differential output swing will remain unchanged since neither ISS nor RD has changed

CH 10 Differential Amplifiers 55 Example 10.20

 Design an NMOS differential pair for a power budget of 3 mW 2 and ∆Vin,max=500 mV. Assume μnCox=100 μA/V and VDD=1.8 V.

3 mW I  1.67 mA SS 1.8 V 2I From VV  SS in1 in 2 max W  C n ox L

W 2ISS 2 133.6 LCVn ox in,max

RD is determined by the required voltage gain.

CH 10 Differential Amplifiers 56 Small-Signal Analysis of MOS Differential Pair

1 W 4I 2 IICVVVV    SS    D1 D 2 n ox in 1 in 2W in 1 in 2 2 L  C n ox L 1 W 4I  CVV   SS n ox in1 in 2 W 2 L  C n ox L W  CIVV   n oxL SS in1 in 2  When the input differential signal is small compared to 1/2 [4ISS/nCox(W/L)] , the output differential current is linearly proportional to it, and small-signal model can be applied.

CH 10 Differential Amplifiers 57 Virtual Ground and Half Circuit

VP  0

Av  g m R D

 Applying the same analysis as the bipolar case, we will arrive at the same conclusion that node P will not move for small input signals and the concept of half circuit can be used to calculate the gain.

CH 10 Differential Amplifiers 58 MOS Differential Pair Half Circuit Example I

  0  1  Av  g m1  || rO3 || rO1   g m3  CH 10 Differential Amplifiers 59 MOS Differential Pair Half Circuit Example II

  0

gm1 Av   gm3 CH 10 Differential Amplifiers 60 MOS Differential Pair Half Circuit Example III

  0

RDD 2 Av   RSS 2 1 gm CH 10 Differential Amplifiers 61 Bipolar Cascode Differential Pair

Av  g m1 g m 3 r O 1|| r 3 r O 3  r O 1 || r  3 

CH 10 Differential Amplifiers 62 of CE Stage with Degeneration

vX i X  g m v r O  v 

iX  g m i X R E || r  r O  i X R E || r  

Rout 1  g m ( R E || r ) r O  R E || r 

rO  ( g m r O  1)( R E || r )

rO 1  g m ( R E || r )

CH 10 Differential Amplifiers 63 Output Impedance of CS Stage with Degeneration

iX gvi m1  X  g m  iR X S  i X  giR m X S

rO i X  g m i X R S  i X R S  v X

Rout  r O1  g m R S  R S

 1 gm r O R S  r O

gm r O R S  r O

CH 10 Differential Amplifiers 64 Bipolar Telescopic Cascode

Av  gm1gm3rO3 rO1 || r 3 || gm5rO5 (rO7 || r 5 )

CH 10 Differential Amplifiers 65 Example: Bipolar Telescopic Parasitic Resistance

RR1   1 Rop r O51  g m 5 r O 7 || r 5 ||    r O 7 || r  5 || 2   2   Av  g m1 g m 3 r O 3( r O 1 || r 3 ) || R op  CH 10 Differential Amplifiers 66 MOS Cascode Differential Pair

Av  gm1rO3 gm3rO1 CH 10 Differential Amplifiers 67 MOS Telescopic Cascode

Av  g m1gm3rO3rO1 || (gm5rO5rO7 ) CH 10 Differential Amplifiers 68 Example: MOS Telescopic Parasitic Resistance

Rop1  g m5 r O 5 || R 1  r O 7  r O 5 || R 1

Av  g m1( R op || r O 3 g m 3 r O 1 ) CH 10 Differential Amplifiers 69 Effect of Finite Tail Impedance

V R / 2 out,CM   C Vin,CM REE 1/ 2g m

 If the tail current source is not ideal, then when a input CM voltage is applied, the currents in Q1 and Q2 and hence output CM voltage will change.

CH 10 Differential Amplifiers 70 Input CM Noise with Ideal Tail Current

CH 10 Differential Amplifiers 71 Input CM Noise with Non-ideal Tail Current

CH 10 Differential Amplifiers 72 Comparison

 As it can be seen, the differential output voltages for both cases are the same. So for small input CM noise, the differential pair is not affected. CH 10 Differential Amplifiers 73 CM to DM Conversion, ACM-DM

VVIRCM   GS 2  D SS

1  ID  IRVD  2 SS  ,   GS  gm  g m V  I  CM D 1  2RSS gm

VVVout   out1   out 2

 IRIRRDDDDD       IR  1 W 2 DD ICVVD1 n ox GS 1  TH  Textbook V 2 L CM Error!  RD 1/g 2 R 1 W 2 m SS ICVV    D2 n ox GS 2 TH V RR  2 L out DD  IIIIVVD1 D 2 &  D 1   D 2 ,  GS 1  GS 2 VCM1/ g m  2 R SS 2 R SS  If finite tail impedance and asymmetry are both present, then the differential output signal will contain a portion of input common-mode signal. CH 10 Differential Amplifiers 74 Example: ACM-DM

ACM DM 

RC 1  2[1 gm3 (R1 || r 3 )]rO3  R1 || r 3  gm1

CH 10 Differential Amplifiers 75 CMRR

A CMRR  DM ACM DM

 CMRR defines the ratio of wanted amplified differential input signal to unwanted converted input common-mode noise that appears at the output. CH 10 Differential Amplifiers 76 Example 10.28

 Calculate the CMRR of the circuit in Fig. 10.46.

A g R CMRR DM  m1 C AACM DM CM  DM

gm1 R C 1    2 [1 gm3 ( R 1 || r 3 )] r O 3  R 1 || r  3   RC g m1  Figure10.46

CH 10 Differential Amplifiers 77 Differential to Single-ended Conversion

 Many circuits require a differential to single-ended conversion, however, the above topology is not very good.

CH 10 Differential Amplifiers 78 Supply Noise Corruption

 The most critical drawback of this topology is supply noise corruption, since no common-mode cancellation mechanism exists. Also, we lose half of the signal.

CH 10 Differential Amplifiers 79 Better Alternative

 This circuit topology performs differential to single-ended conversion with no loss of gain.

CH 10 Differential Amplifiers 80 Active Load

 With used as the load, the signal current

produced by the Q1 can be replicated onto Q4.  This type of load is different from the conventional “static load” and is known as an “active load”.

CH 10 Differential Amplifiers 81 Differential Pair with Active Load

 The input differential pair decreases the current drawn from

RL by I and the active load pushes an extra I into RL by current mirror action; these effects enhance each other.

CH 10 Differential Amplifiers 82 Active Load vs. Static Load

 The load on the left responds to the input signal and enhances the single-ended output, whereas the load on the right does not.

CH 10 Differential Amplifiers 83 MOS Differential Pair with Active Load

 Similar to its bipolar counterpart, MOS differential pair can also use active load to enhance its single-ended output.

CH 10 Differential Amplifiers 84 Asymmetric Differential Pair

 Because of the vastly different resistance magnitude at the

drains of M1 and M2, the voltage swings at these two nodes are different and therefore node P cannot be viewed as a

virtual ground when Vin2=-Vin1.

CH 10 Differential Amplifiers 85 Quantitative Analysis - Approach 1

1 iX  i Y & v A   i X g mP r OP 

vout v out 1 iY   g mP v A   g mP i X g mP r OP  i X rOP r OP

vout iX  r1 g g1 r  OP mP mP OP  

M4 M 3 1 rOP v A rOP vout g mP g v  mP A  A i i  X Y   rON N N rON

M1 M 2 CH 10 Differential Amplifiers 86 Quantitative Analysis - Approach 1 – cont’d

vA  i X  g mN v1 r ON  i Y  g mN v 2  r ON  v out  0

 vA 2 i X r ON  g mN r ON v in1  v in 2   v out  0

v1 v 2  vin 1  v in 2 & i X   i Y

Substituting for vAX and i ,

vout1 v out  gmP r OP  2 r ON r1 g g1 r  r  1  g g  1 r  OP mP mP OP  OP  mP mP OP 

vout  g mN r ON v in1  v in 2  r1 g g1 r  vout OP mP mP OP     gmN r ON vin1 v in 2 2 r ON  2 r OP

 gmN r ON r OP 

CH 10 Differential Amplifiers 87 Quantitative Analysis - Approach 2

vX i iX X

v1 v2

Textbook Error!

vThev  g mN r oN() v in1  v in 2 + - RThev 2 r oN

Textbook vv1 2 &  igvrX  m 1 1 O 1  igvr X  m 2 2 O 2  v X Error!

CH 10 Differential Amplifiers 88 Quantitative Analysis - Approach 2 – cont’d

1 r g O3 vm3  v  v  A1 out Thev rO3  R Thev gm3 v v v g v out  out Thev  0 m4 A 1 rO4 rO3  R Thev + - gm3 1  r gO3 1  v gm3   v  v  out  0 m4 1 1  out Thev    rO4 rO3 R Thev r O 3  R Thev  gm3 g m 3 

2vout 1 vout  v Thev  0 ( r O3  R Thev and g m 3  g m 4 ) RThev r O4 g m 3

1 1  gmN r ON v in1 v in 2  vout     rON r OP  r ON

vout   gmN r ON r OP  vin1 v in 2 CH 10 Differential Amplifiers 89 Example 10.29

 Prove that the voltage swing at node A is much less than that at the output.

vout 1  vA   g m4 v A  r O 3  rO4  g m 3    A vout 1    gm4 v A  rO4  g m 3 I vout vAA    v rO4 g m 3 vout I    gm4vA vout rO4 vA   2rO4 g m 3

CH 10 Differential Amplifiers 90