I. Common Base / Common Gate Amplifiers

I. Common Base / Common Gate Ampliﬁers - Current Buffer A. Introduction ¥ A current buffer takes the input current which may have a relatively small Norton resistance and replicates it at the output port, which has a high output resistance ¥ Input signal is applied to the emitter, output is taken from the collector ¥ Current gain is about unity ¥ Input resistance is low ¥ Output resistance is high.

V+ V+

i SUP ISUP

iOUT IOUT

R is S IBIAS IBIAS

V− V− (a) (b)

B. Biasing = /α ≈ ¥ IBIAS ISUP ISUP

EECS 6.012 Spring 1998 Lecture 19

II. Small Signal Two Port Parameters

A. Common Base Current Gain Ai ¥ Small-signal circuit; apply test current and measure the short circuit output current

ib iout

+ = β v r gmv oib r − o

ve roc

¥ Analysis -- see Chapter 8, pp. 507-509. ¥ Result: Ðβ ------o ≅ Ai = β Ð 1 1 + o

¥ Intuition: iout = ic = (- ie- ib ) = -it - ib and ib is small

EECS 6.012 Spring 1998 Lecture 19

B. Common Base Input Resistance Ri

¥ Apply test current, with load resistor RL present at the output

+ v r gmv r − o

roc RL +

vt i − t

¥ See pages 509-510 and note that the transconductance generator dominates which yields

1 Ri = ------gm

µ ¥ A typical transconductance is around 4 mS, with IC = 100 A ¥ Typical input resistance is 250 Ω -- very small, as desired for a current ampliﬁer

¥ Ri can be designed arbitrarily small, at the price of current (power dissipation)

EECS 6.012 Spring 1998 Lecture 19

C. Common-Base Output Resistance Ro ¥ Apply test current with source resistance of input current source in place

¥ Note roc as is in parallel with rest of circuit

g v m ro

+ vt it r − oc − v r RS +

¥ Analysis is on pp. 510-511 of Chapter 8, with the ﬁnal result boiling down to:

R ≈r ||r 1 +g r ||R out oc o mπ s

¥ If the RS is much greater than rπ, then the output resistance is approximately:

[]β Rout =roc oro

¥ Rout is limited to the small-signal resistance of the current source

EECS 6.012 Spring 1998 Lecture 19

D. Common-Base Two-Port Model ¥ The output resistance depends on the source resistance -- which means that the CB current buffer is not unilateral ¥ The two-port formal model is not strictly valid ¥ Error in using the model is small • Conceptual simpliﬁcation for design is huge

iin iout

1 −   iin roc ro[1 + gm(r RS)] gm

¥ Input resistance << CE Ampliﬁer ¥ Output resistance >> CE Ampliﬁer

EECS 6.012 Spring 1998 Lecture 19

III. Common-Gate Ampliﬁer A. Circuit Conﬁguration

+ V + V

iSUP ISUP I iOUT OUT

V − V −

i RS I s BIAS IBIAS

− V − V (a) (b)

¥ It is sometimes possible to tie the backgate to the source which shorts the backgate transconductance generator in small signal model • It is obvious that the current gain for this ampliﬁer must be unity, since the gate current for a MOSFET is zero ¥ The circuit analysis leading to the two port model is very similar to the CB ampliﬁer -- see pp. 513 - 518 of the text.

EECS 6.012 Spring 1998 Lecture 19

B. Common-Gate Two-Port Model ¥ The resulting two port model is shown below:

iin iout

1 −  iin roc (ro + gmroRS) gm + gmb

¥ The input resistance is the same as for the CB for the case where source and backgate are shorted. ¥ When this isn’t the case, the backgate generator is added in (which helps!):

1 1 Ri =or------Ri= ------gm gm+ gmb

¥ Ri can be designed to be arbitrarily small, at the price of area, by increasing (W/L) or current

¥ The output resistance is similar to the CB result with rπ --> infinity

R = r r + g r R o oc o m o S

EECS 6.012 Spring 1998 Lecture 19 IV. Common Collector/Drain Ampliﬁer - Voltage Buffer A. Introduction ¥ A voltage buffer takes the input voltage which may have a relatively large Thevenin resistance and replicates the voltage at the output port, which has a low output reisistance ¥ Input signal is applied to the base/gate, output is taken from the emitter/source ¥ Voltage gain is about unity ¥ Input resistance is high ¥ Output resistance is low V + V +

+ vs + − + + VBIAS − + VOUT V vOUT BIAS RL I − − iSUP SUP −

V − V − B. Biasing = ¥ Set VOUT to “halfway” between power rails-->VBIAS -VBE VOUT I kT SUP V = ------ln ------BE q I S

≈ ¥ Output voltage maximum VCC /2 -VCE(sat) VCC /2 - 0.2 V

¥ Output voltage minumum set by voltage requirement across ISUP

EECS 6.012 Spring 1998 Lecture 19 V. Small-Signal Two Port Parameters A. Common Colletor small-signal model and procedure for ﬁnding Av

+ g v v r m ro + v − t − + r oc vout −

¥ Circuit analysis: current through roc || ro is vπ / rπ + gmvπ --> v Ð v v t out ()out ------+g m v t Ð v out = ------rπ roc ro

β ¥ Multiplying by rπ and recognizing that gm rπ = ο, v β ()()β()out v t Ð v out +1o vt Ð vout ==+ovtÐ vout ------r π roc ro

¥ Solving for the open-circuit voltage gain:

1≈ Av= ------1 rπ 1+ ------()β - roc ro o + 1

EECS 6.012 Spring 1998 Lecture 19 B. Common-Collector Input Resistance Ri

¥ Procedure: apply pure test source, leave load resistor RL

β i + r o b

it vt −

 ro roc RL

β ¥ Note that current through roc || ro ||RL is it + o it -->

R = r + ()β + 1 rr R in π o oc o L

C. Common Collector Output Resistance ¥ Apply pure test current source at the output, leaving source resistance attached

v r g m v −

R S

it  ro roc + v t −

1 R R ≈ ------+ ------S out β gm o

EECS 6.012 Spring 1998 Lecture 19 D. Common Collector Two-Port Model ¥ Good voltage buffer ¥ Non unilateral network

/ + /β 1 gm RS o

+ + + v r + β (r r R ) v v in o o oc S − in out − −

E. Common Drain Ampliﬁer

V+ V+

+ v s − + + + VBIAS V + − OUT V vOUT RL I − BIAS − iSUP SUP

−

V − V−

¥ Analysis: much the same as for CC ampliﬁer

¥ If VSB isn’t zero, then the voltage gain is degraded from about 1 to 0.8-0.9

EECS 6.012 Spring 1998 Lecture 19 F. Common Drain Ampliﬁer Two-Port Model

1 + (gm gmb) + +

+ gm vin + v vout − (gm gmb) in − −

≈ ≈ ¥ If VSB = 0, then the voltage gain is Av 1 and Ro 1 / gm ¥ The CD ampliﬁer is a reasonable voltage buffer

¥ Improve output resistance by increasing gm ¥ Input loading is a non-issue, since the gate is open-circuited for MOSFETs.

EECS 6.012 Spring 1998 Lecture 19 VI. Summary A. Single-Stage Building Blocks

Table 1: Simpliﬁed Two-Port Parameters

Ampliﬁer Type Controlled Source Input Resistance Ri Output Resistance Ro

Common Gm = gm rπ ro || roc Emitter

Common Gm = gm inﬁnity ro || roc Source

Common Ai = -1 1 / gm roc ||ro [1+gm(rπ||RS) ] Base

1 / gm if vsb = 0, roc || (ro + gmroRS ), if vsb=0 Common Ai = -1 -otherwise- Gate 1 / (gm + gmb) -otherwise- roc ||[ro+(gm+gmb)roRS]

β β Common Av = 1 rπ + ο (ro || roc|| RL) (1 / gm ) + RS / ο Collector

Common Av = 1 if vsb = 0, 1 / gm if vsb = 0, Drain -otherwise- inﬁnity -otherwise- gm / (gm + gmb) 1 / (gm + gmb)

EECS 6.012 Spring 1998 Lecture 19 B. Ultra Simpliﬁed Two-Port Parameters

¥ gmb = 0, common base used as a current buffer --> RS >> rπ Table 2: Ultra Simpliﬁed Two-Port Parameters

Ampliﬁer Type Controlled Source Input Resistance Ri Output Resistance Ro

Common Gm = gm rπ ro || roc Emitter

Common Gm = gm inﬁnity ro || roc Source β Common Ai = -1 1 / gm roc || ( οro) Base

Common Ai = -1 1 / gm roc ||(gm RS ro) Gate β β Common Av = 1 rπ + ο (ro || roc|| RL) (1 / gm ) + RS / ο Collector

Common Av = 1 inﬁnity 1 / gm Drain

¥ This table is adequate for ﬁrst-cut hand design

EECS 6.012 Spring 1998 Lecture 19