Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS
Outline • NMOS inverter with resistor pull-up –The inverter • NMOS inverter with current-source pull-up • Complementary MOS (CMOS) inverter • Static analysis of CMOS inverter
Reading Assignment: Howe and Sodini; Chapter 5, Section 5.4
6.012 Spring 2007 Lecture 12 1 1. NMOS inverter with resistor pull-up: Dynamics
•CL pull-down limited by current through transistor – [shall study this issue in detail with CMOS]
•CL pull-up limited by resistor (tPLH ≈ RCL) • Pull-up slowest
VDD VDD
R R VOUT: VOUT: HI LO LO HI V : VIN: IN C LO HI CL HI LO L
pull-down pull-up
6.012 Spring 2007 Lecture 12 2 1. NMOS inverter with resistor pull-up: Inverter design issues
Noise margins ↑⇒|Av| ↑⇒
•R ↑⇒|RCL| ↑⇒ slow switching
•gm ↑⇒|W| ↑⇒ big transistor – (slow switching at input)
Trade-off between speed and noise margin.
During pull-up we need: • High current for fast switching • But also high incremental resistance for high noise margin.
⇒ use current source as pull-up
6.012 Spring 2007 Lecture 12 3 2. NMOS inverter with current-source pull-up
I—V characteristics of current source:
iSUP
+
1 ISUP r i oc vSUP SUP
_
vSUP
Equivalent circuit models :
iSUP +
ISUP r r vSUP oc oc
_
large-signal model small-signal model
• High current throughout voltage range vSUP > 0
•iSUP = 0 for vSUP ≤ 0
•iSUP = ISUP + vSUP/ roc for vSUP > 0
• High small-signal resistance roc.
6.012 Spring 2007 Lecture 12 4 NMOS inverter with current-source pull-up Static Characteristics VDD
iSUP
VOUT
VIN CL Inverter characteristics :
iD
= V 4 3 VIN VGS I + DD SUP roc 2
1 = vOUT vDS VDD (a)
VOUT 1 2
3 4
VIN (b)
High roc ⇒ high noise margins
6.012 Spring 2007 Lecture 12 5 PMOS as current-source pull-up
I—V characteristics of PMOS:
+ S +
VSG _ VSD G B − _ + IDp 5 V + D − V + G − V − D
− ID(VSG,VSD)
(a)
= VSG 3.5 V 300
V = V + V = V − 1 V 250 (triode SD SG Tp SG region) V = 3 V 200 SG − IDp (µA) (saturation region) 150 = VSG 25 100 = 0, 0.5, VSG 1 V (cutoff region) V = 2 V 50 SG = VSG 1.5 V
12345 VSD (V) (b)
Note: enhancement-mode PMOS has VTp <0.
In saturation:
2 −IDp ∝(VSG + VTp )
6.012 Spring 2007 Lecture 12 6 PMOS as current-source pull-up: Circuit and load-line diagram of inverter with PMOS current source pull-up:
PMOS load line for V =V -V VDD SG DD B -IDp=IDn
VDD
VB
VOUT VIN VIN CL
0 0 VDD VOUT
Inverter characteristics: NMOS cutoff PMOS triode VOUT NMOS saturation PMOS triode VDD
NMOS saturation PMOS saturation
NMOS triode PMOS saturation
0 0 VTn VDD VIN
6.012 Spring 2007 Lecture 12 7 PMOS as current-source pull-up: NMOS inverter with current-source pull-up allows high noise margin with fast switching • High Incremental resistance • Constant charging current of load capacitance
But…
When VIN = VDD, there is a direct current path between supply and ground ⇒ power is consumed even if the inverter is idle.
VDD PMOS load line for VSG=VDD-VB -IDp=IDn
VDD VB
VOUT:LO VIN VIN:HI CL
0 0 VDD VOUT
Ideally, we would like to have a current source that is itself switchable, i.e it shuts off when input is high ⇒ CMOS!
6.012 Spring 2007 Lecture 12 8 3. Complementary MOS (CMOS) Inverter Circuit schematic:
VDD
VIN VOUT
CL
Basic Operation:
•VIN = 0 ⇒ VOUT = VDD
VGSn = 0 < VTn ⇒ NMOS OFF VSGp = VDD > - VTp ⇒ PMOS ON
•VIN = VDD ⇒ VOUT = 0
VGSn = VDD > VTn ⇒ NMOS ON VSGp = 0 < - VTp ⇒ PMOS OFF No power consumption while idle in any logic state!
6.012 Spring 2007 Lecture 12 9 VOUT V 1 DD 2 CMOS Inverter (Contd.): 3 Output characteristics of both transistors: 4 5 VDD VIN
= − − = IDn IDp IDp IDn
VIN
3 3 4 2 4 2 5 1 5 1 VDD VOUT VDD VOUT n-channel p-channel (a) (b) Note:
VIN = VGSn = VDD -VSGp ⇒ VSGp=VDD -VIN
VOUT = VDSn = VDD -VSDp ⇒ VSDp=VDD -VOUT
IDn = -IDp
Combine into single diagram of ID vs. VOUT with VIN as parameter
6.012 Spring 2007 Lecture 12 10 CMOS Inverter (Contd.): ID
VDD-VIN VIN
0 0 VOUT
• No current while idle in any logic state
Inverter Characteristics:
NMOS cutoff PMOS triode
VOUT NMOS saturation PMOS triode VDD
NMOS saturation PMOS saturation
NMOS triode PMOS saturation
NMOS triode PMOS cutoff 0 0 V V +V V Tn DD Tp VDD IN
• “rail-to-rail” logic: logic levels are 0 and VDD • High |Av| around logic threshold ⇒ good noise margins
6.012 Spring 2007 Lecture 12 11 2. CMOS inverter: noise margins
VOUT NML
VDD
Av(VM) VM
0 0 V V V V IL M IH VDD IN NMH
• Calculate VM
• Calculate Av(VM)
• Calculate NML and NMH
Calculate VM (VM = VIN = VOUT)
At VM both transistors are saturated:
Wn 2 I Dn = µ nCox()VM − VTn 2Ln
Wp 2 −IDp = µ pCox()VDD − VM + VTp 2Lp
6.012 Spring 2007 Lecture 12 12 CMOS inverter: noise margins (contd.)
Define:
Wn Wp kn = µnCox; kp = µpCox Ln Lp
Since :
I Dn = −IDp
Then:
1 2 1 2 kn()VM − VTn = kp (VDD − VM + VTp ) 2 2
Solve for VM:
k V + p V + V Tn k ()DD Tp V = n M k 1+ p kn
Usually, VTn and VTp fixed and VTn = - VTp ⇒ VM engineered through kp/kn ratio.
6.012 Spring 2007 Lecture 12 13 CMOS inverter: noise margins (contd..)
• Symmetric case: kn = kp V V = DD M 2 This implies:
Wp Wp µ pCox µp k L L W W p =1 = p ≈ p ⇒ p ≈ 2 n k Wn Wn L L n µ nCox 2µ p p n Ln Ln
Since usually Lp ≈ Ln = Lmin ⇒ Wp ≈ 2Wn
Wn Wp • Asymmetric case: kn >> kp, or >> Ln Lp
VM ≈ VTn
NMOS turns on as soon as VIN goes above VTn.
Wn Wp • Asymmetric case: kn << kp, or << Ln Lp
VM ≈ VDD + VTp
PMOS turns on as soon as VIN goes below VDD + VTp.
6.012 Spring 2007 Lecture 12 14 CMOS inverter: noise margins (contd…)
Calculate Av(VM)
• Small signal model:
S2 + v =-v sg2 in gmpvsg2 rop - G2 D2
G1 D1 + + +
vin vgs1 gmnvgs1 ron vout - - - S1
G1=G2 D1=D2
+ +
vin gmnvin gmpvin ron//rop vout - - S1=S2
Av =−()gmn + gmp (ron // rop )
This can be rather large.
6.012 Spring 2007 Lecture 12 15 CMOS inverter: calculate noise margins (contd.) VOUT NML
VDD
Av(VM) VM
0 0 V V V V IL M IH VDD IN NMH
• Noise-margin low, NML:
VDD − VM VIL = VM − Av
VDD − VM NML = VIL − VOL = VIL = VM − A v
• Noise-margin high, NMH: ⎛ 1 ⎞ ⎜ VIH = VM 1 + ⎟ ⎝ Av ⎠
⎛ 1 ⎞ ⎜ NMH = VOH − VIH = VDD − VM 1+ ⎟ ⎝ Av ⎠
6.012 Spring 2007 Lecture 12 16 What did we learn today?
Summary of Key Concepts
• In NMOS inverter with resistor pull-up, there is a trade-off between noise margin and speed • Trade-off resolved using current source pull-up – Use PMOS as current source. • In NMOS inverter with current-source pull-up: if
VIN = High, there is power consumption even if inverter is idling. • Complementary MOS: NMOS and PMOS switch- on alternatively. – No current path between power supply and ground – No power consumption while idling • Calculation of CMOS
–VM – Noise Margin
6.012 Spring 2007 Lecture 12 17