Design of Scaled CMOS Circuits in the Nano -meter Regime: Leakage Tolerance and Computing with Leakage Kaushik Roy Professor of Electrical & Computer Engineering Purdue University VLSI Applications General purpose computing: internet server, database server, real-time Ultralow power jobs etc. applications: medical, space, ER specific sensor W network etc. PO Portable applications: mobile computing, wireless, multimedia etc. PERFORMANCE • Different applications have different power-performance demands • Scaling affects all applications in different ways 1 Cha llenges a hea d … in Si nanometer regime Challenge No. 1: Device Scaling Bulk MOS UTB-SOI MOS DG-SOI MOS Retograde Well, Halo Fully-depleted ultra-thin body Planar double-gate structure Strained Channel Ground-plane Independent gate control FinFET Tri-gate Vertical MOS Quasi-planar DG structure Quasi-planar with 3 gates Conduction normal to plane Most promising device Better area efficiency Difficult to fabricate 2 Scaling & Ion/Ioff 1 um 100 nm 10 nm Silicon micro Silicon nano Non-Silicon electronics electronics technology • Increasing I leakage V • Increasing process variations • Carbon Nanotubes • Short Channel • Molecular transistors Effects • Molecular RTDs I ION 3 I ON =106 =10 ON =104 I IOFF OFF IOFF 2. Power & Power Density 100 P6 Pentium ® proc ) 2 10 tts) cm a 486 286 8086 386 8085 1 8080 Power (W 8008 4004 Power Density (W/ 0.1 1971 1974 1978 1985 1992 2000 Year Year Increased Average Power • Battery Life Increased Power Density • Cooling Cost • Reliability Source: Intel 3 Challenge 3: Process Variations Device 1 Device 2 Leff1<Leff2 A. Asenov, TED03 Dopant Line-Edge atoms Roughness M. Hane, et. al., SISPAD 2003 Variation in channel length Random Dopant Fluctuations (RDF) 1.4 NMOS z Intrinsic parameter variations: PMOS ON 1.2 – Channel length and width d I e – Variations due to line edge 1.0 2X roughness 0.8 – Threshold voltage (Vt) variations Normaliz 0.6 100X 150nm, 110°C due to random dopant fluctuation 0.4 0.01 0.1 1 10 100 Normalized IOFF Device parameters are no longer deterministic Challenge 4: Reliability Temporal degradation of performance -- NBTI Tech. generation ailure probability F Time Defects Life time degradation 4 Power Consumption • Leakage Power – Subthreshold, Gate, Junction, GIDL, Punchthrough, …. • Dynamic Power – Due to charging/discharging of capacitive load – Short-circuit power due to direct path currents when there is a temporary connection between power and ground Leakage Vs. Dynamic Power (Projection) 1200 15 mm Die 1000 Leakage ~54% Dynamic 800 600 ~32% Power (W) 400 7% 1% 3% ~16% ~ ~ 200 ~ 0 Source: Intel 0.25u 0.18u 0.13u 90nm 65nm 45nm Leakage power limits Vth scaling 5 Leakage Power Scaling and Other Leakage Components • Leakage Components Subthreshold Gate Leakage Leakage – Subthreshold Leakage Gate Source Drain – Gate Leakage n+ n+ – Reverse-biased Junction Band- Reverse Biased To-Band-Tunneling (BTBT) Junction BTBT Leakage. –Others Bulk Long Channel Short Channel Very Short Nano-scaled ( ( L > 1 μm) ( L > 180 nm, Channel ( L < 90 nm, Tox > 30A0) L > 90 nm, Tox Tox < 20A0) Negligible Subthreshold > 20A0) Subthrehold leakage leakage Subthrehold + + Gate + Jn. Gate Leakage BTBT leakage 6 Leakage Power Consumption V DD VDD Vout = VDD Diode leakage Vq / kT IO = is (e −1) Sub-threshold leakage (Vgs −Vt )q / nkT Vdsq / kT I D = K ⋅e (1− e ) Pstatic = Ileakage. VDD Diode Leakage • Leakage current through the reverse biased diode junctions • For typical devices it is between 0 .1nA - 0. 5nA at room temperature • For a die with 1 million devices operated at 5 V, this results in 0.5mW power consumption → not much • Junction leakage current is caused by thermally generatedid carriers -> thfherefore is a strong funct ion of temperature • More important is sub-threshold leakage, gate leakage, and Junction BTBT leakage 7 Leakage Components •Vt Scaling Subthreshold •Short Channel Leakage Ç Effects Gate Scale Tox Leakage Ç •Scale Wd-doping Ç Junction •Channel Engg. – patches of higher BTBT doping in the channel Leakage Ç Doping -1 has more effective “halo” doping to reduce SCE Jn. Band-To-Band-Tunneling Current (IBTBT) Electron tunneling from EC q(V +V ) VB of p-side to the CB of bi app E n-side. V EC BTBT Current density p-side depends on Junction field EV (ξ), junction voltage(Vapp) , n-side band-gap (Eg). High BTBT in scaled 3/2 ξVEapp⎛⎞ g devices JA=− expB⎜⎟ bb− 1/2 ⎜⎟ High junction doping: Eg ⎝⎠ξ ' *3 * “Halo” profiles 242mq m 'Small depletion width AB==32 , and 43π hhq 'Large electric field 8 Gate Leakage (Igate) Φ Direct tunneling of electron ox, ECB=3.1 eV ECB through gate oxide. Gate current density EVB depends on oxide thickness, oxide field and HVB voltage drop across oxide n+ poly p substrate ⎛⎞−BV11−− /φ 3/2 2 goxox( ( ) ) JAVTexp= ⎜⎟ DT g() ox ox ⎜⎟ ⎜⎟VTox/ ox ⎝⎠ High Gate leakage in scaled devices: Low oxide thickness and high oxide field Components of Gate Leakage Gate leakage components Gate to source/drain overlap region • I I (Igso, Igdo) gso gdo ¾Controlled by Vgd and Vgs I gc • Gate to channel (Igc)= to source (Igcs) + to drain (Igcd) ¾Controlled by Vox≈Vgs- Igcs I gcd VFB -Φs –Vpoly. I gb • Gate to body (Igb) ¾Controlled by Vgb Transistor off (Vg=‘0’) – Igdo and Igso dominates. Transistor on (Vg=‘1’) – Igc (Igcs & Igcd) dominates. Igb small compared to others. 9 Subthreshold leakage (Isub) Exponentially dependence on Vgs and Vth. wqNε ⎛⎞⎛⎞ VV− ⎛⎞−V Ivexpexp=−effμ si cheff2 gs th 1 ds sub T ⎜⎟⎜⎟⎜⎟ Lnvveff2Φ s⎝⎠⎝⎠ T⎝⎠ T Vth modulation 9 Short channel Effect – Vth reduction due to ¾ Increase in Vds (DIBL), ¾ Reduction in Channel Length (Vth roll off). 9 Body effect – negative Vbs increases Vth. 9 Quantum confinement effect – increases Vth ⎛⎞W VV=+Φ−ΔΦ+Φ−−γλ V1 dm ++ V V th FB() s00 s s bs⎜⎟ nce QM ⎝⎠Leff ΔΦ =2(VVeeandlTW −φεεη ) + ×⎡⎤−−Ll/2cc + 2 Ll / = sbiSds[]0 ⎣⎦ Csioxoxdm( ) Subthreshold Leakage Subthreshold leakage reduces with 9Negative Vbs, Reduction of Vds 9Application of Quantum Correction 10 Total Leakage “Sum of Current Source Model ” Voltage Controlled Current Sources describing each leakage comp. Total Transistor Leakage= IIIIoverall= BTBT++ sub gate Leakage Estimation Method Logic Gates Isub I gate Isub Itotal ‘00’ ‘01’ ‘10’ ‘11’ Leakage Table Curr en t M odeling Estimated Total INPUT Circuit Leakage OUTPUT Logic Circuits 11 Low-Vdd Low-Vt Design • Stacked CMOS • Dual-threshold CMOS • Dynamic-threshold CMOS Leakage Reduction (Logic & Memory) Circuit Techniques DiDesign Time Run Time Dual V th Standby Leakage Active Leakage Reduction Reduction Natural Stacking DVTS Sleep Transistor FBB/RBB 12 Self-Reverse Bias (Source-Biasing, Supply-Gating, Stacking) log(I ) V DS • Primary effect: D –VGS < 0 VG= 0V VS = 0 – move down VS subthreshold V > 0 slope S VGS • Secondary effects: – Drain Induced Barrier Lowering VDS ↓⇒ VT ↑ – Body effect VS ↑⇒ VT ↑ Leakage Control: Stacking Vdd Vdd M1 ‘0’ ‘0’ VM>0 ‘0’ M2 Vgs=0,Vbs=0,Vds=Vdd For M1: 9NtiVNegative Vgs, Vgs =-VM< 0,Vbs =-VM<0, 9Negative Vbs- More Vds = Vdd-V <Vdd Body effect, M For M2: 9Reduced Vds-Less DIBL Vgs =0,Vbs =0, 2-T stack has lower Vds = V < Vdd subthreshold leakage M 13 Input Vector Control - Subthreshold Vdd Vdd M1 M1 ‘0’ ‘1’ VM>0 Vdd-Vth_M1 ‘0’ ‘0’ M2 M2 Minimum Vgs is For M1: Minimum Vgs is For M2: VM10Vgs_M1 < 0, VM20Vgs_M2 = 0, Vds_M1= Vdd - VM Vds_M2=Vdd-Vth_M1 ‘00’ gives minimum subthreshold leakage. Turn ‘off’ maximum number of transistors in a stack to reduce subthreshold leakage Leakage vs. Transistors Off Leakage [nA] 10 8 6 4 2 0 1234 Number of transistors off in stack 14 Input Vector Control – Gate Leakage 9Vg=‘0’ – EDT dominates Vdd ¾Ig = Igdo + Igso Igdo_M1(Vdd) 9Vg=‘1’ – Gate to Channel M1 tunneling is significant ‘0’ ¾Ig = Igdo + Igso + Igc Igso_M1(VM) VM>0 With ‘00’ – Igdo_M2(VM) Igdo_M1(Vdd) >> ‘0’ Igso_M1(VM) + Igdo_M2(VM) M2 Igdo of M1 dominates the total gate current ⎛⎞−−−BV11 /φ 3/2 2 ( ()dd ox ) IWLAVTexp= ⎜⎟ gstack SDE() dd ox ⎜⎟ ⎜⎟VTdd/ ox ⎝⎠ Input Vector Control – Gate Leakage With ‘01’ – Vdd Igdo_M1(Vdd) is high. Igdo_M1(Vdd) Igdo_M2(Vdd) is high. M1 Igso_M2(Vdd) is high. ‘0’ Gate to channel leakage of M2 is controlled by : 0 Vox_M2 = Vdd - VFB -Φs – Igdo_M2(VM) Vpoly. ‘1’ Igc_M2(Vdd) Igso_M2(V ) M2 Total gate current is high. M 15 Input Vector Control – Gate Leakage With ‘10’ the major gate Vdd currents are: 9Igso_M1(Vth) M1 Igc_ M1(Vth) 9Ig do_ M2(Vdd - Vth_ M1) ‘1’ 9Igc_M1(Vgs = Vth) Igso_M1(Vth_M1) Vdd-Vth_M1 Igdo_M2(V ) =V Igdo_M2 dominates the INT INT total current. ‘0’ M2 3/2 2 ⎛⎞ −−−−BVV11(dd th_1 M )/φ ox ⎛⎞()VVdd− th_1 M ⎜⎟( ()) IWLAgstack= SDE ⎜⎟ exp TVVT⎜⎟()/− ⎝⎠ox⎜⎟ dd th_1 M ox ⎝⎠ Input Vector Control – Gate Leakage Vdd Vdd Igdo_M1(Vdd) M1 M1 Igc_M1(Vth) ‘0’ ‘1’ Igso_M1(VM) Igso_M1(Vth_M1) Vdd-Vth_M1 VM>0 Igdo_M2(VM) Igdo_M2(VINT) =VINT ‘0’ ‘0’ M2 M2 I(Vdd)I(VddIg(Vdd) > Ig(Vdd-Vth_ M1) Rate of change of gate current increases with an increase in Vox (exponential) Gate current with ‘10’ is lower than ‘00’ 16 Gate Leakage Gate leakage increases with 9 Increase in Vox 9 Reduction in Tox. Rate of change of current is higher at higher Vox Input Vector Control – BTBT Vdd Vdd Vdd IBTBT_d_M1 IBTBT_d_M1 M1 ‘1’ ‘0’ ‘0’ IBTBT_s_M1 M1 Vdd-Vth_M1 =V M1 INT V >0 M 0 IBTBT_d_M2 ‘0’ ‘0’ ‘1’ M2 M2 M2 ’00’ an d ’01’ –didrain-subtbstra te BTBTfM1dBTBT of M1 dom ina tes. ’10’ – additional BTBT components drain-substrate of M2 and source-substrate of M1. ’10’ gives maximum BTBT. However, BTBT is not very sensitive to stacking.