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Dynamic Logic Gates Chapter 14 Dynamic Logic Gates Dynamic or clocked logic gates are used to decrease complexity, increase speed, and lower power dissipation. The basic idea behind dynamic logic is to use the capacitive input of the MOSFET to store a charge and thus remember a logic level for use later. Before we start looking into the design of dynamic logic gates, let's discuss leakage current and the design of clock circuits. 14.1 Fundamentals of Dynamic Logic Consider the NMOS pass gate (PG) driving an inverter, as shown in Fig. 14.1. If we clock the gate of the PG high, the logic level on the input, point A, will be passed to the input of the inverter, point B. If this logic level is a "0," the input of the inverter will be forced to ground, while a logic "1" will force the input of the inverter to VDD - VTHN. When the clock signal goes low, the PG shuts off and the input to the inverter "remembers" the logic level. In other words, when the PG turns on, the input capacitance of the inverter is either charged to VDD - VTHN or discharged to ground through the PG. As long as this charge is present on the parasitic input capacitance of the inverter, the logic value is remembered. What we are concerned with at this point are the leakage mechanisms which can leak the stored charge off the node. A node, such as the one labeled B in Fig. 14.1, is called a dynamic node or a storage node. Note that this node is a high-impedance node and is easily susceptible to noise (see Ex. 3.5). Storage node A \B Input —• 1 | -J-— 5N Input capacitance of the inverter Figure 14.1 Example of a dynamic circuit and associated storage capacitance. 398 CMOS Circuit Design, Layout, and Simulation 14.1.1 Charge Leakage One of the important concerns with designing dynamic circuits is the MOSFET's off current, see Sec. 6.4.2. In Fig. 14.2 we show the simulated drain current of a 10/1 MOSFET in the 50 nm process plotted against gate-source voltage. The off current, with Vcs = 0, is taken from the plot as log/ß = -8.45 ->ID = 3.55 nA=I0ff- W- scale (14.1) noting that the worst case off current occurs when the minimum channel length is used (L = 1). The off current can be estimated as I0ff=l-l nAlyun (14.2) The off current is made up of leakage through the source/drain implant to substrate (the formed diode and the associated saturation currents), leakage around the edges of the poly at the edge of the field oxide, and by the source-to-drain leakage currents. log/0 + )VDD /H«' I 1 ! ! ! ! yes Figure 14.2 Drain current of an NMOS device plotted from weak to strong inversion. See Fig. 6.16. PMOS netlist is found at cmosedu.com. The rate at which the storage node seen in Fig. 14.1 discharges is given by dV I»ff- W-scale (14.3) dt ^■node The node capacitance, Cnode , is the sum of the input capacitance of the inverter, the capacitance to ground of the metal or poly line connecting the inverter to the pass transistor, and the capacitance of the drain implant to substrate (the depletion capacitance). For practical applications, we assume that Cnode « Cin of the inverter (14.4) Example 14.1 Estimate the discharge rate of the 50 fF capacitor shown Fig. 14.3. Using Eqs. (14.1) and (14.3), we can write the capacitor's discharge rate as dV _3.55nA ■ l\mVI\xs dt 50fF Chapter 14 Dynamic Logic Gates 399 10/1 * leakage Initally charge to 1 V T £ 50 fF Figure 14.3 Circuit used in Ex. 14.1. For the capacitor to discharge to ground (from an initial voltage of 1 V) takes, roughly, (1 F)/(71 mVI\is) = 14 \xs. Figure 14.4 shows the simulation results. Note how the time it takes the output voltage to discharge to ground is twice as long as what we calculated or roughly 30 us. This is due to the fact that as the voltage between the drain and source of the MOSFET decreases so does the off current. The reduction in the off current causes the capacitor to discharge slower. To keep the voltage across the capacitor from discharging too much we might try holding one side of the MOSFET switch at VDDI2. Consider the following. ■ Figure 14.4 Time it takes the capacitor to discharge due to the off current of the MOSFET in Fig. 14.3. Example 14.2 Repeat Ex. 14.1 with the input tied to VDD/2 instead of ground. The schematic and simulation results are seen in Fig. 14.5. The leakage current is minimized by lowering the VDS of the MOSFET. This is a common technique to u 60 ; 3 VDD/2 !0/l , 'leakage 2 ion o T x 50 fF 5 U Figure 14.5 Circuit used in Ex. 14.2. 400 CMOS Circuit Design, Layout, and Simulation reduce leakage currents in DRAM (see Fig. 16.7 where the bitlines are equilibrated to VDD/2). Note that when the voltage across the capacitor (the storage node) is zero and the PG is off the leakage through the MOSFET causes the storage node to charge upwards (see Problem 14.2). ■ Example 14.3 Figure 14.6 shows a dynamic level-sensitive latch. Estimate the maximum time PG can be off before data is lost on the charge storage node. Compare the estimate to SPICE. Use the 50 nm process with 20/1 PMOS devices and 10/1 NMOS devices. Storage node D D»TH> clock Figure 14.6 A dynamic level-sensitive latch. The input capacitance of the inverter, using Table 10.2, is estimated as Cin = | ■ (1.25 + 0.625)/F= 2.8/F Using Eq. (14.3), we can estimate the rate the storage node decays as dV 3.55 nA 1.27 Vl\xs dt 2.8/F If we want, at most, 100 mV of droop in the storage node's voltage, then we would want to ensure that the PG is clocked, at the minimum, every 100 ns. Figure 14.7 shows the simulation results. Compared to our hand calculations, the discharge rate is considerably faster. This is due to our calculation of the input capacitance. The values used for Cm were the switching input capacitance (see Figs. 10.2, 10.7, and 10.8), not the static input capacitance (see Fig. 6.4). ■ Figure 14.7 How the voltage on the storage node varies in the dynamic latch circuit seen in Fig. 14.6. Chapter 14 Dynamic Logic Gates 401 14.1.2 Simulating Dynamic Circuits Because of the extremely small leakage currents involved, simulating dynamic circuits can be challenging. To begin, when SPICE simulates any circuit, it puts a resistor with a conductance value given by the parameter GMIN across every pn junction and MOSFET drain-to-source. The default value of GMIN is \0'2 mhos or a 1 TQ resistor. A charge storage node at a potential of 1 V has a leakage current, due to GMIN, of 1 pA. The value of GMIN can be set, and increased, using the .OPTIONS command, at the cost of a longer or more difficult convergence time, to a smaller value, say 10"15. Some SPICE simulators are also capable of adding a resistor at every node to ground called RSHUNT (to help with convergence). If RSHUNT is 109 and a node voltage is 1 V, then a current of 1 nA flows through the added RSHUNT resistor. In practice, we can use the default values of SPICE when simulating dynamic circuits. The SPICE leakage paths (using the default values of GMIN and RSHUNT) have little effect on the estimates for the discharge times of storage nodes when simulating dynamic circuits. For example, the leakage current, for VDD = 1 V, due to the default value of GMIN is given by Ueakage ~ 1 pA = VDD ■ GMIN (14.5) and dv 1 pA VDD GMN _ _ • (14 6) at O node ^ node If Cnode = 5 fF, then dVldt = 200 = 200 \xV/^is. It takes approximately 5 ms for the voltage on the charge storage node to drop to ground. In all practical simulations, the leakage through a modern nanometer MOSFET is much more significant than the leakage through GMIN. 14.1.3 Nonoverlapping Clock Generation Consider the string of PGs/inverters shown in Fig. 14.8. This circuit is called a dynamic shift register. When <j>, goes high, the first and third stages of the register are enabled. Data is passed from the input to point A0 and from point Al to A2. If <|>2 is low while (^ is high, the data cannot pass from A0 to Al and from A2 to A3. If <J>, goes low and <|)2 goes high, data is passed from A0 to Al and from A2 to A3. If both <j), and (j)2 are high at the same time, the input of the shift register and the output are connected together, which is not desirable in a shift register application. The purpose of the inverter between PGs is to restore logic levels, since the NMOS PG passes a high with a threshold voltage drop. Two inverters would be used to eliminate the logic inversion between stages. The clocks used in this dynamic circuit must be nonoverlapping, or logically <t>i d>2 =0 (14.7) There should be a period of dead time between transitions of the clock signals, labeled A in Fig.
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