Fabrication and Characterization of Bulk Finfets for Future Nano- Scale CMOS Technology

2nd US-Korea NanoForum, LA

Fabrication and Characterization of bulk FinFETs for Future Nano- Scale CMOS Technology

Jong-Ho Lee

[email protected] School of EECS and National Education Center for Semiconductor Technology Kyungpook National University, Daegu, 702-701 Korea

2nd US-Korea NanoForum, LA Jong-Ho Lee Contents

Introduction Simulation Study

Fabrication of Bulk FinFETs by Spacer Technology

by Selective Si3N4 Recess

Device and SRAM Cell Characteristics Summary

2nd US-Korea NanoForum, LA Jong-Ho Lee Introduction : Technology Roadmap Beyond Bulk LDD CMOS

TGTG G S/D S/D Double/Triple-Gate BGBG S/D S/D S/D Double-Gate CMOS Fin Double/Triple-Gate FET

Si G G

SOI/SiGe S/D SiGe S/D

Performance SOI PD/FD CMOS SiGe CMOS (high mobility)

Halo G Bulk Bulk LDD CMOS (Halo)

2004 2006 2008 2010 Time

2nd US-Korea NanoForum, LA Jong-Ho Lee Introduction

Driving Force of CMOS Scaling-down: Æ High Performance and High Integration Density

A Promising Device Structure Æ Double/Triple-Gate MOSFETs (or FinFETs)

Why Double/Triple-Gate Transistor? Æ Robustness against SCE G Æ Higher Current Drivability S D Æ Good Subthreshold Swing Si film G

2nd US-Korea NanoForum, LA Jong-Ho Lee Introduction : Types of Double-Gate Transistors

Z Current- Carrying Plane Y Z Y

X Plane D Top Gate Left Gate X current Current- Carrying S D direction Right Gate Bottom Gate S Silicon Wafer Silicon Wafer (a) Type I (b) Type II

S current direction Right Gate D Z Current- Left Y Carrying Gate Process technology of FinFET is Plane easy and compatible with X conventional fabrication process Silicon Wafer (c) Type III ∗ H. P. Wong et al., IBM, vol. 87, no. 4, p.537, 1999, Proceedings of the IEEE 2nd US-Korea NanoForum, LA Jong-Ho Lee Types of Double/Triple-Gate Transistors

Type Type I Type II Type III (Planar DG (Vertical DG (Triple-Gate Key (FinFETs) FETs) FETs) MOSFETs) Geometry

Gate Left/Right (or Top/Bottom Left/Right Left/Right/Top Position Cylinder)

Body Horizontal Vertical Vertical Vertical Shape Current Horizontal Carrying Side Surfaces Side Surfaces Side Surfaces Surfaces Plane Current Flow Horizontal Vertical Horizontal Horizontal Direction

2nd US-Korea NanoForum, LA Jong-Ho Lee Double-Gate Transistor (SOI FinFET)

FinFET Ã simple, self-aligned double-gates Ã good process compatibility Ä thickness control of fin body Ä RIE damage on the channel, high S/D resistance

∗ D. Hisamoto et al., UC Berkeley, p.1032, IEDM 1998

2nd US-Korea NanoForum, LA Jong-Ho Lee Body-Tied Double/Triple-Gate MOSFET Using Bulk Wafer (Bulk FinFET)

Low wafer cost S/D te Ga 0 Low defect density Less back-bias effect HFin S/D x j High heat transfer rate

o to substrate d WFin Ox y Good process compatibility Si id e T Su FOX bs tr ate World 1st Cost-Effective Double/Triple-Gate MOSFETs Schematic 3-D View

∗ J.-H. Lee., Korea/Japan/USA patent

2nd US-Korea NanoForum, LA Jong-Ho Lee Cross-Sectional Views (Body Structure) for 3- Dimensional Device Simulation

Gate Fin body Gate Fin body

SiO SiO2 2

Si sub Si sub

SOI FinFET Bulk FinFET

2nd US-Korea NanoForum, LA Jong-Ho Lee 3-D Simulation Results

0.5 180 100 L =25 nm G L =25 nm 150 95 G T =1.5 nm T =1.5 nm 0.4 OX OX

DIBL (mV/0.9V) DIBL V =0.9 V 120 90 DS Bulk 0.3 90 85

SOI (V) T Swing (mV/dec) V =0.05 V Bulk V DS SOI 60 80 N =1x1019 cm-3 0.2 a H =70 nm H =70 nm Fin 30 75 Fin x =66 nm 19 -3 j,S/D N =1x10 cm x =66 nm a j,S/D 0.1 0 Subthreshold 70 10 20 30 40 50 10 20 30 40 50 Fin Width (nm) Fin Width (nm)

VT and DIBL versus Fin Width Subthreshold Swing versus Fin Width

qNsub tb VTMSB=Φ +2φ + for fully depleted body 2C ox ∗ J.-H. Lee et al., KNU, p. 102, Si Nanoelectronics Workshop 2003

2nd US-Korea NanoForum, LA Jong-Ho Lee 3-D Simulation Results

475 substrate electrode L =30 nm 450 G @ temperature=300 K S/D e T =1.5 nm at 0 425 OX G SOI 400 V =0.9 V HFin DS

S/D Bo x j 375

d ∆T~130 °C

y W Fin 350 O xi Bulk S de T 325 i S FOX ubs (K) Device Temperature tra 300 t e Heat 0.0 0.2 0.4 0.6 0.8 1.0 Gate Voltage (V) 3-D Schematic View of Heat Device Temperature versus Gate Transfer from Body to Substrate Voltage

∗ J.-H. Lee et al., KNU, p. 102, Si Nanoelectronics Workshop 2003

2nd US-Korea NanoForum, LA Jong-Ho Lee Fabrication Steps by Using Spacer Technology

SiN 80 nm

SiO2 30 nm SiN 25 nm SiO2 30 nm

4 Stack Layer Growth and Deposition SiN Removal Using Phosphoric Acid

Poly-Si Spacer 30 nm Poly-Si Spacer

Si Photo Lithography, SiN Etching, Poly-Si Depo., and Dry Etching

2nd US-Korea NanoForum, LA Jong-Ho Lee Fabrication Steps

SiO2, SiN, and SiO2 Dry Etching Fin Dry Etching

Top Si Width 25 nm Bottom Si Width 100 nm Si Fin Height 230 nm Fin body

2nd US-Korea NanoForum, LA Jong-Ho Lee Fabrication Steps

SiO2

Wet Etch-back Thin Ox., Filling, and Densification Field Oxide Thickness 80 nm

SiO2

Chemical Mechanical Polishing (CMP)

2nd US-Korea NanoForum, LA Jong-Ho Lee / 27 First Body-Tied Triple-Gate MOFET (Bulk FinFET)

As+, 20 keV 3x1015 /cm2, 2 Fin

V = 0.1 V -7 DS Gate Poly-Si Etching 10

25 nm 10-8

40 nm 50 nm

-9 10 Vbs = 0 V

Poly-Si (A) Current Drain Vbs = -1 V 40 nm Vbs = -2 V 10-10 -0.5 0.0 0.5 1.0 1.5 Gate Voltage (V)

ID-VGS Characteristics of 40 nm bulk NFiNFET

∗ T. Park et al., SNU/KNU, Nanomes03 2003 ∗ T. Park et al., SNU/KNU, Physica E19, p.6, 2003

2nd US-Korea NanoForum, LA Jong-Ho Lee Modified Structure of Bulk FinFET

Thick SiN liner formation & CMP and SiN liner only recessed partial etch-back Top Si Width 25 nm Bottom Si Width 100 nm de Si Fin Height 230 nm unclear tro lec E te Oxide Ga SiO 2

Si S

iO Fin 2 SiN

te ra st Sub Clear Sidewall Open Si Planarization of the Top Surface of Poly-Si Gate Easy nano-scale patterning of gate poly-Si

∗ E. Yoon, J.-H. Lee, and T. park, Korea/Japan/USA/Germany patent

2nd US-Korea NanoForum, LA Jong-Ho Lee Key Process Steps of Modified Bulk FinFET

2nd US-Korea NanoForum, LA Jong-Ho Lee SEM Views of Key Process Steps

Gate

SiO2 SiN SiN Active Fin Si Substrate

Si Substrate

SiN Liner Deposition SiN Recess Etch

2nd US-Korea NanoForum, LA Jong-Ho Lee SEM Views of Key Process Steps

Gate Etch Profiles

Mask SiN Width = 70 nm, Poly-Si Neck Width = 47 nm Poly-Si Bottom Width = 64 nm SiN Gate Stack Gate Stack Poly-Si SiO2

N i S Fins Si Substrate Si Substrate Along Gate Line Across Gate Line

∗ T. Park et al., Samung/SNU/KNU, Symp. on VLSI Tech., 2003

2nd US-Korea NanoForum, LA Jong-Ho Lee SEM and TEM Views of Key Process Steps

SiN Liner30 nmDeposition Si Fin Gate P 99 nm oly-Si 82˚ fin Poly-Si 61 nm

SiO2

N 181 nm i

S iN

S Si Substrate

Along Gate Line 12 nm fin body

∗ T. Park et al., Samung/SNU/KNU, IEDM., 2003

2nd US-Korea NanoForum, LA Jong-Ho Lee Bulk FinFET Measurement

ID-VGS plot: ID, DIBL, SS, and Isub

-4 -4 10 V = 0 V 10 -5 -1 V BS 1 V -5 10 10 -6 V =-0.05 V V =0.05 V -6 Measured ID-VGS of N 10 DS DS 10 10-7 10-7 and P type bulk FinFETs L =100 nm -8 W =25 nm G -8 with drain bias 10 Fin 10

| (A) T =1.8 nm -9 H =100 nm Ox,top -9 high I (~200 µA/µm 10 Fin 10 on

SUB I T =5.5 nm -10 D Ox,top -10 |I 10 10 @ VGS=1.5 V) compared , I | SUB -11 I -11 D 10 V =1 V SUB 10 to that of first lot devices

|I V =-1 V DS -12 DS -12 10 10 low Ioff (<0.2 nA/µm 10-13 10-13 @ V =1.0 V) -0.05 V 0.05 V DS -14 -14 -7 10 10 Isub/ID < ~10 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 Gate Voltage (V)

2nd US-Korea NanoForum, LA Jong-Ho Lee Static Noise Margin (SNM)

Bulk FinFET

Planar MOSFET

Pass Load

W/L Load: 35 nm/90 nm Pull-Down Pass: 35 nm/90 nm Pull-Down: 50 nm/90 nm

2nd US-Korea NanoForum, LA Jong-Ho Lee Summary

Briefly introduced key features of double/triple-gate FinFETs

Bulk FinFETs were compared with SOI FinFETs Nearly the same device scalability Better wafer quality Better characteristics regarding the body connected to sub.

Bulk FinFETs have been demonstrated experimentally First nano-scale bulk FinFET realized by using spacer technology

Modified bulk FinFETs realized by adopting selective Si3N4 recess Good device characteristics were achieved and SNM of

280 mV was obtained from SRAM cell at VCC of 1.2 V

2nd US-Korea NanoForum, LA Jong-Ho Lee 3-D Device Structure for Simulation

Gate LG=25 nm TOX=1.5 nm S/D

S/D S/D S/D

body SiO2

Si substrate Si substrate body

2nd US-Korea NanoForum, LA Jong-Ho Lee Key Process Steps for Thinning of the Fin Body

2nd US-Korea NanoForum, LA Jong-Ho Lee