Introduction to Multi‐gate MOSFETs
Tsu‐Jae King Liu Department of Electrical Engineering and Computer Sciences University of California, Berkeley, CA 94720‐1770 USA
October 3, 2012
6th Annual SOI Fundamentals Class MOSFET Fundamentals
Metal Oxide Semiconductor 0.25 micron MOSFET XTEM Field‐Effect Transistor:
GATE LENGTH, Lg
Gate
Source Drain Si substrate http://www.eetimes.com/design/automotive‐design/4003940/LCD‐driver‐highly‐integrated
GATE OXIDE THICKNESS, Tox
2 MOSFET Operation: Gate Control
Desired N‐channel MOSFET • Current between Source and Drain characteristics: cross‐section is controlled by the Gate voltage. • High ON current Gate • Low OFF current • “N‐channel” & “P‐channel” MOSFETs gate oxide Leff operate in a complementary manner N+ P N+ “CMOS” = Complementary MOS Source Body Drain
log ID Electron Energy Band Profile ION n(E) exp (‐E/kT) E
Inverse slope is subthreshold swing, S Sourceincreasing IOFF [mV/dec] GATE VOLTAGE
increasing 0 V Drain VTH GS V distance DD 3 MOSFET in ON State (VGS > VTH) width velocity inversion‐layer charge density I D W vQinv gate‐oxide capacitance v eff Qinv Cox (VGS VTH ) mobility gate overdrive D I
Gate CURRENT,
Source Drain
DRAIN Substrate
DRAIN VOLTAGE, VDS 4 CMOS Devices and Circuits
CIRCUIT SYMBOLS CMOS INVERTER CIRCUIT V INVERTER N‐channel P‐channel VDD OUT LOGIC SYMBOL MOSFET MOSFET S G G VDD D VIN VOUT S D S D D S GND VIN 0 V CMOS NAND GATE DD STATIC MEMORY (SRAM) CELL NOT AND (NAND) WORD LINE TRUTH TABLE
0 1 or or BIT LINE 1 0 BIT LINE
5 Effective Drive Current (IEFF) CMOS inverter chain: V V V V DD 1 2 3 V2 tpLH IH + IL V /2 V3 DD IEFF = V tpHL 2 1 TIME I IH (DIBL = 0) DSAT VDD VIN = VDD S
D IH VIN = 0.83VDD
V VOUT CURRENT IN D V = 0.75V S IN DD GND DRAIN IL VIN = 0.5VDD NMOS
0.5VDD VDD NMOS DRAIN VOLTAGE = VOUT M. H. Na et al., IEDM Technical Digest, pp. 121‐124, 2002 6 Improving IEFF
Gate log I D ION C ox Ctotal C S dep Cox Source Body Drain VDD VGS • The greater the capacitive coupling between Gate and channel, the better control the Gate has over the channel potential.
higher ION/IOFF for fixed VDD, or lower VDD to achieve target ION/IOFF reduced drain‐induced barrier lowering (DIBL):
log ID increasing VDS increasing Drain Source IOFF VDS VGS 7 CMOS Technology Scaling
XTEM images with the same scale courtesy V. Moroz (Synopsys, Inc.) 90 nm node 65 nm node 45 nm node 32 nm node
T. Ghani et al., (after S. Tyagi et al., IEDM 2005) K. Mistry et al., P. Packan et al., IEDM 2003 IEDM 2007 IEDM 2009
• Gate length has not scaled proportionately with device pitch (0.7x per generation) in recent generations. – Transistor performance has been boosted by other means.
8 MOSFET Performance Boosters
• Strained channel regions eff
• High‐k gate dielectric and metal gate electrodes Cox Cross‐sectional TEM views of Intel’s 32 nm CMOS devices
P. Packan et al. (Intel), IEDM Technical Digest, pp. 659‐662, 2009 9 Process‐Induced Variations
• Sub‐wavelength lithography: – Resolution enhancement techniques are costly and increase process sensitivity
• Gate line‐edge roughness: courtesy Mike Rieger (Synopsys, Inc.)
photoresist
• Random dopant fluctuations (RDF): – Atomistic effects become significant in nanoscale FETs A. Brown et al., SiO2 Gate IEEE Trans. Nanotechnology, p. 195, 2002 Source Drain A. Asenov, Symp. VLSI Tech. Dig., p. 86, 2007
10 Bulk MOSFET Design Optimization
• To maximize IEFF and minimize VTH variation, heavy doping near the surface of the channel region should be avoided.
Use a steep retrograde channel doping profile to suppress IOFF
• tSi is a critical design parameter!
Energy Band Profile: Structure: Double-Gate FET Ground-Plane FET (OFF State) Scale length: Si Si tSitox tSitox longer 2ox 2 ox 1 Sitox / oxtSi Source Drain R.‐H. Yan et al., IEEE Trans. Electron Devices, Vol. 39, pp. 1704‐1710, 1992 11 Thin‐Body MOSFETs
Ultra‐Thin Body (UTB) Double‐Gate (DG)
Lg Lg
Gate Gate Source Drain t Source Drain tSi Si Buried Oxide Gate Si Substrate
B. Yu et al., ISDRS 1997 R.‐H. Yan et al., IEEE TED 1992 12 Why Thin‐Body Structures? • Physically limit the depth of the channel region to eliminate sub‐ surface leakage paths and achieve good electrostatic integrity
• Body doping can be eliminated if tSi is sufficiently thin
higher ION due to higher carrier mobility reduced impact of random dopant fluctuations (RDF)
Lg Ultra‐Thin‐Body MOSFET: Gate
SourceSource DrainDrain “Silicon‐on‐ Buried Oxide Insulator” (SOI) Substrate Wafer
13 Effect of tSi on OFF‐state Leakage
Lg = 25 nm; tox,eq = 12Å
tSi = 10 nm tSi = 20 nm
6 10 G Si Thickness [nm] G 0.0 SD4.0 3x102 8.0 12.0 SD G 16.0 10‐1 20.0 Leakage Current G 2 Density [A/cm ] @ VDS = 0.7 V IOFF = 2.1 nA/ m IOFF = 19 A/ m
14 Relaxing the Body Thinness Requirement
• Thinner buried oxide (BOX) reduced DIBL • Reverse back biasing further reduction of SCE
Impact of BOX Thickness tSi Reduction with Lg Scaling
O. Faynot, IEEE Int’l SOI Conference, 2011 15 Threshold Voltage (VTH) Adjustment
• VTH can be adjusted via substrate doping, for reduced VTH:
TBOX = 10nm
T. Ohtou et al., IEEE‐EDL 28, p. 740, 2007
• VTH can be dynamically adjusted via back‐biasing.
– Reverse back biasing (to increase VTH) is beneficial for lowering SCE. S. Mukhopadhyay et al., IEEE‐EDL 27, p. 284, 2006
16 Double‐Gate MOSFET Structures
PLANAR:
VERTICAL FIN:
L. Geppert, IEEE Spectrum, October 2002 17 Double‐Gate “FinFET”
Planar DG‐FET FinFET
Lg Lg Drain Gate D. Hisamoto et al., IEDM Gate Technical Digest, 1998
Source N. Lindert et al., IEEE tSi Source Drain Electron Device Letters, p. 487, 2001 Gate Fin Height HFIN = W/2 Fin Width = tSi
GATE 20 nm DRAIN Y.‐K. Choi et al., 15nm L FinFET: 10 nm g IEDM Technical Digest, 2001 SOURCE
18 Fin Patterning by Spacer Lithography
• Use spacers to define finsfins, and photoresist to define source/drain contact pad regions: Plan View 3‐D View spacer resist hard mask
Gate spacer Fin SOI BOX
Source Drain CD=1.3nm • Better CD control is sacrificial achieved with spacer lithography • Note that gate line‐edge roughness is not an Y.‐K. Choi et al., issue for FinFETs IEEE Trans. Electron CD=3.6nm Devices, Vol. 49, pp. 436‐441, 2002
19 Impact of Fin Layout Orientation
• If the fin is oriented || or to the wafer flat, the channel surfaces lie along (110) planes. – Lower electron mobility – Higher hole mobility • If the fin is oriented 45° to the (Series resistance is more wafer flat, the channel surfaces
significant at shorter Lg.) lie along (100) planes.
L. Chang et al., SISPAD, 2004 20 Independent Gate Operation • The gate electrodes of a double‐gate FET can be isolated
by a masked etch, to allow for separate biasing. Drain Back‐ – One gate is used for switching. Gate1 Gated Gate2 – The other gate is used for VTH control. FET Source
D. M. Fried et al. (Cornell U.), IEEE Electron Device Letters, L. Mathew et al. (Freescale Semiconductor), Vol. 25, pp. 199‐201, 2004 2004 IEEE International SOI Conference 21 FinFET Layout • Layout is similar to that of conventional MOSFET, except
that the channel width is quantized: Pfin
Source Source Gate Gate Drain Drain
Source Source Bulk‐Si MOSFET FinFET The S/D fins can be merged by selective epitaxy:
Intel Corp. M. Guillorn et al., Symp. VLSI Technology 2008 22 FinFET Design Trade‐Offs
• Fin Width Lg Drain Gate –Determines short‐channel effects
• Fin Height Source – Limited by etch technology –Tradeoff: layout efficiency Fin Height
vs. design flexibility HFIN = W/2 Fin Width = tSi • Fin Pitch – Limited by lithographic capability –Constrains source/drain implant tilt angle Pfin –Tradeoff: performance vs. layout efficiency
Parasitic gate resistance and capacitance depend on Pfin
23 Impact of Random Variations @ 25 nm Lg
• RDF‐induced variations were simulated using KMC model • Gate‐LER‐induced variations were simulated by sampling profiles from an SEM image of a photoresist line
• variations were estimated based on Dadgour et al., 2008 IEDM
tSi = 6 nm tSi = 2Lg/3 tBOX = 10 nm
C. Shin et al., IEEE Int’l SOI Conference, 2009 24 Multi‐gate MOSFETs
I. Ferain, C. A. Colinge, J.‐P. Colinge, Nature 479, 310–316 (2011) SOI Multi‐Gate MOSFET Designs
Tri‐Gate FET Relaxed fin dimensions
WSi > Lg/2; HSi > Lg/5
FinFET Narrow fin
WSi ~ Lg/2
body dimensions required for DIBL=100 mV/V eff L
/ Tox = 1.1nm Si H
UTB FET Ultra‐thin SOI WSi / Leff HSi ~ Lg/5 after Yang and Fossum, IEEE Trans. Electron Devices, Vol. 52, pp. 1159‐1164, 2005 26 Double‐Gate vs. Tri‐Gate FET
• The Double‐Gate FET does not require a highly selective gate etch, due to the protective dielectric hard mask. • Additional gate fringing capacitance is less of an issue for the Tri‐Gate FET, since the top fin surface contributes to current conduction in the ON state.
Double‐Gate FET Tri‐Gate FET
channel
after M. Khare, 2010 IEDM Short Course 27 22nm Tri‐Gate FETs
• Lg = 30‐34 nm; Wfin = 8 nm; Hfin = 34 nm • High‐k/metal gate stack, EOT = 0.9 nm • Channel strain techniques
Transfer Characteristics
PMOS NMOS
C. Auth et al., Symp. VLSI Technology 2012 28 SOI MOSFET Evolution
• The gate‐all‐around (GAA) structure provides for the greatest capacitive coupling between the gate and the channel.
http://www.electroiq.com/content/eiq-2/en/articles/sst/print/volume-51/issue-5/features/nanotechnology/fully-gate-all-around-silicon-nanowire-cmos-devices.html 29 Summary
• Power density and variability now limit conventional bulk MOSFET scaling. • Multi‐gate MOSFET structures can achieve superior electrostatic integrity than the conventional planar bulk MOSFET structure and hence offer a pathway to lower
VDD, reduce VTH variability, and extend transistor scaling.
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