Introduction to Digital Circuits

Basic Logic Circuits The NMOS Inverter The NMOS Depletion Load

+ VDD 50 [I D ] µA VGS = 1.0V 40 = VGS 0.5V VGS2 = 0 30 Depletion Resistance Q2 load characteristic of Q VGS = 0V 20 2 VGS = −0.5V

10 VGS = −1.0V vo VGS = −1.5V v Enhancement i Q1 1 2 3 4 5 6 [VDS ]V driver

Drain characteristic of the load MOSFET Q2

1 ©Loberg Introduction to Digital Circuits

Basic Logic Circuits The NMOS Inverter The NMOS Depletion Load

VDD − VDS2 − vo = 0 I = I The drain characteristic of D2 D1 I the driver MOSFET Q . D1 [I D ] µA 1 ⇒ V = 6.0V 300 GS I = f (V − v ) Load line D2 I D DD o 250 v o 200 A = VOH = 5.8V VGS 5.0V 5 Transfer 150 characteristic of the inverter. 100 VGS = 4.0V 3 50 Load line

VGS = 3.0V 1 B [V ]V V = 0.5V 1 2 3 4 5 6 DS OL v 1 2 3 4 5 6 i

VIL = 2.6V VIH = 3.4V 2 ©Loberg Introduction to Digital Circuits

Basic Logic Circuits The NMOS Inverter The NMOS Depletion Load

VOH = 5.8V

VOL = 0.5V ⇒ Noise Margins VIL = 2.6V

VIH = 3.4V

NM H = VOH min − VIH min = 5.8 − 3.4 = 2.4V

NM L = VIL max − VOL max = 2.6 − 0.5 = 2.1V

The additional processing steps are required to fabricate both depletion and enhancement devices on the same chip.

3 ©Loberg Introduction to Digital Circuits

Basic Logic Circuits The NMOS Inverter The NMOS Depletion Load Summary The Linear (Nonsaturated) Load The Saturated Enhancement Load

Transfer characteristic of the inverter.

vo W 1 Depletion load = 5 L 4 W 1 Linear load = 3 L 4 W 1 Saturated load = L 4 1 W Saturated load = 1 vi 1 2 3 4 5 6 L

4 ©Loberg Introduction to Digital Circuits

Basic Logic Circuits Propagation Delay of an NMOS Inverter

The speed of NMOS inverter is limited by the load capacitors. + + VDD VDD Chargin and discharging time.

Load Depletion RL Transition time load Q2 iL iL v v o Controlled iD o Device capacitances : switch iC iD iC Voltage-dependent R capacitors vi Q ON 1 Input C gate-to-drain driver Ctot tot Driver drain-to-substrate source-to-substrate (a) (b)

(a) An NMOS depletion-load inverter

For pencil-and-paper calculations all capacitive effects (b) Equivalent circuit representation can be summed to form a single total capacitance Ctot .

5 ©Loberg Introduction to Digital Circuits

Basic Logic Circuits Propagation Delay of an NMOS Inverter

Assumptions:

(switch is closed) + VDD When the driver fet Q1 is conducting, the switching element has resistance RON .

(switch is open) Load RL When Q1 is OFF, we assume that the open switch has infinite resistance R . OFF iL v Controlled iD o switch iC

When input is V(0), then output is V(1) = V . RON DD Input ⇒ Ctot Driver

Ctot is charged to VDD (b)

6 ©Loberg Introduction to Digital Circuits

Basic Logic Circuits Propagation Delay of an NMOS Inverter

Input transition is V(0) to V(1) Output transition is V(1) to V(0)

must be discharged toward C vo (t) tot V(0) . V (1)

1 [V (1)+ V (0)] 2

vo (t = 0) = VDD = V (1) V (0) t t R pHL ON t = 0 switch is closed vo (t = ∞) = VDD = V (0) RL + RON

Time constant

τ HL = Ctot (RON RL ) 7 ©Loberg Introduction to Digital Circuits

Basic Logic Circuits Propagation Delay of an NMOS Inverter

Output transition is V(1) to V(0)

1 1 V ' = v (t ) = V (0) + [V (1)− V (0)] = [V (1)+ V (0)] o pHL 2 2

The capacitor discharge exponentially

vo (t) from V(1) toward V(0). V (1) (Assumption)

1 RL and RON are constant V ' [V (1)+ V (0)] 2 ⇒ t can be calculated from the analytical pHL expression for the exponent curve. V (0)

t Time constant tpHL τ HL = Ctot (RON RL )

8 ©Loberg Introduction to Digital Circuits

Basic Logic Circuits Propagation Delay of an NMOS Inverter

Input transition is V(1) to V(0) Output transition is V(0) to V(1)

must be charged toward Ctot V(1) . v (t) o V (1)

1 [V (1)+ V (0)] 2 RON vo (t = 0) = VDD = V (0) V (0) RL + RON t t pLH switch is open vo (t = ∞) = VDD = V (1)

9 ©Loberg Introduction to Digital Circuits

Basic Logic Circuits Propagation Delay of an NMOS Inverter

The capacitor is charged exponentially Output transition is V(0) to V(1) from V(0) toward V(1).

(Assumption) Time constant RL is constant

τ LH = Ctot RL ⇒ t can be calculated from the analytical pLH expression for the exponent curve.

Since RL >> RON ⇒ t pLH >> t pHL

In practical circuits, resistances RL and RON depends on voltage.

We must use approximation, based on the amount of charge transferred to (or from) Ctot .

10 ©Loberg Introduction to Digital Circuits

Basic Logic Circuits Propagation Delay of an NMOS Inverter

Approximative calculations for tpHL + VDD

Load R Discharge current is : iC = iD − iL L i iC is time-varying L v Controlled iD o Iav is average value of iC during time interval ∆t switch iC

∆Q is change of charge on Ctot during time interval ∆t RON Input Ctot Driver ∆Q = Iav∆t = Ctot ∆vo

C When ∆t = tpHL t = tot [V (1)− V (0)] pHL ⇐ 1 2 Iav ∆v = [V (1)− V (0)] o 2

11 ©Loberg Introduction to Digital Circuits

Basic Logic Circuits Propagation Delay of an NMOS Inverter

Approximative calculations for tpHL 1 I = [i (v = V )+ i (v = V ' )] av 2 C 0 OH C o iC = iD − iL vo (t) ' 1 V (1) V = [V + V ] VOH 2 OH OL 1 V ' [V (1) + V (0)] 2

VOL V (0) t tpHL

1 Iav = [(iD − iL ) + (iD − iL ) ' ] 2 VOH V 12 ©Loberg Introduction to Digital Circuits

Basic Logic Circuits Propagation Delay of an NMOS Inverter

1 Approximative calculations for tpLH I = [i (v = V ' )+ i (v = V )] av 2 C o C 0 OL

vo (t) V V (1) OH

1 [V (1)+ V (0)] ' 2 V

V (0) VOL t tpLH switch is open

C t = tot [V (1)− V (0)] 1 pLH Iav = [(iD − iL ) + (iD − iL ) ' ] V V 2 Iav 2 OL 13 ©Loberg Introduction to Digital Circuits

Basic Logic Circuits The NMOS NOR Gate

A B Y

v1 State v2 State vo State ≤ V 0 ≤ V 0 ≥ V 1 + V IL IL OH + VDD DD ≤ VIL 0 ≥ VIH 1 ≤ VOL 0 ≥ ≤ ≤ VIH 1 VIL 0 VOL 0 Load R Depletion L ≥ V 1 ≥ V 1 ≤ V 0 load IH IH OL Y Controlled The truth table of the 2-input NMOS NOR gate. switches Y

A B A B vo Y = A + B v vo v 2 1 Drivers drivers

(a) (b) Idealized representation An NMOS NOR gate. of the NMOS NOR gate.

14 ©Loberg Introduction to Digital Circuits

Basic Logic Circuits The NMOS NAND Gate

A B Y v State v State v State 1 2 o + V + DD V1(0) 0 V2 (0) 0 V0 (1) 1 VDD Load RL V1(0) 0 V2 (1) 1 V0 (1) 1 Depletion load V (1) 1 V (0) 0 V (1) 1 Y 1 2 0 Y V (1) 1 V ( ) 1 V (0) 0 Controlled v 1 2 0 vo switches o The truth table of the 2-input NMOS NAND gate. A v1 A B B v2 drivers

Y = A⋅ B (a) (b) An NMOS NAND gate. Idealized representation of the NMOS NAND gate.

15 ©Loberg Introduction to Digital Circuits

Basic Logic Circuits The CMOS Inverter Complementary Metal-Oxide-Semiconductor circuits Assumptions :

MOSFETs are perfectly matched. Virtually no static power dissipation

⇒ VTON = VTOP + VDD λN = λP + µC  W  VDD K = K = 0   Q PMOS N P 2  L  2 load

vi vo Where µ is mobility of charge carrier: A electron or hole vo Electrons has higher mobility NMOS Q1 A ⇒ driver

 W   W    ≈ 2.5  The circuit diagram Equivalent representation  L PMOS  L NMOS of a CMOS inverter. of the CMOS inverter.

16 ©Loberg Introduction to Digital Circuits

Basic Logic Circuits The CMOS Inverter

Drain characteristics with Channel-Length Modulation

Ohmic region (Linear) VGS − VTO > VDS I D Boundary

Saturation region

VGS − VTO < VDS

Subthreshold

VGS < VTO

VDS

Drain characteristics of n-channel enhancement MOSFET 17 ©Loberg Introduction to Digital Circuits

Basic Logic Circuits The CMOS Inverter

PMOS linear NMOS off v o PMOS linear NMOS saturated + VDD VOH

PMOS Q2 load V PMOS and NMOS saturated v TO vi o VDD 2 VTO Q NMOS PMOS saturated NMOS linear 1 driver

PMOS off NMOS linear VOL

The circuit diagram V V VDD vi of a CMOS inverter. IL IH

VDD − VTO VDD /2

18 Introduction to Digital Circuits

Basic Logic Circuits The CMOS Inverter

Enhancement-mode MOSFET

Ohmic Region VGS −VTO > VDS

 W  W/L = aspect ratio 2 W = channel width I D = k [2(VGS − VTO )VDS − VDS ] 1 L = channel length  L  k = µnC0 2 VTO = threshold voltage k = process parameter

Boundary Region VGS −VTO = VDS µn = electron mobility C = gate capacitance per unit area fF/µm2  W  0 I = k V 2 D  L  DS Typical values of parameter k

2 Saturation Region VGS −VTO < VDS 10 to 50 µA V

Early voltage = 1/λ  W  2 I = k (V − V ) (1 + λV ) DS  L  GS TO DS Millman/Grabel

19 ©Loberg Introduction to Digital Circuits

Basic Logic Circuits The CMOS Inverter SPICE MODEL (large signal) Ohmic Region VGS −VTO > VDS Enhancement-mode MOSFET KP W  I =  [2(V −V )V −V 2 ] D 2  L  GS TO DS DS

Saturation Region VGS −VTO < VDS KP = µnC0 2 Typical values : VTO = 0.7V KP = 30 µA/V KP W  2 I =  (V −V ) DS 2  L  GS TO

Saturation Region with channel-length modulation

KP W  2 I =  (V −V ) (1+ λV ) DS 2  L  GS TO DS

20 ©Loberg Introduction to Digital Circuits Basic Logic Circuits The CMOS Inverter

Saturation Region vGS1 − VTO < vDS1

KPN  W  2 vGS1 = vi vSD2 = VDD − vo iD1 =   (vi − VTO ) (1 + λvo ) 2  L N vDS1 = vo vSG2 = VDD − vi

KP  W  2 i = P   (V − v − V ) [1 + λ(V − v )] D2 2 L DD i TO DD o  P + VDD

iD1 (vi ) = iD2 (vi ) where vi = VDD 2 vSG2 Q PMOS vSD2 2 load VDD ⇒ vo = Assumption: 2 MOSFETs are identical vo v v k = 1 i o Switching-point voltage vGS1 Q NMOS vDS1 (ideal) 1 driver VTO V DD PMOS and NMOS 2 V saturated The slope of the transfer TO The circuit diagram characteristic at switching-point can of a CMOS inverter. be calculated from small-signal gain vo / vi . vi V VDD /2 DD 21 ©Loberg Introduction to Digital Circuits

Basic Logic Circuits The CMOS Inverter

gm1Vgs1 + g V Unloaded voltage gain : G m2 gs2 2 G + - 1 + V V V o Vo V gs2 gs1 A = = −(g + g )(r r ) i - rd1 rd2 v m1 m2 d1 d2 S + S - Vi - 2 1

Small-signal model of the push-pull stage

Assumption: MOSFETs are identical vo = −∞ ⇒ Av = −gmrd Slope

VDD 2 If we use "ideal" MOSFETs, then PMOS and NMOS saturated

(λ = 0) Av = −gmrd ≈ −∞ when rd ≈ ∞

V vi VDD /2 DD 22 ©Loberg Introduction to Digital Circuits

Basic Logic Circuits The CMOS Inverter

KP  W  KP  W  P   < N   2  L P 2  L N

KP  W  KP  W  P   = N   vo 2  L P 2  L N

KP  W  KP  W  P   > N   2  L P 2  L N VDD 2

vi V VDD /2 DD

23 ©Loberg Introduction to Digital Circuits

Basic Logic Circuits Power Dissipation of CMOS Logic

Total Power Dissipation :

Ptot = Pdync + Pdp + Pstatic

Dynamic Power Consumption

Pdync Dissipation due to load capacitances

Dissipation due to direct - path current Pdp

Static Power Consumption

Pstatic Leakage currents

Basic Logic Circuits Power Dissipation of CMOS Logic

Dynamic Power Consumption Pdync

+ V DD iVDD Energy-consuming transition iVDD t

vo vo

Charge Discharge t

Stored energy in capacitance during low-to-high transition:

∞ VDD 1 = = = 2 EC ∫ iVDD (t)vodt CL ∫ vodv CLVDD 0 0 2 Q = CU

Basic Logic Circuits Power Dissipation of CMOS Logic

Dynamic Power Consumption Pdync

Energy, taken from supply during low-to-high transition:

∞ ∞ dv E = i (t)V dt = V C o dt = C V 2 VDD ∫0 VDD DD DD ∫0 L dt L DD

Energy, dissipated by PMOS during low-to-high transition: 1 E = E − E = C V 2 PMOS VDD C 2 L DD

Energy (stored in CL), dissipated by NMOS during high-to-low transition: 1 E = C V 2 C 2 L DD

E = C V 2 VDD L DD

26 Introduction to Digital Circuits

Basic Logic Circuits Power Dissipation of CMOS Logic

Dynamic Power Consumption Pdync

Switching activity

f0→1 = frequency of energy consuming transitions

Power consumption for inverter

2 Pdync = CLVDD f0→1

For more complex 2 gates and circuits Pdync = CEFFVDD f

CEFF is average capacitance switched every clock cycle.

Basic Logic Circuits Power Dissipation of CMOS Logic

Dynamic Power Consumption Pdp

Dissipation Due to Direct - Path Currents (For inverter)

iSHORT iPEAK VDD t T

Energy in one cycle (time period T) ?

Basic Logic Circuits Power Dissipation of CMOS Logic

Dynamic Power Consumption Pdp

Dissipation Due to Direct - Path Currents Simple approximation Time when both devices are conducting Assumption: Rise and fall times are equal. Approximation iSHORT ⇒ I t I t I PEAK E = V PEAK sc + V PEAK sc = V I t dp DD 2 DD 2 DD PEAK sc ⇒ v tsc o E dp = P = t V I f V − V dp sc DD PEAK DD TO T

VTO

Basic Logic Circuits Power Dissipation of CMOS Logic

Dynamic Power Consumption Pdp

t V − 2V tr(f ) I PEAK s DD TO tsc = (VDD − 2VTO ) ≈ VDD VDD 0.8 90%

VTO Short-circuit power dissipation can be modeled by adding a load capacitance Csc in parallel 0.8VDD with CL .

10% "Short-circuit capacitance" t vo r C V sc CL TO tsc

E Q I t dp 2 where = sc = PEAK sc = Pdp = tscVDD I PEAK f = CscVDD f Csc T VDD VDD

Basic Logic Circuits Power Dissipation of CMOS Logic

Static Power Consumption P Static Power Consumption Pstatic static

The static (or steady-state) power Istat is the current that flows dissipation of a circuit is between the supply rails in the expressed by the relation : Pstat = IstatVDD absence of switching activity.

Typical leakage current 2 (For inverter) per unit drain area : 10 − 100 pA/ µm + VDD 1 million gates 0.5µm2 drain area VDD = 2.5V v = V ⇒ 0.125mW Low o DD

However, leakage current depends on Drain Leakage Current the temperature. Subthreshold It doubles on every 10°C current

Ta = 85°C ⇒ Leakage currents increase by a factor of 60 over their room temperature values. 31 ©Loberg Introduction to Digital Circuits

Basic Logic Circuits Power Dissipation of CMOS Logic

Total Power Consumption Ptot

2 Ptot = Pdync + Pdp + Pstatic = (CLVDD + VDD I peaktsc )f0→1 + VDD Ileak

Capacitive power dissipation is by far the dominant factor