MOSFET Transistor I-V Characteristics

MOSFET transistor I-V characteristics

Linear region: []() K = C µ iD = K 2 vGS – Vt vDS n ox n vDS « vGS – Vt W K = ------K 2L n []()2 Triode region: iD = K 2 vGS – Vt vDS – vDS < vDS vGS – Vt

vDS = vGS – Vt sat (current) Saturation region: []()2 ()λ iD = KvGS – Vt 1 + vDS ≥ vDS vGS – Vt

iD + + vGS vDS - -

Lecture 20-1

Is the transistor in saturation region? vDS = vGS – Vt sat Vt = 1V

V D = 3.5V V D = 3.5V

VG = 4V VG =

VS = 2V VS = 2V

Lecture 20-2

Body Effect

• The source and bulk will not be at zero volts all of the time • The p-type bulk will be connected to the lowest supply voltage for an IC • Discrete MOSFETs may have bulk tied directly to the source

• But for ICs we can assume that there can be a positive VSB for NMOSFETs

VS2>0 VS2B>0 VS2B=0 VB

V =0 VS1B=0 S1B

Lecture 20-3 Body Effect

• Positive VSB for NMOSFETs tends to increase QB, hence decrease QI, for a ﬁxed VGS

VGS > Vt VS>0 VDS > 0 + QI n+ QB0 n+

Lecture 20-4 Body Effect

• Modeled as a change in the threshold voltage as a function of VSB • The source is, by deﬁnition for NMOSFET, at a lower positive potential than the drain, which is why we use it as our reference voltage

γ ()φ φ Vt = Vt0 + 2 f +2VSB – f

• SPICE will calculate this variation in threshold voltage, or you can over-ride its calculation by directly specifying gamma

Lecture 20-5 Temperature Variations • The threshold voltage varies with temperature due to carrier generation in the substrate --- tends to decrease with increasing temperature •~2mV for every 1ºC increase

γ ()φ φ Vt = Vt0 + 2 f +2VSB – f • K also changes with temperature due to change in mobility

•Tends to dominate temperature variation for large iD 1 W 2 I ∝ ---µ C -----()v – V 2 n ox L GS t

• Will iD increase or decrease with temperature?

T2 > T1

Lecture 20-6 Where is drain, where is source?

D S G G B B

S D n-channel transistor p-channel transistor

Lecture 20-7 PMOSFETs

• All of the voltages are negative • Carrier mobility is about half of what it is for n channels

S G D p+ p+

n B

• The bulk is now connected to the most positive potential in the circuit • Strong inversion occurs when the channel becomes as p-type as it was n-type • The inversion layer is a positive charge that is sourced by the larger potential and drained at the smallest potential • The threshold voltage is negative for an enhancement PMOSFET •Note that the ﬂatband voltage (which is negative) effects now tend to increase the PFET threshold while they decreased the NFET threshold

Lecture 20-8 PMOS

• The equations are the same, but all of the voltages are negative • Triode region: ≥ ≤ vGS Vt vDS vGS – Vt 2 1 W A i = K[]2()v – V v – v K = ---µ C ------D GS t DS DS n ox 2 2 L V

• iD is also negative --- positive charge ﬂows into the drain • Saturation expression is the same as it is for NFETs:

[]()2 ()λ iD = KvGS – Vt 1 + vDS sat +V dd

Lecture 20-9 PMOS

• Characteristic appears to be the same, except that all of the voltages are negative

VDS -5 -4 -3 -2 -1 0 10 VGS=-1.0V 0

-10 V =-1.5V GS W=1 micron -20 L=1 microns Vt0= -1 volt (µA) -30 V =-2.0V 2 GS Kp=2e-5 (A/v ) DS I -40 phi =-0.6 -50 ND=1e15 -60 VGS=-2.5V -70 -80 -90 VGS=-3.0V -100

Lecture 20-10 PMOS

• But it is generally displayed as:

-VDS 0 1 2 3 4 5 100

90 VGS=-3.0V 80 70 W=1 micron V =-2.5V L=1 microns (µA) 60 GS Vt0= -1 volt DS 2 50 K =2e-5 (A/v ) -I p 40 phi =-0.6 N =1e15 30 VGS=-2.0V D 20 10 VGS=-1.5V 0 VGS=-1.0V -10

Lecture 20-11 Depletion Mode NMOSFET

• Depletion mode FETs have a channel implanted such that there is conduction with VGS=0 • The operation is the same as the enhancement mode FET, but the threshold voltage is shifted

•Vt is negative for depletion NMOS, and positive for depletion PMOS

VGS VS VDS

n+ n+ n+

Lecture 20-12 Depletion Mode NMOSFET

• Negative gate voltage is required to turn the channel off

VDS 0 1 2 3 4 5 0.4

VGS=2.0V

(mA) W=1 micron

DS L=1 microns I Vt0= -2 volt VGS=1.0V 2 Kp=2e-5 (A/v ) 0.2

VGS=0.0V

VGS=-1.0V

0.0 VGS=-2.0V

Lecture 20-13 Depletion Mode NMOSFET

• The iDS vs. vGS characteristic is still quadratic in saturation

VGS -4 -3 -2 -1 0 1 2 3 4 5 2

W=1 micron L=1 microns V = -2 volt t0 2 Kp=2e-5 (A/v )

(mA) 1 DS I

Lecture 20-14 Examples

• Find the largest value that RD can have before the transistor fails to operate in saturation 5V Vt = 2V 2 K = 20µAV⁄ RD n L = 10µm W = 400µm λ = 0 5kΩ

-5V

Lecture 20-15 Examples

• Find the drain currents and voltages for both transistors

10V 10V Vt = 2V 2 K = 20µAV⁄ 10kΩ 15kΩ n L = 10µm M2 M1 W = 100µm λ = 0

Lecture 20-16 Examples

• What is the effective resistance of the transistor in the triode region?

10V

Ω 24.8k Vt = 1V 2 K = 0.5mA⁄ V

Lecture 20-17 Examples

• Select the R’s so that the gate voltage is 4V, the drain voltage is 4V and the current is 1mA.

10V 10V Vt = 2V 2 RG1 RD K = 1mA⁄ V λ = 0

RG2 RS

Lecture 20-18 Examples

• Select the R’s so that the transistor is in saturation with a drain current of 1.0mA and a drain voltage of 5V

10V

RG1 Vt = –1V 2 K = 0.5mA⁄ V λ = 0

RG2 RD

Lecture 20-19 Examples

• Solve for the drain current and voltage

20V Vt = –2V 2 32kΩ K = 1mA⁄ V λ = 0

10MΩ 4kΩ

Lecture 20-20