MOS CAPACITOR – MOSFET TRANSISTOR – MOS INVERTERS
Prof. Philippe LORENZINI Polytech-Nice Sophia Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 2
Outline
• Metal Oxyde Semiconductor Structure • MOS Transistor • MOS Inverters • NMOS • CMOS Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 3
• Two definitions (only 2!) • Work Function (Travail de sortie)eM : this is the energy we have to give to an electron to extract it of metal without kinetic energy. It reaches the "vacuum level". Work function is the energy difference between the vacuum level and the highest occupied energy level, ie the Fermi level.
• Electron Affinity (Affinité électronique )e SC : it’s the difference between the vacuum level and the bottom of the conduction band. It’s only defined for SC and not for Metal.
• Unity for both of them: eV (electron volt) Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 4
Metal Oxyde Semiconductor Structure Energy band diagram of the three components of a MOS system
MOS capacitor E g SC SC 2e fi Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 5
Field Effect Transistor
• The field effect is the variation of the conductance of a channel in a semiconductor by the application of an electric field Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 6 Equilibrium of MOS structure
dV d 2V (x) Vbi M SC , E , 2 dx dx SC
Metal SC(n) Metal SC(n)
e SC eSC eVbi e E M C e e M SC e E SC F EC EF E F EF E V EV dx Independant system Equilibrium state Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 7
Ox The five regimes : a function of work function
(a) Accumulation
(b) Flat band
(c) Desertion / depletion
(d) Weak inversion
(e) Strong inversion Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 8 Energy band diagram for ideal n and p type MOS capacitors under different bias conditions Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 9 Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 10
Field, potential and charges in Silicon
We suppose we deal with a p type semiconductor:
warning: in few books, e E E 0 absolute value is not Fi F Fi present!!!!
V (x ) 0, V (x 0) Vs, Vg Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 11
Field, potential and charges in Silicon
d2V (x) Poisson’s Equation: 2 dx SC
(x) ep(x) n(x) N D (x) N A (x)Charge density
e e Fi Fi p n N N n n exp( ) p0 ni exp( ) 0 0 A D 0 i kT kT eV(x) e(V (x) ) n(x) n exp( ) n exp( Fi ) 0 kT i kT
e(V (x) Fi ) eV (x) p(x) ni exp( ) p0 exp kT kT Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 12
Field, potential and charges in Silicon
eV ( x) eV ( x) kT kT (x) en0 p0 p0e n0e
2 eV (x) eV (x) d V (x) e kT kT 2 p0 (e 1) n0 (e 1) dx SC
d 2V (x) d dV (x) d dV (x) dV (x) dx 2 dx dx dV dx dx
eV ( x) eV ( x) dV (x) dV (x) e kT kT d p0 (e 1) n0 (e 1)dV (x) dx dx SC Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 13
Field, potential and charges in Silicon •We compute the integral from bulk to a point x in SC
dV ( x ) MO S V(x=« bulk »)=0 et 0 Vg dx bulk
eV (x) eV (x) dV (x) V ( x) dx dV (x) dV (x) e kT kT d p0 (e 1) n0 (e 1) dV (x) 0 0 dx dx SC dV (x) And the Electric Field is given by: E(x) dx
2 eV (x) eV (x) 2 dV (x) 2kTp0 eV (x) n0 eV (x) E (x) e kT 1 e kT 1 dx SC kT p0 kT Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 14
Field, potential and charges in Silicon
2 2 eV (x) eV (x) 2 dV (x) kT 2 kT eV (x) n0 kT eV (x) E (x) 2 e 1 e 1 dx e LD kT p0 kT
SC kT With the Debye length: LD 2 e po Q If we use the Gauss’s theorem: SC E(x 0) ES SC
1 eV e(V 2 ) 2 S S FI kT SC 2 kT eVS kT n0 eVS QSC e 1 e 1 Qmetal e LD kT p0 kT Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 15
Allways negligible (p type) Field, potential and charges in Silicon
1 eV e(V 2 ) 2 S S FI kT SC 2 kT eVS kT n0 eVS QSC e 1 e 1 Qmetal e LD kT p0 kT
For Vs (and so Vg) negative (accumulation)
For Vs (and Vg) positive but less than 2fi (depletion – weak inversion)
For Vs (and Vg) > 2fi (strong inversion) Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 16
Weak / Strong Inversion 2kT N A VS 2 Fi ln e ni
eFI
ns=p0=NA
This condition will define a very important parameter of the struture: the threshold voltage or the required gate voltage to put the transistor in strong inversion regime Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 17
Measurement of capacitance in Ideal MOS Structure
The C-V curve is usually measured with a CV meter: • We apply a DC bias voltage Vg + small sinusoidal signal (100 Hz to 10 MHz) • We measure the capacitive current with an AC meter (90 degree phase shift)
=> icap/vac =C Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 18
Measurement of capacitance in Ideal MOS Structure
When a voltage Vg is applied to the MOS Gate, part of it appears as a potential drop across oxide and the rest of it appears as a band bending Vs in silicon:
Q SC SC is grounded, Vg Vox VSC VS so V =VS Cox SC
V(X) MO S VOX Vg VG V Vox VSC S Oxide and Silicon have -t 0 X capacitor behavior OX Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 19
Measurement of capacitance in Ideal MOS Structure
• Oxide capacitance: as a parallel‐plate capacitor
ox 2 Cox F/cm dox • We can also write :
QM QM dQM Cox VOX (VG VS ) d(VG VS ) Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 20
Measurement of capacitance in Ideal MOS Structure
• Semiconductor (silicon) capacitance
(charge in SC) d(QSC ) d(QM ) CSC (voltage across SC) dVS dVS Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 21
Measurement of capacitance in Ideal MOS Structure
M O S Vg • Global capacitance of the structure: Vox VSC dQM dQSC CMOS dVG dVG • If we combine the 3 relations above :
1 1 1 2 capacitances connected in series CMOS Cox CSC Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 22
Measurement of capacitance in Ideal MOS Structure
• Total charge in SC depends on different regimes 2 types of charges, fixed and mobile/free:
QSC free carriers charges fixed charges QS Qdep
Semiconductor capacitance can be written as:
dQsc (dQS dQdep ) dQS dQdep CSC dVS dVS dVS dVS Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 23
Measurement of capacitance in Ideal MOS Structure
• Total charge in SC depends on different regimes 2 types of charges, fixed and mobile/free:
QSC free carriers charges fixed charges QS Qdep
Semiconductor capacitance can be written as:
dQ sc C SC C S C dep dV S Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 24
Measurement of capacitance in Ideal MOS Structure
• Summary: MOS capacitor is equivalent : - of 2 capacitors series connected, COX and CSC - CSC is equivalent of two capacitors - the two are variable and be view as 2 capacitors in //
C ox Cox
Csc Cs Cdep
Conclusion: the whole capacitance of MOS structure is function of bias conditions or operating regime through
CSC Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 25
Capacitance of MOS structure
• Accumulation Regime: VS<0 ie VG<0 1 eV e(V 2 ) 2 S S FI kT SC 2 kT eVS kT n0 eVS QSC e 1 e 1 Qmetal e LD kT p0 kT
eV S SC 2 kT 2 kT Q SC e 0 eL D
dQSC e e CSC QSC Cox Vg VS dVs 2kT 2kT Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 26
Capacitance of MOS structure
• Accumulation Regime: VS<0 ie VG<0
1 eV eV 2 S S kT SC 2 kT eVS n0 kT eVS QSC e 1 e 1 Qmetal e LD kT p0 kT
2kT 1 1 1 1 e C ox CMOS Cox CSC Cox Vg VS
Csc 2kT 1 1 1 e C C V V MOS ox g S Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 27
Capacitance of MOS structure
• Accumulation Regime: VS<0 ie VG<0
1 eV eV 2 S S kT SC 2 kT eVS n0 kT eVS QSC e 1 e 1 Qmetal e LD kT p0 kT
kT=26 meV, in accumulation regime VS is around ‐0,3 V to ‐0,4 V, as soon as VG<‐1 to ‐2 V, so we can simplify to:
2 kT 1 1 1 1 e C C V V C MOS ox g S ox Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 28
Capacitance of MOS structure
• Flat Band: VS =0 V ie VG=0 V (warning : ideal structure!!!!!)
SC Analytical computing: CSC ( fb) LD
C ( fb) ox ox MOS ox ox kT SC dox LD d ox SC SC e N A Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 29
Capacitance of MOS structure
• Depletion regime and weak inversion
0 VS 2 Fi
1 2 1 2 SC kT eVS 2 QSC 2eN A SCVS Qdep 0 eLD kT Insulator 1 dQ eN 2 C SC A SC SC SC dVS 2VS Wdep
Wdep Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 30
Capacitance of MOS structure
• Depletion regime and weak inversion
0 VS 2 Fi 1 dQ eN 2 C SC A SC SC SC dV 2V W S S dep C C (depletion) ox ox MOS 2 ox 1 (2C V / eN ) dox Wdep ox g SC A SC Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 31
Capacitance of MOS structure
• Strong inversion VS 2Fi
1 eV e(V 2 ) 2 S S FI kT SC 2 kT eVS kT n0 eVS QSC e 1 e 1 Qmetal e LD kT p0 kT
e (V S 2 FI ) SC 2 kT 2 kT Q SC e 0 eL D
dQ e(Vs 2FI ) 1 1 1 1 C SC e 2kT SC C C C C dVs 2LD MOS ox SC ox Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 32
Capacitance of MOS structure Strong inversion accumulation dep 2kT 1 1 1 e C C V V MOS ox g S
C ( fb) ox MOS ox dox LD SC ???
ox CMOS (depletion) ox dox Wdep SC
p type SC Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 33 Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 34
Capacitance of MOS structure
• Strong inversion:
Which mechanism governs the onset of strong inversion layer?
P type SC : we must create electrons at oxide/SC interface. Where they come from? From Metal : NO because oxide barrier From SC (neutral region) : NO minority carriers (e‐)
Only one solution: thermal (or optical) generation Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 35
Capacitance of MOS structure
• Strong inversion: • Thermal generation? • N°1 :In the space charge + dissipation of charge by electric field E F • N°2 : In the neutral region (a) recombination + + p ++ 0W + + + space charge diffusion zone zone semitransparent metal contact (b) metal p+ SiO 2 n n+
First mechanism dominates but it’s a slow (c) one. Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 36
Capacitance of MOS structure
• Strong inversion • Which Delay time to create strong inversion layer ?
Shockley-Read equation n g i Strong inversion limit: n = N th 2 S A m N g N 2 A th S A S n m i N Si: A 10 -3 More realistics S 1- 10 m ni=10 cm 15 -3 ni NA=10 cm s=1s !! -5 m=10 s Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 37
Capacitance of MOS structure
• When we measure C(V) , results depend on YES or NO, we give enough time to create this layer • YES: we measure capacitance du to inversion layer • NO : Depletion layer preserves the neutrality of the system with an increase of its width . The limit is the breakdown of the semiconductor
Results are frequency dependant Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 38
Capacitance of MOS structure: strong inversion
3 cases :
Low frequency High frequency High frequency + + + Slow ramp Vg Slow ramp Vg High ramp Vg
Q Q Q
x x x Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 39 Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 40
Capacitance of MOS structure: strong inversion
• minimum capacitance (HF):
BF 2 sc 4 sckT Wmax 2 Fi 2 ln(N A / ni ) eN A e N A HF
1 1 4kT ln(N A / ni ) 2 Cmin Cox sce N A Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 41
MOS capacitor : parasitic effects
• 2 factors modify « ideal » structure of MOS capacitor. • The Charges in oxide and/or Charges at interface Oxide – SC. • The Difference between the work function of the Metal and the SC
Influence on the threshold voltage VT of the structure. Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 42
MOS capacitor :oxide charge
• Distribution of charges in the oxide : K+ Na+ Ionic mobiles • Mobile ionic charge SiO2 • Oxide traped charge ----- traped • Fixed oxide charge + + + +
• Traped charge at Si-SiO2 interface + + + + + SiOx x x x x Si
Depending on their position in the oxide, the charges will influence more or less on the electron population below the gate. Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 43
MOS capacitor :oxide charge
• Effect of a sheet charge of areal density Q within the oxide layer of an MOS capacitor: Q V =0V (x) Oxide charges are g compensated with charges Metal Oxyde Si in Metal AND SC.
0 x1 x
Q Vg=Vfb (x) If Vg=Vfb, charges in SC must be zero. Only Metal « DO the job »
d x ox xQox x Qox -Q Vg ox d ox Cox Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 44
MOS capacitor :oxide charge
• The effect is maximum when the charges are located at the interface oxide - SC, ie Qox=QSS (and no effect if Qox close to Metal)
Qss x d ox Vg Cox It is a common practice to define an equivalent
oxide charge per unit area Qox located at the oxide – silicon interface (ie QSS):
Qox (VS ) Vg (VS ) VFB Cox Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 45 Work function difference
• Work function difference non zero oxide field.
• Even when Vg = 0 V, structure show a band bending
e
Depletion zone
A gate voltage must be applied to restore the flat band
condition VFB = M – S = MS : this voltage is called Flat Band voltage VFB Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 46 Work function difference
• Work function difference. • Example: polysilicon n+ gate on p-MOS
poly e silicium n E g SC Silicium 2e fi
poly Eg kT Na MS fi 0.56 ln( ) 2e e ni Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 47
Non ideal MOS capacitor
• Taking into account both Oxide charges and work- function difference, the global flat band voltage can be written as:
Qox VFB MS Cox
Warning: this is the voltage we have to apply on the gate to restore de flat band condition. Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 48 Threshold voltage
• Key parameter for behavior understanding of transistor
• Many definitions (same results!):
• nS = NA
• Vs = 2 fi • … Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 49 Threshold voltage
VT is simply the applied gate voltage when the surface potential or band bending reaches 2FI and the silicon charge is equal to the bulk depletion charge for that potential
4 SCeN A Fi VT Vg (VS 2 Fi ) 2 Fi VFB (from slide 16) COX
V(X) (we suppose here that no bias of bulk is present no V OX (V 0) body effect) FB VT VS=2FI
-tOX 0 X Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 50 Threshold voltage
• Substrate sensitivity - Body Effect
• In general the MOS devices have a common silicon substrate substrate voltage is equal for all transistor.
• BUT when multiple NFETs (or PFETs) are connected in series in a circuit, they share a common body (the silicon substrate) but their sources do not have the same voltage. We must introduce a coefficient that accounts for this effect : Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 51 Threshold voltage
>0 >0 +++++++ + +++++++++
-- - + + +
=0 <0 One part of Gate voltage is no more used to create inversion layer but just to
compensate the extra depletion width VT will increase Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 52 Threshold voltage
• The new threshold voltage taking account the body effect can be written as: 2eN A SC VT VT 0 2 Fi VSB 2 Fi Cox • The substrate sensitivity as:
dVT 1 dQ sceNa / 2(2 Fi VSB ) Q et VT dVSB Cox dVSB Cox Cox
• Of course substrate bias have to be reverse to prevent current flow Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 53 Threshold voltage
1,8 Na = 1E16 cm-3 Na = 3E15 cm-3 1,6
(V) d 200 A ox
VFB 0V
T 1,4
1,2
1,0
Threshold voltage 0,8
0 2 4 6 8 10
Substrate bias voltage VSB (V) The effect of (reverse) substrate bias is to widen the bulk depletion region and raise the threshold voltage: • The back contact acts as a back Gate
• We can tune VT ! MOS-FET TRANSISTOR Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 55
MOS-FET transistor Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 56 Graphical summary of the major processing steps in the formation of a MOSFET Transistor
http://www.youtube.com/watch?v=dR-Qtv-7uWI Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 57
MOS-FET transistor
Stockage time ? Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 58 Linear regime Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 59 Saturation / linear limit Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 60
Saturation regime
Effective length of canal decreases from L to L’ Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 61
Basic MOSFET IV Model
• L, canal length( y oriented) • W, canal width(z oriented) • V, voltage in the canal (f(y))
• V(y=0) = V(source) = Vs = 0 V • V(y=L) = V (drain) = Vds • Vg, gate voltage
• -VBS, body voltage Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 62
Schematic MOSFET cross section (Taur) Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 63
Charge sheet approximation
• Analytical solution we simplify the model:
• Charge sheet approximation (xi=0): • We assume all the inversion charges are located at the silicon interface without any thickness • No potentiel drop across this layer • No band bending across this layer Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 64
Charge sheet approximation
First step: calculation of inversion layer charge function of Vg
Q dep eN AW M 2eN A SC V S ( y) 2eN A SC (2 Fi V ( y) )
Qsc (y) Qmétal (y) Cox (Vg VFB VS (y)) Cox (Vg VFB 2 Fi V (y))
Qinv Qsc Qdep Cox (Vg VFB 2 Fi V (y)) 2eN A SC (2 Fi V (y))
1 Q 2 Qinv Qsc dep Cox (Vg VFB 2 Fi V (y)) 2N A SC (2 Fi V (y)) nS (y) e e e e e Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 65
Charge sheet approximation
• Current density in the channel can be caused by diffusion and drift components
dV (y) kT dn J = qnμ qµ n 0 dy 0 q dy
• Current is simply given (integration over channel section)
W xi dV W xi kT dn I DS= dz qn 0 dx dz qµ0 dx 0 0 dy 0 0 q dy
xi dV xi kT dn I DS W qn0 dx W qµ0 dx 0 dy 0 q dy
There is a sign change because we want IDS>0 in –y direction Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 66
Charge sheet approximation
• The previous relation can be rewritten
dV xi kT d xi I DS=W0 qndx Wµ0 qndx dy 0 q dy 0 • If we remember that: xi Qinv q n(x, y)dx 0
dV kT dQ (V ) I = Wμ Q (V ) Wµ n • Current expression can be found DS 0 inv dy 0 q dy
• And so, by integrationg from y=0 to y=L and as current is independant of y:
L V (L) kT Qinv (L) I DS dy=W0 QinvdV dQinv 0 V (0) Q (0) q inv conduction diffusion Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 67
Charge sheet approximation
• If we want to derive basic expressions for long channel current in linear and saturation regions, we can neglect drift component
L V (L) VDS I DS dy W 0 Qinv (V )dV W0 Qinv (V )dV 0 V (0) 0 with Qinv Cox (Vg VFB 2 Fi V (y)) 2eN A SC (2 Fi V (y)) After few simple steps:
W V I C (V V 2 DS )V DS n L ox g FB Fi 2 DS 2 eN 3 3 2 sc A 2 2 (2 Fi V DS ) (2 Fi ) 3 C ox ‐2 ‐2 !! Cox is the oxide capacitance per surface unit (Fm ou Fcm )!! Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 68
Characteristics in the linear (triode) region
When VDS is small (VDS << 2Fi) , one can expand the previous equation into power series in VDS and keep only first order term:
W 4 sceN A Fi I DS nCox (VGS V fb 2 Fi )VDS L Cox W I C (V V )V DS n ox L GS T DS
We recognize threshold voltage VT. In the linear region, the MOSFET simply acts like a resistor modulated by the gate voltage Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 69
Characteristics in the linear (triode) region
• For larger values of VDS we have to keep second order term (quadratic term) and a good approximation of current is:
W m 2 I DS nCox (Vgs VT )VDS VDS L 2
eN / 4 C 3d with m 1 sc A Fi 1 dm 1 ox 1 Cox Cox Wm
Cdm is the bulk depletion capacitance in limit of strong inversion Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 70
Characteristics in the saturation region
• Previous equation is a parabole. Ids follows a parabolic curve with VDS until a maximun (or saturation) value is reached when VDS = Vdsat. (V V ) V V gs T D Dsat m
W (V V ) 2 I I C gs T DS Dsat n ox L 2m
In the case of thin oxide and low doping m can be reduced to 1 and Drain current yield the well known expression:
W 2 VDS I I C (V V ) DS Dsat n ox 2L gs T Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 71
Characteristics in the saturation region • Without any approximation (series expand,…), complete
expressions for IDSAT can be expressed as: 1 W 4 (eN ) 2 I µ C (V 2 )(V 2 2V 2V ) 12 (V V A sc Fi ) dsat n 6L ox Dsat Fi Dsat Fi gs FB Fi gs Fb Fi 3 C ox
sceN A 2 sceN A sc eN A VDsat Vgs VFB 2 Fi 2 2 (Vgs VFB 2 ) Cox Cox 2Cox
If we suppose high value for Cox (thin oxyde) and low doping level,
threshold voltage can be simplified as VT 2Fi VFB, and at the
same time we can rewrite Vdsat Vgs VT Vgs 2Fi VFB
VDsat Vgs VT W W I µ C (V V )2 µ C V 2 Dsat n 2L ox gs T n 2L ox Dsat Pr. Ph.Lorenzini From MOS Capacitor to CMOS inverter 72
Subthreshold characteristics – weak inversion region
• Three regimes: • Triode (Linear) • Saturation
• OFF state (if Vg < VT for nMOS) • Transition ON /OFF is not so sharp
• Weak inversion for fi MOSFET basics • Subthreshold current : « OFF » is not totally « OFF » • Previous analysis VGS