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MOSFET Capacitancescapacitances MOSFETMOSFET CapacitancesCapacitances 97.477 Lecture January 13, 2003 WhyWhy thisthis lecturelecture isis important.important. We will use MOSFETs to design our circuits. MOSFET capacitances tend to limit the frequency response of circuits. n In order to predict the circuit frequency response, we need to estimate the circuit capacitance. We may use the MOSFET capacitance to our advantage, by intentionally implementing capacitors using MOSFETs. EXAMPLEEXAMPLE PROBLEM:PROBLEM: DifferentialDifferential PairPair 3dB3dB--DownDown FrequencyFrequency Find the 3dB-down frequency (include the MOSFET capacitances). Ignore the sidewall capacitances. Assume the drain implant region length is 6mm and the width equals the device width. In order to solve this problem, we must find the total capacitance present at the output of the amplifier. The capacitance is a combination of the load capacitance and the MOSFET capacitances. ExtrinsicExtrinsic VersusVersus IntrinsicIntrinsic MOSFET parasitic capacitances are subdivided into two general categories: n extrinsic capacitances n intrinsic capacitances. Extrinsic capacitances are associated with regions of the transistor outside the dashed line. Intrinsic capacitances are all those capacitances located within the boxed region. B S G D p+ n+ n+ p-sub intrinsic region EXTRINSICEXTRINSIC CAPACITANCESCAPACITANCES Extrinsic capacitances are modeled by using lumped D capacitances, each of which C is associated with a region GD,e CSD,e of the transistor’s geometry. Intrinsic G S One capacitor is used Model CDB,e between each pair of transistor terminals, plus an CGS,e C additional capacitor between GB,e CSB,e the well and the bulk if the B W transistor is fabricated in a CBW,e well. ExtrinsicExtrinsic CapacitanceCapacitance TypesTypes Overlap capacitances that are mostly dependent on geometry. Junction capacitances that are dependent on geometry and on bias. GateGate OverlapOverlap CapacitancesCapacitances There is some overlap between the gate and the source and the gate and the drain. This overlap area gives rise to the gate overlap capacitances. Gate-Source/Drain Overlap Capacitances The overlap between the gate and the source and the gate and the drain gives rise to the gate overlap capacitances denoted by CGSO and CGDO for the gate-to-source overlap capacitance and the gate-to- drain overlap capacitance respectively. The overlap capacitances of the The overlap capacitances CGSO source and the drain are often and CGDO are proportional to modeled as linear parallel-plate the width, W, of the device and capacitors, since the high dopant the amount that the gate concentration in the source and overlaps the source and the drain regions and the gate material drain, typically denoted as “LD” implies that the resulting in SPICE parameter files. capacitance is largely bias independent. Gate-Source/Drain Overlap Capacitances For MOSFETs constructed with a lightly-doped-drain (LDD-MOSFET), the overlap capacitances can be highly bias dependent and therefore non-linear. For a treatment of overlap capacitances in LDD- MOSFETs, refer to Klein, P., “A Compact-Charge LDD-MOSFET Model”, IEEE Transactions on Electron Devices, vol. 44, pp. 1483-1490, Sep, 1997. For non-LDD MOSFETs, the gate-drain and gate- source overlap capacitances can be approximated by the expression CGSO = CGDO = W LD Cox, where Cox is the thin-oxide field-capacitance per unit area under the gate region. Gate-Source/Drain Overlap Capacitances It turns out that fringing field lines add significantly to the total capacitance. Estimates of the fringing field capacitances based on measurements are normally used. The gate-to-drain overlap capacitances are generally given as measured parameters in the MOSFET model files. There are values for NMOS MOSFETs and PMOS MOSFETs. The values are “per-width” values. GateGate--Source/DrainSource/Drain OverlapOverlap CapacitancesCapacitances FromFrom ModelModel FilesFiles .MODEL CMOSN NMOS LEVEL=3 PHI=0.700000 TOX=9.6000E-09 XJ=0.200000U TPG=1 + VTO=0.6684 DELTA=1.0700E+00 LD=4.2030E-08 KP=1.7748E-04 + UO=493.4 THETA=1.8120E-01 RSH=1.6680E+01 GAMMA=0.5382 + NSUB=1.1290E+17 NFS=7.1500E+11 VMAX=2.7900E+05 ETA=1.8690E-02 + KAPPA=1.6100E-01 CGDO=4.0920E-10 CGSO=4.0920E-10 + CGBO=3.7765E-10 CJ=5.9000E-04 MJ=0.76700 CJSW=2.0000E-11 + MJSW=0.71000 PB=0.9900000 .MODEL CMOSP PMOS LEVEL=3 PHI=0.700000 TOX=9.6000E-09 XJ=0.200000U TPG=-1 + VTO=-0.9352 DELTA=1.2380E-02 LD=5.2440E-08 KP=4.4927E-05 + UO=124.9 THETA=5.7490E-02 RSH=1.1660E+00 GAMMA=0.4551 + NSUB=8.0710E+16 NFS=5.9080E+11 VMAX=2.2960E+05 ETA=2.1930E-02 + KAPPA=9.3660E+00 CGDO=2.1260E-10 CGSO=2.1260E-10 + CGBO=3.6890E-10 CJ=9.3400E-04 MJ=0.48300 CJSW=2.5100E-10 + MJSW=0.21200 PB=0.930000 GateGate--toto--BulkBulk OverlapOverlap CapacitanceCapacitance There is a gate-to-bulk overlap capacitance caused by imperfect processing of the MOSFET. The parasitic gate-bulk capacitance, CjGB,e , is located in the overlap region between the gate and the substrate (or well) material outside the channel region. The parasitic extrinsic gate-bulk capacitance is extremely small in comparison to the other parasitic capacitances. In particular, it is negligible in comparison to the intrinsic gate-bulk capacitance. The parasitic extrinsic gate-bulk capacitance has little effect on the gate input impedance and is therefore often ignored. SourceSource--DrainDrain CapacitanceCapacitance Accurate models of short channel devices may include the capacitance that exists between the source and drain region of the MOSFET. The source-drain capacitance is denoted as CCSD,e. SourceSource--DrainDrain CapacitanceCapacitance Although the source-drain capacitance originates in the region normally associated with intrinsic capacitance, it is still referred to as an extrinsic capacitance. The value of this capacitance is difficult to calculate because its value is highly dependent upon the source and drain geometries. For longer channel devices, CSD,e is very small in comparison to the other extrinsic capacitances, and is therefore normally ignored. Refresher:Refresher: DiodeDiode CapacitanceCapacitance When a reverse voltage is applied to a PN junction , the holes in the p-region are attracted to the anode terminal and electrons in the n-region are attracted to the cathode terminal. The resulting region contains almost no carriers, and is called the depletion region. The depletion region acts similarly to the dielectric of a capacitor. The depletion region increases in width as the reverse voltage across it increases. If we imagine that the diode capacitance can be likened to a parallel plate capacitor, then as the plate spacing (i.e. the depletion region width) increases, the capacitance should decrease. Increasing the reverse bias voltage across the PN junction therefore decreases the diode capacitance. Source/DrainSource/Drain--BulkBulk JunctionJunction CapacitancesCapacitances At the source region there is a source-to- bulk junction capacitance, CjBS,e, and at the drain region there is a drain-to-bulk junction capacitance, CjBD,e. Source/DrainSource/Drain--BulkBulk JunctionJunction CapacitancesCapacitances The junction capacitances can be calculated by splitting the drain and source regions into a “side-wall” portion and a “bottom-wall” portion. n The capacitance associated with the side wall portion is found by multiplying the length of the side-wall perimeter (excluding the side contacting the channel) by the effective side- wall capacitance per unit length. n The capacitance for the bottom-wall portion is found by multiplying the area of the bottom- wall by the bottom-wall capacitance per unit area. WellWell--BulkBulk JunctionJunction CapacitanceCapacitance If the MOSFET is in a well, a well-to-bulk junction capacitance, CjBW,e, must be added. The well-bulk junction capacitance is calculated similarly to the source and drain junction capacitances, by dividing the total well-bulk junction capacitance into side-wall and bottom-wall components. If more than one transistor is placed in a well, the well-bulk junction capacitance should only be included once in the total model. JunctionJunction CapacitanceCapacitance EquationsEquations AA NoteNote onon EstimationEstimation If you are estimating a worst case delay, then you should generally use a worst case capacitance. Both the effective side-wall capacitance and the effective bottom-wall capacitance are bias dependent. The zero-bias side-wall capacitance and the per unit area zero-bias bottom-wall capacitance give the worst case (largest) capacitance. JunctionJunction CapacitancesCapacitances FromFrom ModelModel FilesFiles The junction capacitances can be calculated from parameters given in the MOSFET model files. There are values for NMOS MOSFETs and PMOS MOSFETs. .MODEL CMOSN NMOS LEVEL=3 PHI=0.700000 TOX=9.6000E-09 XJ=0.200000U TPG=1 + VTO=0.6684 DELTA=1.0700E+00 LD=4.2030E-08 KP=1.7748E-04 + UO=493.4 THETA=1.8120E-01 RSH=1.6680E+01 GAMMA=0.5382 + NSUB=1.1290E+17 NFS=7.1500E+11 VMAX=2.7900E+05 ETA=1.8690E-02 + KAPPA=1.6100E-01 CGDO=4.0920E-10 CGSO=4.0920E- 10 + CGBO=3.7765E-10 CJ=5.9000E-04 MJ=0.76700 CJSW=2.0000E-11 MJSW=0.71000 PB=0.9900000 .MODEL CMOSP PMOS LEVEL=3 PHI=0.700000 TOX=9.6000E-09 XJ=0.200000U TPG=-1 + VTO=-0.9352 DELTA=1.2380E-02 LD=5.2440E-08 KP=4.4927E-05 + UO=124.9 THETA=5.7490E-02 RSH=1.1660E+00 GAMMA=0.4551 + NSUB=8.0710E+16 NFS=5.9080E+11 VMAX=2.2960E+05 ETA=2.1930E-02 + KAPPA=9.3660E+00 CGDO=2.1260E-10 CGSO=2.1260E- 10 + CGBO=3.6890E-10 CJ=9.3400E-04 MJ=0.48300 CJSW=2.5100E-10 MJSW=0.21200 PB=0.930000 MODELMODEL EXAMPLEEXAMPLE .MODEL CMOSN NMOS LEVEL=3 PHI=0.700000 TOX=9.6000E-09 XJ=0.200000U TPG=1 + VTO=0.6684 DELTA=1.0700E+00 LD=4.2030E-08 KP=1.7748E-04 + UO=493.4 THETA=1.8120E-01 RSH=1.6680E+01 GAMMA=0.5382 + NSUB=1.1290E+17 NFS=7.1500E+11 VMAX=2.7900E+05 ETA=1.8690E-02 + KAPPA=1.6100E-01 CGDO=4.0920E-10 CGSO=4.0920E-10 + CGBO=3.7765E-10 CJ=5.9000E-04 MJ=0.76700 CJSW=2.0000E- 11 MJSW=0.71000 PB=0.9900000 CJSW´´perimeterCJ area Cj =+MJSWMJ éævvddöùéùæö ê11--ç÷úêúç÷ ëèff00øûëûèø.
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