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Power FINFET, a Novel Superjunction Lateral Power MOSFET

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Power FINFET, a Novel Superjunction Lateral Power MOSFET Power FINFET CMOSET, June 16, 2011 Power FINFET, a Novel Superjunction Power MOSFET Wai Tung Ng Smart Power Integration & Semiconductor Devices Research Group Department of Electrical and Computer Engineering University of Toronto Toronto, Ontario Canada, M5S 3G4 E-mail: [email protected] © 2011 University of Toronto 1 Power FINFET CMOSET, June 16, 2011 Outline ►Overview of Power Semiconductor Devices ►Design issues for Low Voltage Super-Junction Devices ►A Low Voltage Lateral Super-Junction FINFET Basic Idea of SJ-FINFET Structure Device Simulation Works Process Flow and IC Fabrication Experimental Results ►Summary University of Toronto 2 Power FINFET CMOSET, June 16, 2011 Applications of Smart Power ICs 100 Linear AC Regulator Motors 10 Automotive Switching Regulators 1 Fluorescent Ballast Digital 0.1 Telecom Bipolar Load Current (A) Load Current 0.01 linear Display 0.001 1 10 100 1000 Supply Voltage (V) University of Toronto 3 Power FINFET CMOSET, June 16, 2011 Worldwide Power Semiconductor Market $16B LV LV LV LV LV LV SWR SWR SWR SWR SWR SWR Source: M. Vukicevic, Data Processing Market to Dominate Power Semiconductor Market in 2007: Market Tracker, iSuppli Corp., Q1, 2007. University of Toronto 4 Power FINFET CMOSET, June 16, 2011 HVNMOS process (cont’d) ► Another example of CMOS compatible HV-CMOS with a variety of 40V devices with minimal process changes.HV n-EDMOS HV p-EDMOS Floating Source HV n-FSMOS source/body drain source source/bodydrain source source/body drain source/body SiO2 SiO2 SiO2 SiO2 SiO2 SiO2 SiO2 SiO2 SiO2 SiO2 p+ n+ n+ n+ p+ n+ p+ p+ p+ n+ p+ n+ n+ n+ p+ n-drift region p-drift region n-drift region p-well n-well p-well HV n-well Tox = 120Å p-substrate HV n-EDSMOS HV p-EDSMOS Low Voltage CMOS source drain body sourcedrain body source/body drain source/body SiO SiO SiO SiO SiO SiO SiO SiO SiO SiO SiO 2 n+ 2 2 n+ 2 p+ 2 p+ p+ 2 2 p+ 2 n+ 2 p+ n+ n+ 2 p+ p+ n+ 2 n-drift region n-drift region p-drift region p-drift region p-well n-well p-well n-well Tox = 780Å p-substrate University of Toronto 5 Power FINFET CMOSET, June 16, 2011 Lateral Super-Junction Power MOSFETs ► Super-Junction (SJ) power MOSFET is a promising devicetoachievealowRon,sp because the drift region is composed of heavily doped alternating n/p-pillars. However, conventional SJ structure is not very attractive for low voltage MOSFETs (<100V) due to the fact that the channel resistance becomes comparable to the drift region resistance at low voltage ratings. Gate Gate Source Drain Source Drain n p n- n+ n n+ p n p+ n+ p+ n+ p n- p Oxide Oxide UniversityConventional of Toronto LDMOSFET Superjunction LDMOSFET 6 Power FINFET CMOSET, June 16, 2011 Impact of the p/n pillar thickness Si Majority-Carrier Lateral Devices 1000 Si-limit z 100 SJ Devices (Lz = 10µm) cm2) y 10 Ω x ly p 1 n lx p d n d p 0.1 0.01 lz G Specific on-resistance (m 0.001 D S Vgs 0.0001 Vds 10 100 1000 Breakdown voltage (V) Fujihira, Fuji, JJAP, 1997 University of Toronto 7 Power FINFET CMOSET, June 16, 2011 Features of Super-Junction MOSFETs ► Drift region structure: n-drift region replaced by alternatively stacked, charge-coupled/heavily doped, n- and p- thin layers or pillars. ► Low specific on-resistance: Current flow only through the heavily doped parallel n-pillars. ► High breakdown voltage: requires full-depletion of SJ structures (a space-charged region, acting like a pure intrinsic layer); simply depends on drift region length; independent on dose. ► Charge counterbalance condition: controlling the doping of p- and n-type SJ layers according to the RESURF theory. ► Fabrication process: complicated and need precise process controls. University of Toronto 8 Power FINFET CMOSET, June 16, 2011 Lateral Power Devices – Performance 103 BV vs. Ron-sp Dual path double-resurf LDMOS[11] has been a SJ-LDMOS/SOS[13] 2 performance 10 Unbalanced SJ-LDMOS[12] matrix that many Toshiba-0.8μm Thick drift LDMOS CMOS/BESOI[4] 101 researchers ] 2 have been cm BCD5[7] chasing for Ω− 100 IDLDMOS[14] years. Si_Limit[8],[9] [ m -1 SJVDMOS[9] Ron-sp for power on,sp 10 μ Cool_MOS[9] R d=5 m LUDMOS[10] devices in the SOI Resurf[2]-[6] Motorola[3] low voltage 10-2 HexLDMOS range (<100V) Simple Resurf Data Source depends on 10-3 many factors. 10 100 1000 BV [ V ] University of Toronto dss 9 Power FINFET CMOSET, June 16, 2011 Main Issue: Low Voltage SJ-MOSFETs Chen et al, NUS, ISPSD, 2007 Sub-200V Si-limit Miura et al , NEC, ISPSD, 2005 University of Toronto 10 Power FINFET CMOSET, June 16, 2011 Basic Idea of SJ-FINFET Structure Drain Z Y Gate X Fill trench with p-pillar Source to form SJ device n-drift region SOI substrate ► Reduction of channel resistance ► Reduction of n-drift resistance SOI substrate ► E-field relaxation (i.e. higher BV) ► More efficient use of silicon University of Toronto 11 Power FINFET CMOSET, June 16, 2011 Proposed Lateral SJ-FINFET Structure Cross-section: A-A’ 0.6 0.3 0.3 Z Gate A’ B’ Poly-Si Drain 2 .5 W W side Y Wtop top C X C n T n Wn C’ Gox p n+ 0.035 p-body 1.0 Source n+ DTI S p W p p BOX n 2·Wn SJ unit-cell SJ unit-cell Lch Ldrift n+ Wside n+ Cross-section: B-B’ n Tepi p-body W A B top p+ 0.3 Wp Wn 0.3 0.3 0.3 BOX p-drift n-drift W DTI p-substrate 2 .5 side (S ) (S ) Compatibility with modern CMOS process is an p n 0.5 essential design consideration 0.5 BOX SJ unit-cell SJ unit-cell University of Toronto 12 Power FINFET CMOSET, June 16, 2011 Process Flow for the SJ-FINFET Structure (a) p-body implant (b) SJ-drift trench & implant (c) p-pillar diffusion (d) gate trench (e) n-doped poly-Si gate (f) n+ source implant (g) p+ contact opening (h) Al metallization University of Toronto 13 Power FINFET CMOSET, June 16, 2011 Parameters for 3D Simulations ► These Parameters Values Drift length, L (µm) 3 to 12 parameters drift n-drift width, Wn (µm) 0.6 -3 × 16 were also used n-drift doping conc., ND (cm )7.410 in the p-drift width, Wp (µm) 0.3 p-drift doping conc., N (cm-3) 7.4 to 9.8 × 1016 fabrication of A -3 × 17 p-body doping conc., Np-body (cm )5.0 10 the prototypes. -3 × 14 p-substrate doping conc., Nsub (cm )2.0 10 -3 × 20 n+ source/drain contact, Ns/d (cm )1.0 10 -3 × 19 p+ contact, Np+(cm )5.0 10 Gate oxide thickness, TGox (nm) 35 Top channel width, Wtop (µm) 0.6 Side channel width, Wside (µm) 2.0 and 3.0 Gate length, Lgate (µm) 1.0 Channel length, Lch (µm) 0.5 SOI thickness, Tepi (µm) 2.6 and 3.6 DTI depth (µm) 2.0 and 3.0 Buried oxide thickness, Tbox (µm) 2.0 University of Toronto 14 Power FINFET CMOSET, June 16, 2011 SJ-FINFET — Initial MESH Structure Drain SJ drift Gate DTI SJ unit-cell (w/o DTI & Gox) Source Drain p-body BOX p-sub channel p-drift Source SJ unit-cell (w/ DTI & Gox) p-body p-sub University of Toronto 15 Power FINFET CMOSET, June 16, 2011 Formation of the p/n pillars Implant After annealing @ Y = -3 B, 8e13 cm-2, 45 keV, ± 12° Boron P-pillar N-epi P-pillar N-epi Phosphorus University of Toronto 16 Power FINFET CMOSET, June 16, 2011 Formation of the n+ source/drain contacts P, 5e14 cm-2, 180 keV, ± 45° @ Y = -3 As, 9e14 cm-2, 200 keV, ± 45° N+ Phosphorus P-body N+ N-epi P-body Arsenic N-epi. Boron University of Toronto 17 Power FINFET CMOSET, June 16, 2011 SJ-FINFT — Device Simulation Results 400 1E-04 On-state @ Vg=10V @Ld=3.0μm 1E-05 @Ld=3.0μm 300 @Ld=3.5μm @Ld=3.5μm ) @Ld=4.0μm @Ld=4.0μm 2 1E-06 @Ld=4.5μm (A) @Ld=4.5μm 200 ds @Ld=5.0μm I @Ld=5.0μm (A/cm 1E-07 ds @Ld=6.0μm @Ld=6.0μm I Off-state 100 @Ld=8.0μm @Ld=8.0μm 1E-08 @Ld=12.0μm @Ld=12.0μm 0 1E-09 0 0.02 0.04 0.06 0.08 0.1 0 50 100 150 200 V (V) Vds (V) ds @ L = 3.0µm Wn = Wp = 0.3µm @ Vds=1V, Ldrift = 3.0µm drift 3 Np-drift = 9.5e16/cm N = 7.4e16/cm3 Vth ~1.7V n-drift University of Toronto 18 Power FINFET CMOSET, June 16, 2011 SJ-FINFT — Device Simulation Results (cont’d) 120 ) Other Published Data Wside / Ldrift = 2µm / 6µm 2 ∝ 1.9-2.0 ·cm BV 100 Ω Simulated conventional W / L = 3µm / 6µm lateral SJ-LDMOS side drift 1 80 BV (V) Simulated SJ-FINFET Wside / Ldrift = 2µm / 3µm 60 (О: 2µm and ∆: 3µm) W / L = 3µm / 3µm side drift Si-limit: ∝BV2.5 Specific on-resistance on-resistance (m Specific 40 0.1 -30 -25 -20 -15 -10 -5 0 90V 165V 10 100 Charge imbalance (Nn-Np)/Np (%) Breakdown voltage (V) University of Toronto 19 Power FINFET CMOSET, June 16, 2011 SJ-FINFT: Device Simulation Results SJ-FINFT — Device Simulation Results (cont’d) Relaxing the electric field at this point Gate @ Lgate=1µm, Lch=0.5µm, Ldrift=3µm achieves higher breakdown voltage Rsource Rch Rn-drift Rdrain 0.6 Source Gate n-drift Drain 4.5 0.5 4 SJ SOI-LDMOS 3.5 ) 2 0.4 3 source n-drift drain ·cm 2.5 V/cm) channel 5 Ω 0.3 2 (m Wside = 2µm (x10 1.5 0.2 field 1 on,sp W = 3µm E R side 0.1 0.5 SJ-FINFET 0 012345 0 Ldrift (μm) 012345 5 Y-distance (μm) Ec for Si ~ 5 x 10 V/cm, BV~(Ec·Ldrift) / 2 University of Toronto 20 Power FINFET CMOSET, June 16, 2011 Final Chip Layout & Die Image 50000µm (Mask=5cm, Die=1cm) , Die=1cm) Mask=5cm 50000µm ( Total 9 Mask Layers University of Toronto 21 Power FINFET CMOSET, June 16, 2011 Fabricated SJ-FINFETs: Optical & SEM Images Drain Drain Poly-Si: Top Gate Poly-Si: Top Gate Gate Gate P-pillar Trench Poly-Si: Trench Gate P-pillar Trench Poly-Si: Trench Gate Source Source Poly-Si: Trench Gate P-pillar Trench Source Drain Trench Trench Ldrift Poly-Si: Top Gate University of Toronto 22 Power FINFET CMOSET, June 16, 2011 SJ-FINFETs: After Al-Metallization Ldrift = 3.5µm Ldrift = 6.0µm Ldrift = 10.0µm Ldrift = 12.0µm University of Toronto 23 Power FINFET CMOSET, June 16, 2011 Measured Data: Transfer I-V Characteristics ► Ldrift=3.5µm, W=200µm, Tox = 35nm @ Vds = 0.1V 6E-03 5E-03 4E-03 (A) 3E-03 ds I The measured threshold 2E-03 voltage of the SJ-FINFET was approximately 1.7V 1E-03 Vth ~ 1.7V 0E+00 0123456789101112131415 Vgate (V) University of Toronto 24 Power FINFET CMOSET, June 16, 2011 Measured Data: Output I-V Characteristics ► The Ron,sp of the SJ-FINFET is approximately 30% smaller than that of the conventional SJ-LDMOSFET.
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