ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices Christopher Batten

School of Electrical and Computer Engineering Cornell University

http://www.csl.cornell.edu/courses/ece5745 Simple Transistor RC Model Simple Wire RC Model MOSFET Fabrication Part 1: ASIC Design Overview

PP Topic 1 Hardware Description MM Languages

Topic 4 Topic 6 Topic 5 Full-Custom Closing Automated Topic 8 Design the Design Testing and Verification Methodology Gap Methodologies

Topic 3 CMOS Circuits

Topic 7 Clocking, Power Distribution, Topic 2 Packaging, and I/O CMOS Devices

ECE 5745 T02: CMOS Devices 2 / 33 Simple Transistor RC Model Simple Wire RC Model MOSFET Fabrication Agenda

Simple Transistor RC Model

Simple Wire RC Model

CMOS Fabrication

ECE 5745 T02: CMOS Devices 3 / 33 • Simple Transistor RC Model • Simple Wire RC Model MOSFET Fabrication Fundamental Building Block: MOSFET Transistor

IBM Power 7 1.2 Billion Transistors

ECE 5745 T02: CMOS Devices 4 / 33 • Simple Transistor RC Model • Simple Wire RC Model MOSFET Fabrication “Metal”-Oxide-Semiconductor Structure

Polysilicon Gate Silicon Dioxide Insulator p-Type Silicon Body (doped to create mobile majority carriers, positively charged holes)

Accumulation: Battery puts negative charge on gate, attracts positively-charged majority carriers in p-type silicon body

Adapted from [Weste’11]

ECE 5745 T02: CMOS Devices 5 / 33 • Simple Transistor RC Model • Simple Wire RC Model MOSFET Fabrication “Metal”-Oxide-Semiconductor Structure

Polysilicon Gate Silicon Dioxide Insulator p-Type Silicon Body (doped to create mobile majority carriers, positively charged holes)

Depletion Region

Depletion: Battery puts positive charge on gate, pushes positively-charged carriers away from surface, uncovers some negatively-charged dopant atoms in substrate

Adapted from [Weste’11]

ECE 5745 T02: CMOS Devices 5 / 33 • Simple Transistor RC Model • Simple Wire RC Model MOSFET Fabrication “Metal”-Oxide-Semiconductor Structure

Polysilicon Gate Silicon Dioxide Insulator p-Type Silicon Body (doped to create mobile majority carriers, positively charged holes)

Depletion Region Inversion Region

Inversion: Battery puts more positive charge on gate, instead of pushing holes even further away, draws free electrons to surface. Where did electrons come from? No electron donors in p-type silicon; electron/hole pairs always being generated by thermal excitation – electrons caught by efield in depletion region Adapted from [Weste’11]

ECE 5745 T02: CMOS Devices 5 / 33 • Simple Transistor RC Model • Simple Wire RC Model MOSFET Fabrication NMOS Transistor

Cutoff: Vgs = 0V, Vds can be 0V or Vdd Linear: Vgs = Vdd, Vds = 0V No Channel, Ids = 0 Channel Formed, Ids increases with Vds

0 < Vds < Vgs - Vt Vds > Vgs - Vt

Linear: Vgs = Vdd, Vds = Vdd Saturation: Channel Pinched Off, Channel Formed, Ids increases with Vds Ids independent of Vds Adapted from [Weste’11]

ECE 5745 T02: CMOS Devices 6 / 33 • Simple Transistor RC Model • Simple Wire RC Model MOSFET Fabrication Simple NMOS Circuit

Vds d

Vgs 0 < VVdsds <> VVgsgs -- VtVt s Saturation:Cutoff:Linear: No ChannelChannel Channel, PinchedFormed Ids = 0 Off, IIdsds independentincreases with of VVdsds

Vt Vgs =Vdd Vds =Vdd Vgs log Id Id V Id Vds

Vds Vgs Vgs time

ECE 5745 T02: CMOS Devices 7 / 33 • Simple Transistor RC Model • Simple Wire RC Model MOSFET Fabrication Key Qualitative Characteristics of MOSFET Transistors

I Vt sets when transistor turns on, impacts leakage current Cd Reff I Id ∝ µ × (W /L) Key qualitative characteristicsµ > µ =of⇒ R < R Cg I n p N,eff P,eff Cd MOSFET transistors I Cg ∝ (W × L)

I Cd ∝ W

Width I ↑ W = ↓ Reff = ↑ Id = ↑ Vin Vout Cd , Cg

Cg I ↑ L = ↑ Reff C=d ↓ Id = ↑ Cg Reff

Length

• ThresholdECE 5745 voltage sets when transisT02:tor CMOSturns Devices on – also impacts leakage 8 / 33

• IDS is proportional to mobility x (W/L)

• NMOS mobility > PMOS mobility => ReffN < ReffP (assume mobility ratio is 2)

• Increase W = Increase I = Decrease Reff

• Increase L = Decrease I = Increase Reff

• Cg proportional to ( W x L ) and Cd proportional to W

6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 7 Simple Transistor RC Model • Simple Wire RC Model • MOSFET Fabrication Agenda

Simple Transistor RC Model

Simple Wire RC Model

CMOS Fabrication

ECE 5745 T02: CMOS Devices 9 / 33 Simple Transistor RC Model • Simple Wire RC Model • MOSFET Fabrication WireWire ResistanceResistance

length resistivity resistance Height Length height width

bulk aluminum 2.8x10-8 -m -8 Width bulk copper 1.7x10 -m bulk silver 1.6x10-8 -m

Thickness fixed in given manufacturing process Resistances quoted as /square TSMC 0.18m 6 Aluminum metal layers M1-5 0.08 /square (0.5 m x 1mm wire = 160 ) M6 0.03 /square (0.5 m x 1mm wire = 60 )

Rsq = resistivity / height resistance = Rsq × ( length / width ) Adapted from [Terman’02]

ECE 5745 T02: CMOS Devices 10 / 33 6.371 – Fall 2002 10/2/02 L09 – Wires 4 Simple Transistor RC Model • Simple Wire RC Model • MOSFET Fabrication WireWire Capacitance Capacitance

H2 2

D12 12 W2

H1 1

D1 W1 S1 DD1

Capacitance depends on geometry of surrounding wires and relative permittivity, r,of dielectric

– silicon dioxide, SiO2 r = 3.9 – silicon flouride, SiOF r = 3.1 TM – SiLK polymer, r = 2.6 Can have different materials between wires and betweenAdapted from [Terman’02] ECE 5745 layers, and also differentT02: CMOSmaterials Devices on higher layers 11 / 33

6.371 – Fall 2002 10/2/02 L09 – Wires 7 Distributed RC wire model gives accurate Simple Transistor RC Model • Simple Wire RC Model • MOSFET Fabrication resultsKey but Qualitative is computationally Characteristics of Wiresexpensive

R driver R1 R2 RN

Lumped model can provideCload a C C C quick1 reasonable2 approximationN

UseBecause Penfield-Rubenstein both wire equation to find delay resistance and wire Rdriver R N w capacitance increase with j i Cload length, wire delayDelay grows R j Ci quadratically with length i j 1 Cw/2 Cw/2 How does the delay scale with longer wires?

–Wire delay increases quadraticallyCw C w Delay Rdriver Rdriver R w Cload –Edge rate also degrades quadratically2 2 ECE 5745 T02: CMOS Devices 12 / 33

6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 31 Rw is lumped resistance of the wire

Cw is lumped capacitance

Partition half of Cw at each end

6.375 Spring 2006 • L04 CMOS Transistors, Gates, and Wires • 32 Simple Transistor RC Model Simple Wire RC Model • MOSFET Fabrication • Agenda

Simple Transistor RC Model

Simple Wire RC Model

CMOS Fabrication

ECE 5745 T02: CMOS Devices 13 / 33 IC Fabrication and Layout Representation

“Mask” drawings sent to the fabrication facility to make the chips.

Simple Transistor RC Model Simple Wire RC Model • MOSFET Fabrication • Mask Set for NMOS Transistor (circa 1986) Mask set for an n-Fet (circa 1986) Vg = 0V Vd = 1V Vs = 0V Masks #1: n+ diffusion I ≈ nA dielectric n+ n+ #2: poly (gate) #3: diff contact p- #4: metal

Top-down view: Layers to do p-Fet not shown. Modern processes have 6 to 10 metal layers (or more)

(in 1986:38 2).

Lecture 02, Introduction 1 CS250,Adapted UC Berkeley from Fall ‘11 [Asanovic’11]

ECE 5745 T02: CMOS Devices 14 / 33 Simple Transistor RC Model Simple Wire RC Model • MOSFET Fabrication • Design Rules for Masks (circa 1986) “Design rules” for masks, 1986 ... Poly Minimum gate length. Metal rules: overhang. So that the source and Contact So that if drain depletion regions separation from masks are do not meet! channel, one misaligned, fixed contact channel length size, overlap rules doesn’t with metal, etc ... short out.

#1: n+ diffusion #3: diff contact #2: poly (gate) #4: metal Lecture 02, Introduction 1 CS250,Adapted UC Berkeley from Fall ‘11 [Asanovic’11]

ECE 5745 T02: CMOS Devices 15 / 33

Fabrication

40

Lecture 02, Introduction 1 CS250, UC Berkeley Fall ‘11 Mask set for an n-Fet ... Vg = 1V Vd Vd = 1V Vs = 0V

I ≈ μA dielectric n+ n+ Vg Ids

p- Vs Masks Top-down view: #1: n+ diffusion #2: poly (gate) #3: diff contact #4: metal How does a fab use a mask41 set to make an IC?

Lecture 02, Introduction 1 CS250, UC Berkeley Fall ‘11

Simple Transistor RC Model Simple Wire RC Model • MOSFET Fabrication • Start With an Un-Doped Wafer Start with an un-doped wafer ... UV hardens exposed resist. A wafer wash leaves only hard resist.

Steps #1: dope wafer p- oxide #2: grow gate oxide p- #3: deposit undoped polysilicon #4: spin on photoresist

#5: place positive poly mask and expose with UV.

Lecture 02, Introduction 1 CS250,Adapted UC Berkeley from Fall ‘11 [Asanovic’11]

ECE 5745 T02: CMOS Devices 16 / 33 Simple Transistor RC Model Simple Wire RC Model • MOSFET Fabrication • Wet Etch to Remove Unmasked Regions Wet etch to remove unmasked ... HF acid etches through poly and oxide, but not hardened resist.

oxide

p-

oxide After etch and resist removal p-

Lecture 02, Introduction 1 CS250,Adapted UC Berkeley from Fall ‘11 [Asanovic’11]

ECE 5745 T02: CMOS Devices 17 / 33

Use diffusion mask to implant n-type accelerated donor atoms

Notice how donor oxide n+ n+ atoms are blocked by gate and do not p- enter channel. Thus, the channel is “self-aligned”, precise mask alignment is not needed!

44

Lecture 02, Introduction 1 CS250, UC Berkeley Fall ‘11 Wet etch to remove unmasked ... HF acid etches through poly and oxide, but not hardened resist.

oxide

p-

oxide After etch and resist removal p- 43

Lecture 02, Introduction 1 CS250, UC Berkeley Fall ‘11

Simple Transistor RC Model Simple Wire RC Model • MOSFET Fabrication • Use Diffusion Mask to Implant N-Type Use diffusion mask to implant n-type accelerated donor atoms

Notice how donor oxide n+ n+ atoms are blocked by gate and do not p- enter channel. Thus, the channel is “self-aligned”, precise mask alignment is not needed!

Lecture 02, Introduction 1 AdaptedCS250, UC Berkeley from Fall [Asanovic’11]‘11

ECE 5745 T02: CMOS Devices 18 / 33 Simple Transistor RC Model Simple Wire RC Model • MOSFET Fabrication • Metallization Completes Device Metallization completes device

Grow a thick oxide oxide on top n+ n+ of the wafer. p-

Mask and etch oxide to make contact n+ n+ holes p-

Put a layer of metal on chip. oxide Be sure to fill in n+ n+ the holes! p-

Lecture 02, Introduction 1 CS250, UC Berkeley Fall ‘11 Adapted from [Asanovic’11]

ECE 5745 T02: CMOS Devices 19 / 33

Final product ... Vd Vs “The planar process”

oxide n+ n+ Jean Hoerni, Fairchild p- Semiconductor 1958 Top-down view:

46

Lecture 02, Introduction 1 CS250, UC Berkeley Fall ‘11 Metallization completes device

Grow a thick oxide oxide on top n+ n+ of the wafer. p-

Mask and etch oxide to make contact n+ n+ holes p-

Put a layer of metal on chip. oxide Be sure to fill in n+ n+ the holes!45 p-

Lecture 02, Introduction 1 CS250, UC Berkeley Fall ‘11

Simple Transistor RC Model Simple Wire RC Model • MOSFET Fabrication • Final NMOS Transistor Final product ... Vd Vs “The planar process”

oxide n+ n+ Jean Hoerni, Fairchild p- Semiconductor 1958 Top-down view:

46

Lecture 02, Introduction 1 AdaptedCS250, UC Berkeley from Fall [Asanovic’11]‘11

ECE 5745 T02: CMOS Devices 20 / 33 p-channel Transistors

47

Lecture 02, Introduction 1 CS250, UC Berkeley Fall ‘11

Simple Transistor RC Model Simple Wire RC Model • MOSFET Fabrication • PMOS Transistor is Dual of NMOS Transistor p-Fet: Change polarity of everything Vg = 0V Vs Vwell = Vs = 1V Vd = 0V I ≈ μA dielectric p+ p+ Vg Isd n-well p- Vd

New “n-well” mask “Mobility” of holes is slower than electrons.

p-Fets drive less current than n- Fets, all else being equal

Lecture 02, Introduction 1 Adapted from [Asanovic’11]

ECE 5745 T02: CMOS Devices 21 / 33 Simple Transistor RC Model Simple Wire RC Model • MOSFET Fabrication • Single- and Triple-Well Processes

Adapted from [Weste’11]

ECE 5745 T02: CMOS Devices 22 / 33 Simple Transistor RC Model Simple Wire RC Model • MOSFET Fabrication • Local Interconnect

IBM 6-Transistor SRAM Cell

Adapted from [Weste’11]

ECE 5745 T02: CMOS Devices 23 / 33 Simple Transistor RC Model Simple Wire RC Model • MOSFET Fabrication • Intel Metal Stacks: 90nm and 45nm

Adapted from [Weste’11]

ECE 5745 T02: CMOS Devices 24 / 33 Simple Transistor RC Model Simple Wire RC Model • MOSFET Fabrication • Intel Metal Stacks: 45nm with M9 and I/O Bump

Adapted from [Weste’11]

ECE 5745 T02: CMOS Devices 25 / 33 Simple Transistor RC Model Simple Wire RC Model • MOSFET Fabrication • Intel Metal Layer Dimensions in 45nm

Layer t (nm) w (nm) s (nm) pitch (nm) M9 7µm 17.5µm 13µm 30.5µm M8 720 400 410 810 M7 504 280 280 560 M6 324 180 180 360 M5 252 140 140 280 M4 216 120 120 240 M3 144 80 80 160 M2 144 80 80 160 M1 144 80 80 160

Adapted from [Weste’11]

ECE 5745 T02: CMOS Devices 26 / 33 Simple Transistor RC Model Simple Wire RC Model • MOSFET Fabrication • IBM Metal Stacks

IBM 11-layer Copper Metal Stack

IBM 6-layer Copper Metal Stack

Adapted from [Weste’11]

ECE 5745 T02: CMOS Devices 27 / 33 Simple Transistor RC Model Simple Wire RC Model • MOSFET Fabrication • Bulk vs. Silicon-on-Insulator Processing

I Eliminates parasitic capacitance between source/drain and the body → lower energy, higher performance

I Lower subthreshold leakage, but threshold voltage varies over time Bulk versus ISIO10–15% Processing increase in total manufacturing cost due to substrate cost ‣ “Silicon on Insulator”

‣ Lower parasitic capacitance -> lower energy, higher-performance Adapted from [Asanovic’11,Weste’11] ‣ Also used for “radiation hard”ECE 5745 application (space craft)T02: - CMOSsaphhire Devices 28 / 33 instead of Oxide. ‣ 10 - 15% increase in total manufacturing cost due to substrate cost.

Lecture 02, Introduction 1 49 CS250, UC Berkeley Fall ‘11

Lithography

‣ Optical proximity correction (OPC) is an enhancement technique commonly used to compensate for image errors due to diffraction or process effects.

desired (drawn)

modified mask ‣ Current state-of-the-art photolithography tools use deep ultraviolet (DUV) exposure light with wavelengths of 248 and 193 nm, which allow minimum feature sizes down to 50 nm.

Lecture 02, Introduction 1 50 CS250, UC Berkeley Fall ‘11 Bulk versus SIO Processing

‣ “Silicon on Insulator”

‣ Lower parasitic capacitance -> lower energy, higher-performance ‣ Also used for “radiation hard” application (space craft) - saphhire instead of Oxide. ‣ 10 - 15% increase in total manufacturing cost due to substrate cost. Simple Transistor RC Model Simple Wire RC Model • MOSFET Fabrication • Lithography Lecture 02, Introduction 1 49 CS250, UC Berkeley Fall ‘11

Lithography

‣ Optical proximity correction (OPC) is an enhancement

technique commonly used to Mask of SEM compensate for image errors due to diffraction or process effects.

desired (drawn) I Resolution of patterns far exceeds wavelength modified mask ‣ Current state-of-the-art of light used for exposure whichphotolithography is usually tools use deep ultraviolet (DUV) exposure 193 nm generated with anlight argon with fluoride wavelengths laser of 248 and 193 nm, which allow minimum feature I Sophisticated tricks used tosizes pattern down to 10–10050 nm. µm features including immersion lithography, optical proximity correction,Lecture 02, Introduction double 1 patterning 50 CS250, UC Berkeley Fall ‘11 Adapted from [Asanovic’11,Weste’11]

ECE 5745 T02: CMOS Devices 29 / 33 Simple Transistor RC Model Simple Wire RC Model • MOSFET Fabrication • Processing Enhancements

I High-K Dieletrics and Metal Gates – Replacing silicon dioxide gate dielectric with a high-K material allows increased vertical electric field without increasing gate leakage

I Strained Silicon – Layer of silicon in which silicon atoms are stretched beyond their normal interatomic distance leading to better mobility

I Gate Engineering – Multiple transistor designs with different threshold voltages to allow optimization of delay or power

Adapted from [Asanovic’11,Weste’11]

ECE 5745 T02: CMOS Devices 30 / 33 Simple Transistor RC Model Simple Wire RC Model • MOSFET Fabrication • FinFET Transistors

I Small footprint, but good control of the gate due to using the vertical dimension

I Intel is using FinFETs in 22 nm process

Adapted from [Weste’11]

ECE 5745 T02: CMOS Devices 31 / 33 Simple Transistor RC Model Simple Wire RC Model MOSFET Fabrication Take-Away Points

I Although a basic understanding of devices and fabrication is important for understanding technology constraints, mostly in this course we will focus on first-order RC models of CMOS logic, state, and interconnect I In the next topic of this part of the course, we will briefly introduce CMOS circuits using these devices . Combinational Logic: static CMOS, pass-transistor, tri-state buffers . Sequential State: latches, flip-flops

I In the next part of the course, we will explore the details of how to quantitatively evaluate the cycle time, area, and energy of these digital circuits

ECE 5745 T02: CMOS Devices 32 / 33 Simple Transistor RC Model Simple Wire RC Model MOSFET Fabrication Acknowledgments

I [Weste’11] N. Weste and D. Harris, “CMOS VLSI Design: A Circuits and Systems Perspective,” 4th ed, Addison Wesley, 2011.

I [Terman’02] C. Terman and K. Asanovic,´ “CMOS Technology,” and “Wires, ” MIT 6.371 Introduction to VLSI Systems, Lectures, 2002.

I [Asanovic’11] K. Asanovic,´ J. Wawrzynek, and J. Lazzaro, “Introduction,” UC Berkeley CS 250 VLSI Systems Design, Lecture, 2011.

ECE 5745 T02: CMOS Devices 33 / 33