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Strained silicon
Strained Silicon Devices M. Reiche , O. Moutanabbir , J. Hoentschel , U
Strained Silicon Layer in CMOS Technology
Electron Effective Mobility in Strained Si/Si1-Xgex MOS Devices Using Monte Carlo Simulation
Sige CVD, Fundamentals and Device Applications
Challenges and Innovations in Nano‐CMOS Transistor Scaling
Elastic Strain Engineering in Silicon and Silicon-Germanium Nanomembranes
MOSFET Channel Engineering Using Strained Si, Sige, and Ge Channels
Thin Film Deposition
Chasing Moore's Law with 90-Nm
Characterization and Fabrication of 90Nm Strained Silicon PMOS Using TCAD
Performance Evaluation of Strained Si/Sige N-Channel Mosfet
Stress Modeling of Nanoscale Mosfet
Stretching Silicon's Lifespan
Monolithic Heteroepitaxial Integration of III-V Semiconductor Lasers on Si Substrates
4A-2 Strained Si Channel Mosfets with Embedded Silicon Carbon
A Logic Nanotechnology Featuring Strained-Silicon Scott E
(12) United States Patent (10) Patent N0.: US 7,326,969 B1 Horch (45) Date of Patent: Feb
Strained Silicon T Echnology
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A 90Nm High Volume Manufacturing Logic Technology Featuring Novel 45Nm Gate Length Strained Silicon CMOS Transistors T
A 90 Nm Logic Technology Featuring 50Nm Strained Silicon Channel Transistors, 7 Layers of Cu Interconnects, Low K ILD, and 1 Um2 SRAM Cell S
Silicon Takes the Strain
Electrical and Thermal Properties of Strained Silicon Mosfets
Strained-Silicon Transistors with Silicon-Carbon Source/Drain H-1-2
Design and Simulation of Strained-Si/Strained-Sige Dual Channel Hetero-Structure Mosfets
The Amazing Vanishing Transistor
1406HI01 IBM HIGHLIGHTS, 2000-2006 Year Pages 2000 3-11
Strain Mapping of Tensiley Strained Silicon Transistors with Embedded
Characterization of Strained Silicon MOSFET Using Semiconductor TCAD Tools
Electrical and Material Properties of Strained Silicon/Relaxed Silicon
Beyond the Conventional Transistor
Introducing 90-Nm Technology in Microwind3 Etienne Sicard