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Sige CVD, Fundamentals and Device Applications SiGeSiGe CVD,CVD, fundamentalsfundamentals andand devicedevice applicationsapplications DrDr DerekDerek HoughtonHoughton AixtronAixtron IncInc ICPS,ICPS, FlagstaffFlagstaff JulyJuly 20042004 . OVERVIEW 1.1. Introduction Introduction 2.2. SiGe SiGe Market Market SurveySurvey 3.3. Fundamentals Fundamentals ofof SiGeSiGe CVDCVD 4.4. CVD CVD EquipmentEquipment forfor SiGeSiGe 5.5. Device Device aplicationsaplications andand commercializationcommercialization 6.6. SiGe SiGe materialsmaterials engineering,engineering, metrologymetrology 7.7. Summary Summary and and DiscussionDiscussion SiGe’s Market Opportunity... Si CMOS/BJTs SiGe HBTs/CMOS? III-V FETs/HBTs Automotive Road Collision Pricing Avoidance Navigation/Areospace GPS x-band Radar Communications GSM DCS ISM DECT FRA WLAN DTH WLAN OC-48 DBS FRA G-Ethernet OC-192 LMDS 0.1 0.2 0.5 1 2 5 10 20 50 100 Frequency (GHz) SiGe HBT device structure and process description KeyKey figures figures of of SiGe SiGe HBT HBT process process •• SiGe SiGe BiCMOSBiCMOS uses uses SiGeSiGe HBT HBT ++ SiSi CMOSCMOS •• SiGe SiGe HBT HBT showsshows samesame processprocess asas SiSi BT BT withwith exceptionexception ofof 30-8030-80 nmnm thinthin SiGeSiGe base base layerlayer (Ge(Ge <25%) <25%) •• Growth Growth ratesrates usedused areare aboutabout 3030 nm/minnm/min (~(~ 22 minmin forfor basebase layer)layer) •• Typically, Typically, samesame LPCVDLPCVD growthgrowth chamberschambers cancan depositedeposite both both SiSi and and SiGeSiGe layers layers Only difference: Base SiGe replaces Silicon •• Depending Depending onon SiGeSiGe HBT HBT process,process, basebase layerlayer depositeddeposited eithereither usingusing selectiveselective oror differentialdifferential epitaxyepitaxy SiGe‘s main market is telecommunication (wireless and datacom) SiGe IC forecast by market, 2000 to 2005, in mil. US$ CommentsComments Industrial •• SiGeSiGe viable viable alternativealternative toto GaAsGaAs 1800 Computer Consumer •• Main Main marketsmarkets beingbeing targeted:targeted: 1600 Communications •• Cellular Cellular // CordlessCordless // WLANWLAN 1400 •FO-Datacom•FO-Datacom CAGR=+125%CAGR=+125% 1200 (MUX/DEMUX)(MUX/DEMUX) 1000 •• PC PC interfaceinterface cardscards // LANLAN 800 600 •• Future Future trends:trends: •• integrated integrated lowlow powerpower RF-RF- SiGe [Mio. US$] IC Market 400 frontfront endend ofof mostmost handsetshandsets •• First First choicechoice forfor up/downup/down 200 conversionconversion inin tuners/tuners/ transceiverstransceivers 0 •• will will dominatedominate 4040 GbpsGbps 2000 2001 2002 2003 2004 2005 YEAR Source: Strategies Unlimited, 1999 CAGR: Compound Average Growth Rate Strained Si: prototypes from Intel, IBM & UMC demonstrated Almost all large Si-CMOS manufacturers are presenting cross sectional pictures of CMOS transistors (with gate lengths between 65 and 90 nm) which use Strained-Si technology. Intel and IBM use their own technology, whereas UMC is Amberwave’s licensee Strained-Si HeteroWafer® technology: process and actual status ActualActual statusstatus Strained-SiStrained-Si process process •• Strained Strained SiSi technologytechnology enablesenables improvementimprovement inin CMOSCMOS performanceperformance andand functionalityfunctionality viavia replacementreplacement ofof thethe bulk,bulk, cubic-crystalcubic-crystal SiSi substratesubstrate withwith aa SiSi substratesubstrate thatthat containscontains aa tetragonallytetragonally distorted,distorted, biaxiallybiaxially strainedstrained SiSi thinthin filmfilm atat thethe surfacesurface •• Different Different typestypes ofof processesprocesses developeddeveloped andand patentedpatented byby thethe mainmain players:players: AmberwaveAmberwave (IQE)(IQE) -- AIXTRON, AIXTRON, IBM,ToshibaIBM,Toshiba && IntelIntel •• First First demosdemos ofof perfectperfect workingworking 5252 MbitMbit SRAMsSRAMs with with 9090 nmnm CMOSCMOS devicesdevices onon 300300 mmmm waferswafers availableavailable fromfrom Intel.Intel. Ramp-upRamp-up ofof PentiumPentium 44 productionproduction withwith Str.-SiStr.-Si planned planned forfor 2H/20032H/2003 !! •• Process Process andand substratesubstrate costscosts stillstill notnot 100%100% fixed.fixed. PricePrice expectationsexpectations forfor substratesubstrate fromfrom ICIC manufacturersmanufacturers stillstill unknownunknown Strained Si process of Amberwave: One of the Strained Si pioneers •Typically,•Typically, 22 toto 44 µmµm thickthick gradedgraded SiGeSiGe buffer buffer layer,layer, followedfollowed byby thinthin (<20(<20 nm)nm) strainedstrained SiSi channel channel layerlayer •Depending•Depending onon substratesubstrate GeGe concentration, concentration, clearclear mobilitymobility andand transistortransistor currentcurrent drivedrive improvementimprovement •• Through Through Amberwave’sAmberwave’s proprietaryproprietary chemical-mechanicalchemical-mechanical polishingpolishing (CMP)(CMP) intermediateintermediate process,process, SiGeSiGe bufferbuffer layerlayer surfacesurface roughnessroughness isis eliminatedeliminated beforebefore SiSi layerlayer deposi-tion,deposi-tion, resultingresulting inin samesame qualityquality comparedcompared toto bulkbulk SiSi waferswafers Strained Silicon CMOS technology *SiGe deposited selectively, Intel Pentium IV in production Strained silicon mainly addresses high-end digital CMOS markets Digital electronic market forecast and expected strained Si penetration, 2003 to 2007, in mil. US$ 100000 CAGR*=CAGR*= 12.5%12.5% Si FPGAs 80000 Si Digital Signal Processors (DSPs) 60000 Si Micro-controllers (MCUs) 40000 Si Microprocessors (MPUs) 20000 AssumptionsAssumptions Digital CMOS ElectronicMarket [Mio. US$] 0 •• Main Main applicationapplication willwill bebe high-endhigh-end 100000 2003 2004 2005 2006 2007 MicroprocessorsMicroprocessors likelike IBM‘sIBM‘s Source: VLSI Research, 2002 YEAR Power-PC,Power-PC, SUN‘sSUN‘s Sparc,Sparc, AMD‘sAMD‘s 80000 Athlon,Athlon, IntelIntel PentiumPentium // Itanium.Itanium. 60000 •• Main Main marketsmarkets beingbeing targeted:targeted: PCs,PCs, workstations,workstations, gamegame CAGR*=CAGR*= >200%>200% consoles, other internet 40000 consoles, other internet appliancesappliances 20000 •• Future Future trends:trends: StrainedStrained SiSi penetratespenetrates 3G/WLAN3G/WLAN wirelesswireless 0 applicationsapplications (DSPs/MCUs)(DSPs/MCUs) 2003 2004 2005 2006 2007 Strained Si US$] based CMOS Market [Mio. YEAR CAGR: Compound Average Growth Rate Source: AIXTRON estimates Effect of air exposure prior to HF passivation ) -3 10 21 RCA + 4 hours in air + HF dip RCA + HF dip 1020 1019 Oxygen 1018 Carbon 1017 0 500 1000 1500 2000 2500 3000 3500 Carbon and Oxygen concentrations (cm Carbon and Oxygen Depth (Å) Partial pressure for oxygen incorporation from H2O and O2 AIXTRON‘s flexible epi systems for Strained Si / SiGe Tricent® vs. Multiwafer Reactor® Tricent SiGe Cluster Tool: 150, 200 or 300 AIX 2600G3: up to 7x150 or 3x200 mm mm SiGe UHVCVD Quartz tube SiH4 -3 P~ 10 mbar GeH4 Tg<600C B2H6 PH3 wafers molecular flow uniform growth sticking coefficients~10-3 UHV initial conditions, P~10-9 m bar hydrogen terminated Si wafers at start Hot wall UHVCVD Batch tool Uniform Gas Distribution by AIXTRON´s Closed Coupled Showerhead Horizontal Quarz Tube Reactor Closed Coupled Showerhead Reactor Growth Rate Growth Rate Distance to gas inlet Distance to gas inlet SiGe Tricent® Dual-Chamber Showerhead (pat. pend.) Showerhead Detail Water-Cooled Reactor Lid N2/H2 Gas Mix Showerhead Process Chamber TLid TSH TSubstr Coated Graphite Wafer Susceptor Temperature Control Concept SiGe Tricent® Unique CVD chamber features developed beyond industry standards ..ShowerheadShowerhead ..TemperatureTemperature controlcontrol ® Tricent Customer Process Support Clean Room Wall Process platform for HBTs, HFETs and BiCMOS - pure Silicon Growth - differential SiGe:C growth - selective SiGe:C growth - SiGe on SOI Cassette Station Temp Process Gas Sources 550-680°C SiGe:C SiH4 + GeH4 + SiCH6 650-750°C SiGe SiH4 + GeH4 730-800°C sel. SiGe SiH2Cl2 + HCl + GeH4 800-900°C SEG SiH2Cl2 + HCl SiGe HBT in a BiCMOS flow Metallisation Polysilicon Emitter Spacers Base SiGe LOCOS n+ EpitaxialLayer N N + MOS HBT XTEM of Si deposition on Si/oxide HBT base structure SIMS profiling 15 10 19 SIMS analysis (cameca) CVD-197 Germanium conc. (%) Germanium conc. ) 18 -3 10 10 10 17 Ge 5 Boron conc. (cm 10 16 10 15 0 0 500 1000 1500 Depth (Å) Gummel Plot, npn HBT -3 10 Ic Ib 10 -5 A = 0.6 x 1.2 micron 2 E V = 0 (A) -7 10 CB B I , C I -9 10 NPN11A, CVD-140 -11 10 Triangular SiGe base profile V (V) BE -13 10 0 0.2 0.4 0.6 0.8 1 1.2 1.4 CMOS transistor Selective SiGe Epitaxy DC Houghton J.Appl.Phys.1991 Strained Silicon on Strained Silicon on graded SiGe buffer SOI wafer by layer transfer Amberwave SOITEC Ge% Strained Si Strained Si SiGe stack SiGe grade Si substrate Si substrate DCD x ray diffraction SIMS profileStrained Si – Graded SiGe Buffer Cs Cascade Scientific 12/04/2003 1E+23 1E+05 Sample A3 29Si+30Si-> 1E+22 70Ge interface 1E+04 1E+21 SIMS 1E+03 1E+20 1E+19 Low O and C background 1E+02 No Interface peak 16O Counts Per Second Concentration 1E+18 1E+01 1E+17 12C 1E+16 1E+00 0246 810 Depth (microns) Strained Si layers SiGe 40% SiGe graded 5...40% Pure Ge on Silicon substrates Low defect density Ge without SiGe graded buffer Ge Si wafer Cross sectional TEM Plan view TEM (looking down through Ge cap) Growth Rate vs Germanium concentration 12 Rate @ 495° 10 570°C Rate @ 525° Rate @ 570° 8 ) 525°C 6 4 495°C 2 Growth Rate (nm/minute 0 0 5 10 15 20 25 30 35 40 Ge concentration (%) Growth
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