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Traditional bulk silicon encounters perform- and silicon-on-insulator and, ultimately, ger- Mark Telford ance limitations in shrinking CMOS transis- manium-on-insulator technology, the life of tor feature size to 65nm. But, through the silicon substrates could be stretched as far use of silicon-germanium, strained silicon, as the 22nm generation. Stretching silicon’s lifespan
According to the International Technology France’s Soitec was founded in 1992 as the first Roadmap for Semiconductors, as CMOS transistor company devoted to volume SOI material manu- dimensions shrink beyond the 65nm generation to facturing, and claims that its Smart Cut wafers 45nm, bulk silicon will encounter fundamental lim- have 90% share of the thin-film SOI market its of channel mobility and gate leakage current. (including 10% through licensee Shin-Etsu Indeed, the 130nm and 90nm generations already Handotai). Its June quarter saw record sales, up partly rely on engineered silicon substrates. 68% on a year ago, boosted by demand for 300mm SOI wafers, which are being introduced Silicon on insulator (SOI) introduces a buried by IBM, Sony, and AMD in 2005. In addition to layer of insulating oxide between the bulk and Soitec’s Bernin I 4-8” wafer plant, Bernin II has a the upper surface of the silicon wafer.This capacity of 120,000 300mm wafers per year (ris- increases electrical isolation and reduces para- ing ultimately to 720,000). sitic junction capacitance between device and substrate.That decreases transistor delay time, Analysts forecast that, by 2005, 45% of SOI enabling higher-speed digital ICs, and increasing demand will switch to 300mm, comprising drive currents, while lowering noise and power nearly 50% of 300mm substrates consumed by consumption (by up to a factor of four). 2009. In 2003 SOI represented just 2.5% of total silicon Strained silicon revenues but up to 10% for leading-edge technol- ogy nodes, and has a compound annual growth Device performance can be further improved, rate three to four times that of silicon. For 65nm without shrinks and related capital cost increase, technology, SOI adoption is expected to increase by epitaxially depositing silicon-germanium Figure 1. A SiGe "virtual" (SiGe). Due to a lattice constant mismatch of substrate induces strain in dramatically for high-end microprocessor and silicon grown on top. logic ICs. 4.2% between Si (5.431Å) and Ge (5.657Å), in
Si1-xGex (where o
formation of an in-depth weakened layer strained Si/SiGe strained
4 Cleaning & bonding A to B UK epiwafer foundry IQE plc aims to be the first Si B licensee of Salem, NH-based,AmberWave
5 Smart Cut spits off the top at the mean ion penetration depth, leaving either an SiGe SiGe Systems’ strained-silicon technology for 150 and layer on which strained Si is grown 200mm wafers, reckoning on extending the life or a layer of previously grown Si B strained Si (sSOI) cycle of a fab by two to three years.
6 Annealing & SiGe strained SOI CMP touch polish Strained SOI Strained SOI wafer complete The high speed of strained silicon can be com- 7 Split-off wafer A becomes new New strained Si/SiGe A or B bined with the low-power benefits of SOI, result- ing in strained SOI wafers for 65-45nm CMOS from 2005:
36 III-Vs REVIEW THE ADVANCED SEMICONDUCTOR MAGAZINE VOL 17 - NO 7 - SEPTEMBER/OCTOBER 2004 Insulated silicon TECHNICAL FOCUS
(1) In SiGe-on-insulator (SGOI), a relaxed SiGe layer is transferred onto an oxidised silicon wafer, followed by removal of the donor sub- SGOI (65nm-45nm) sSOI (45nm) strate. Strained silicon can be deposited either Relaxed SiGe sSi directly on BOX as template for sSi before transfer (before the SiGe layer is deposit- ed and on top of a graded Si 1-xGex buffer layer, s-Si r-Si1-xGex s-Si r-Si Ge which is removed after transfer) or after transfer 1-x x BOX (on to what has become a silicon-germanium on BOX Si base B insulator substrate), forming a substrate for epi- B Si base taxy of strained silicon (see Figure 2a).
However, the quality of the SiGe and buried Ge oxide (BOX) layers is a concern, causing material GeOI (32nm) BOX and process integration challenges. In addition, Germanium on Insulator Si base B Ge segregation during high-temperature anneal- ing also limits the maximum Ge composition to a low value.A major concern about the manufac- turability is the high level of crystal defects in depleted device architectures, offering strain Figure 2. Structure for the strained Si layer, typically due to the epi tech- reproducibility in silicon layers as thin as 15nm. a) SiGe-on-insulator (SGOI), (b) strained silicon-on-insula- nique used to grow the SiGe templates. To enable early sampling, concurrent with the tor (sSOI), and (c) germanium-on-insulator (2) In strained silicon directly-on-insulator (SSDOI) development of the epi modules a ‘virtual fab’ (GeOI). - or strained silicon-on-insulator (s-SOI) - a thin operation processes wafers at both companies, layer of strained silicon is epitaxially deposited on enabling fine-tuning of the epi processes to opti- a relaxed SiGe buffer layer, before an oxide layer is mise substrate performance, boost productivity formed.After hydrogen implantation into the SiGe, and maximise cost efficiency, before Sooitec flipping and bonding of the wafer to a handle sub- announced last December that it was installing strate, and high-temperature splitting away of the epi equipment in its pilot line and a full SGOI bulk silicon, the remaining SiGe is removed, leav- and s-SOI manufacturing line at its new 300mm ing SiGe-free strained SOI (see Fig 2b). Bernin II plant.
Processes have been demonstrated by IBM, SGOI early production was due to start in Massachusetts Institute of Technology and Q4/2004.“The ability to perform the epitaxy AmberWave Systems. In September 2003 IBM process in our own production facility will help claimed fabrication of the first transistors using ensure that we can rapidly deliver volume quan- ultra-thin SSDOI, confirmed electron and hole tities of high-quality strained SOI wafers,”says mobility enhancements in MOSFETs, and fabricat- president and CEO André Auberton-Herve. Full ed sub-60nm FETs. capacity will be more than 60,000 200mm-equiv- alent wafer starts per year.
Commercial SGOI and sSOI Using an ASM A412 vertical furnace and a low- Extending a previous collaboration on Soitec’s temperature-enhanced Epsilon 3200 reactor, this 300mm Unibond SOI wafers that used Advance July saw the industry’s first 300mm strained sili- 400 Series vertical furnaces from Netherlands- con substrates, the first high-quality sSOI with based ASM International, in May 2003 a joint wafer-level strain rather than local strain, reduc- strained SOI partnership programme was initiat- ing the high level of crystal defects to nearer to ed that combines Soitec’s Smart Cut SOI technol- that of standard SOI and bulk silicon. ogy with strained silicon epi deposition using “Customer and internal evaluations show that ASM’s Epsilon 3000 reactor.This led in July 2003 the strain of s-SOI is very robust, surviving the to industry-first samples of first-generation typical thermal budgets of 65nm CMOS process- strained SOI wafers for 65nm technology. es,”claims CTO Carlos Mazure.“Strained SOI appears to offer the greatest potential for Soitec’s first strained SOI product consists of a improving the performance of ICs with 65nm 200mm fully relaxed SGOI template substrate, and below design rules”, adds Auberton-Hervé. incorporating 20% Ge (with or without growth of the final strained silicon layer).The wafers can Subsequent generations of strained silicon will be tailored for both partially depleted and fully include SGOI with higher Ge content, strained
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SOI without the SiGe template layer (s-SOI), and and CEO Francois J Henley says it can “signifi- germanium-on-insulator (GeOI) - see Figure 3. cantly enhance mobility over SiGe-based biaxial strain.”It is also compatible with local straining Current relaxed SiGe-based strained silicon and s- techniques and is therefore additive, boosting SOI are based on biaxial wafer-level strain (uniform transistor performance further. SiGen’s process over the substrate’s device fabrication surface). can achieve stress of over 1GPa in a uniaxially But biaxial strain suffers from high defect levels strained silicon layer, either on top of a buried and germanium inter-diffusion, leading to mobili- oxide (s-SOI) or as a bulk Si wafer (s-Si/bulk). ty degradation at high effective gate electric Low-temperature processing yields low defect fields (~1MV/cm) and much lower efficiency in levels. It can be directly integrated on silicon as boosting PMOS transistor performance, contrast an ‘epi-like’ strained bulk wafer or on insulator as in uniaxial strain, where the device silicon film is s-SOI. Production costs are expected to be signifi- strained in a single direction on the crystal sur- cantly lower than biaxial technologies by avoid- face to enhance the mobility. ing growing and relaxing thick SiGe layers steps.
Uniaxial vs biaxial strain “Aavailability of a wafer-level uniaxially strained Benefits of uniaxial strain at the local, transistor substrate works with these existing approaches level have been demonstrated by chip makers to substantially improve total transistor perform- including Intel,TSMC and Texas Instruments. ance and has scaling advantages over local strain Local strain uses micron-scale epi deposition to at the 45nm node and beyond,”Henley adds. strain selected transistor regions. Intel’s 90nm In line with its new IP business model strategy, technology is first to implement a uniaxial SiGen is pursuing development and commerciali- strained silicon process with different stress sation with partners. techniques on the NMOS and PMOS transistors.
Dr Scott Thompson, University of Florida associ- Towards 32-22nm: GeOI ate professor and former director of Intel’s 90nm In 2003 Belgian microelectronics research centre Logic Technology and Strained Silicon IMEC launched two industrial affiliation pro- Programme, adds:“Uniaxial strain is now being grammes (IIAPs) targeting sub-45nm processes: recognized as the preferred strain type for deep- (1) “Implementation of high-mobility layers and submicron device applications, and its local vari- advanced source/drain engineering solutions in ant has displaced global biaxial strain as the scaled planar devices” (ie. strained silicon in a mobility enhancer of choice”. MOS transistor’s channel): IMEC has fabricated Wafer-level vs local strain strained silicon transistors on thin (sub-200nm) strain-relaxed SiGe buffers that show record hole Figure 3. SOITEC's roadmap This August Silicon Genesis Corp said it had mobility in hetero-pMOS with strained SiGe. for SiGe-on-insulator, strained developed ‘Next-Generation Strain’, the first silicon-on-insulator, and ger- (2) Germanium-based CMOS transistors compati- manium-on-insulator. wafer-level uniaxial strained substrates. President ble with silicon process lines (200mm, migrating to 300mm). In Ge channels, carrier mobilities for both electrons and holes are higher than silicon’s (by two and four times, respectively) tripling 140 130nm BOX: Ultra thin/Pattern/New materials transistor switching speed. 120 Multiple Gate/FinFets IMEC has examined deposition on Ge of MOS 100 gates, comprising TaN metal and HfO high-k 90nm 2 Thin SOI 80 dielectric (a promising replacement for SiO2 in
ailabilty SOI 300 mm v SOI HR 65nm silicon CMOS but also overcoming the unstable 60 nature of germanium oxide, allowing aggressive 45nm 40 scaling of the equivalent oxide thickness).Wet
Sample A 32nm
echnology node (nm) SGOI T 20 sSOI 22nm treatment with hydrofluoric acid, followed by an GeOI 200mm 300mm NH3 anneal at 600°C created a smooth Ge-HfO2 0 interfacial layer to avoid Ge diffusion. Ge’s lower- Industry 2001 2003 2005 2007 2009 2011 Roadmaps temperature activation of dopants (implantated boron for n-type and arsenic for p-type) enabled the formation of shallow junctions.
38 III-Vs REVIEW THE ADVANCED SEMICONDUCTOR MAGAZINE VOL 17 - NO 7 - SEPTEMBER/OCTOBER 2004 Insulated silicon TECHNICAL FOCUS
To avoid the need for bulk Ge substrates, September 2003 saw collaboration on the fabri- cation of germanium-on-insulator (GeOI) sub- SOI: bonded vs SIMOX strates, using Soitec’s Smart Cut process to trans- In the manufacture of SOI Nabeel Gareeb. However, non- fer a thin Ge layer from Umicore’s Ge bulk wafers, a buried oxide can be contact wafer smoothing yields wafers on to an insulating oxide layer on a sili- fabricated by separation by improved SOI layer thickness con substrate. In March Soitech agreed to com- implanted oxygen (SIMOX) or uniformity (required for fully bine Smart Cut expertise with the deposition by wafer bonding. SIMOX depleted SOI < 65nm) and gave capabilities of Applied Materials Inc’s Centura RP involves oxygen ion implanta- flexible derivative developiment Epi system, which can deposit virtually any Ge/Si tion into the wafer’s surface, combination up to 100% Ge. Believing dedicated wafer man- followed by a high-temperature ufacturers are best-positioned Subsequently, IMEC’s 200mm silicon prototyping anneal, then thermal oxidation. to meet demand, in July, line has fabricated a transistor device with an Ideal for bulk silicon, SIMOX is isolation structure and a directly etched gate SIMOX-focused Ibis Technology not so successful for strained stack. Extensions were implanted and spacers Corp terminated volume SOI SiGe-on-insulator (SGOI) with formed prior to source/drain implantation. wafer manufacture to focus on Ge content above 30% and can- supplying SOI ion implanters. Marc Meuris, director of the germanium CMOS not handle strained silicon This February Wacker Chemie’s device programme,says that to achieve the high- directly on insulator (SSDOI). er yield and reliability required for ULSI circuits, But wafer bonding does allow Siltronicdivision,licensed Soitec’s low-defect substrates need to be developed. SGOI with any Ge content, as Smart Cut technology (to pro- duce bonded SOI wafers in sec- In March 2003, Silicon Genesis detailed its devel- well as SSDOI. ond-half, 2005) and agreed a opment of GeOI. SiGen’s layer transfer process is In January, silicon wafer maker joint programme to accelerate suited to creating heterogeneous layered struc- MEMC Electronic Materials Inc development of strained SOI. tures, since low processing temperatures min- licensed NanoTec layertransfer imise adverse temperature affects on materials SOI technology and bought "With acceleration of new tech- such as germanium, and allow layer transfer of room-temperature controlled nology nodes, and the resulting materials other than silicon to various substrates. cleaving and integrated Plasma industry shift to the advanced GeOI is used by IBM to develop Ge photodetec- Activation bonding tools from materials for device perform- tors integrated on silicon for on-chip optical Silicon Genesis Corp. "We had ance and low power consump- communications. Ge’s close match in lattice previously considered bonded tion, SOI has become a critical, parameter with GaAs could offer the missing and SIMOX technologies to be enabling technology," said CEO link vital for cost-effective on-chip integration of viable options," said CEO Wilhelm Sittenthaler. active optical components.
The 50th International Electronic Device Meeting
This historic conference, which on Selectively formed, high University and Yun-Lin Poly- Toshiba Ceramics, Komatsu traditionally always produces a mobility strained Ge technic Institute contribute Electronic Materials and MIRAI- cornucopia of ingenious devices, PMOSFETs for high perform- Three dimensional GOI AIST look at Performance from which the key developing ance CMOS and SiGe HBT tech- CMOSFETs with novel IrO2 enhancement of partially, and trends emerge, is held this nology with gate delay below (Hf) dual gates and high-k fully-depleted strained SOI year in San Francisco, 13-15 3.3ps as well as work on dielectric on 1P6M-0.18mm MOSFETs and character- Decem-ber. Performance comparison and CMOS.” isation of strained-Si device channel length scaling of parameters. Extending silicon can be found Japan papers include Toshiba strained Si FETs on SGOI. throughout the entire meeting, Corporation and Sony work on And from IHP Frankfurt, but two session are specifically From Taiwan,TSMC researchers The parasitic resistance and sil- Germany comes Integration of devoted to strained Si & CMOS present on Low power device icon layer thickness scaling for High Performance SiGe:C HBTs devices and one to SiGe HBTs technology with SiGe channel, strained silicon MOSFETs with thin-film SOI CMOS and
IBM’s redoubtable T J Watson HfSiOn and Poly-Si gate, while on relaxed Si1-xGex virtual Infineon’s work is on 3.3ps SiGe Centre researchers have work the National Chiao Tung substrate. bioplar technology.
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