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Stretching Silicon's Lifespan

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Stretching Silicon's Lifespan ViewTECHNICAL metadata, citation and FOCUS similar papers at core.ac.ukInsulated silicon brought to you by CORE provided by Elsevier - Publisher Connector Traditional bulk silicon encounters perform- and silicon-on-insulator and, ultimately, ger- Mark Telford ance limitations in shrinking CMOS transis- manium-on-insulator technology, the life of tor feature size to 65nm. But, through the silicon substrates could be stretched as far use of silicon-germanium, strained silicon, as the 22nm generation. Stretching silicon’s lifespan According to the International Technology France’s Soitec was founded in 1992 as the first Roadmap for Semiconductors, as CMOS transistor company devoted to volume SOI material manu- dimensions shrink beyond the 65nm generation to facturing, and claims that its Smart Cut wafers 45nm, bulk silicon will encounter fundamental lim- have 90% share of the thin-film SOI market its of channel mobility and gate leakage current. (including 10% through licensee Shin-Etsu Indeed, the 130nm and 90nm generations already Handotai). Its June quarter saw record sales, up partly rely on engineered silicon substrates. 68% on a year ago, boosted by demand for 300mm SOI wafers, which are being introduced Silicon on insulator (SOI) introduces a buried by IBM, Sony, and AMD in 2005. In addition to layer of insulating oxide between the bulk and Soitec’s Bernin I 4-8” wafer plant, Bernin II has a the upper surface of the silicon wafer.This capacity of 120,000 300mm wafers per year (ris- increases electrical isolation and reduces para- ing ultimately to 720,000). sitic junction capacitance between device and substrate.That decreases transistor delay time, Analysts forecast that, by 2005, 45% of SOI enabling higher-speed digital ICs, and increasing demand will switch to 300mm, comprising drive currents, while lowering noise and power nearly 50% of 300mm substrates consumed by consumption (by up to a factor of four). 2009. In 2003 SOI represented just 2.5% of total silicon Strained silicon revenues but up to 10% for leading-edge technol- ogy nodes, and has a compound annual growth Device performance can be further improved, rate three to four times that of silicon. For 65nm without shrinks and related capital cost increase, technology, SOI adoption is expected to increase by epitaxially depositing silicon-germanium Figure 1. A SiGe "virtual" (SiGe). Due to a lattice constant mismatch of substrate induces strain in dramatically for high-end microprocessor and silicon grown on top. logic ICs. 4.2% between Si (5.431Å) and Ge (5.657Å), in Si1-xGex (where o<x<l) the distance between silicon atoms is stretched. Such tensile strain increases the mobility of charge carriers in a General SOI Process Flow SiGe-based transistor, speeding devices. 1 Initial wafers - a strained Si layer Wafer A: strained Si Silicon wafer B may or may not already be grown and/or SiGe A strain-relaxed Si1-xGex graded buffer layer on on Wafer A's template SiGe silicon can also provide a SiGe ‘virtual’ substrate 2 Dielectric - adds layer of insulation strained Si/SiGe for epitaxy of silicon, with in-built strain (see (to A or B, in this example it is to A) H+ ions Figure 1),enabling a higher-mobility channel 3 Smart Cut ion implantation induces strained Si/SiGe layer for 65-45nm CMOS transistors. formation of an in-depth weakened layer strained Si/SiGe strained 4 Cleaning & bonding A to B UK epiwafer foundry IQE plc aims to be the first Si B licensee of Salem, NH-based,AmberWave 5 Smart Cut spits off the top at the mean ion penetration depth, leaving either an SiGe SiGe Systems’ strained-silicon technology for 150 and layer on which strained Si is grown 200mm wafers, reckoning on extending the life or a layer of previously grown Si B strained Si (sSOI) cycle of a fab by two to three years. 6 Annealing & SiGe strained SOI CMP touch polish Strained SOI Strained SOI wafer complete The high speed of strained silicon can be com- 7 Split-off wafer A becomes new New strained Si/SiGe A or B bined with the low-power benefits of SOI, result- ing in strained SOI wafers for 65-45nm CMOS from 2005: 36 III-Vs REVIEW THE ADVANCED SEMICONDUCTOR MAGAZINE VOL 17 - NO 7 - SEPTEMBER/OCTOBER 2004 Insulated silicon TECHNICAL FOCUS (1) In SiGe-on-insulator (SGOI), a relaxed SiGe layer is transferred onto an oxidised silicon wafer, followed by removal of the donor sub- SGOI (65nm-45nm) sSOI (45nm) strate. Strained silicon can be deposited either Relaxed SiGe sSi directly on BOX as template for sSi before transfer (before the SiGe layer is deposit- ed and on top of a graded Si 1-xGex buffer layer, s-Si r-Si1-xGex s-Si r-Si Ge which is removed after transfer) or after transfer 1-x x BOX (on to what has become a silicon-germanium on BOX Si base B insulator substrate), forming a substrate for epi- B Si base taxy of strained silicon (see Figure 2a). However, the quality of the SiGe and buried Ge oxide (BOX) layers is a concern, causing material GeOI (32nm) BOX and process integration challenges. In addition, Germanium on Insulator Si base B Ge segregation during high-temperature anneal- ing also limits the maximum Ge composition to a low value.A major concern about the manufac- turability is the high level of crystal defects in depleted device architectures, offering strain Figure 2. Structure for the strained Si layer, typically due to the epi tech- reproducibility in silicon layers as thin as 15nm. a) SiGe-on-insulator (SGOI), (b) strained silicon-on-insula- nique used to grow the SiGe templates. To enable early sampling, concurrent with the tor (sSOI), and (c) germanium-on-insulator (2) In strained silicon directly-on-insulator (SSDOI) development of the epi modules a ‘virtual fab’ (GeOI). - or strained silicon-on-insulator (s-SOI) - a thin operation processes wafers at both companies, layer of strained silicon is epitaxially deposited on enabling fine-tuning of the epi processes to opti- a relaxed SiGe buffer layer, before an oxide layer is mise substrate performance, boost productivity formed.After hydrogen implantation into the SiGe, and maximise cost efficiency, before Sooitec flipping and bonding of the wafer to a handle sub- announced last December that it was installing strate, and high-temperature splitting away of the epi equipment in its pilot line and a full SGOI bulk silicon, the remaining SiGe is removed, leav- and s-SOI manufacturing line at its new 300mm ing SiGe-free strained SOI (see Fig 2b). Bernin II plant. Processes have been demonstrated by IBM, SGOI early production was due to start in Massachusetts Institute of Technology and Q4/2004.“The ability to perform the epitaxy AmberWave Systems. In September 2003 IBM process in our own production facility will help claimed fabrication of the first transistors using ensure that we can rapidly deliver volume quan- ultra-thin SSDOI, confirmed electron and hole tities of high-quality strained SOI wafers,”says mobility enhancements in MOSFETs, and fabricat- president and CEO André Auberton-Herve. Full ed sub-60nm FETs. capacity will be more than 60,000 200mm-equiv- alent wafer starts per year. Commercial SGOI and sSOI Using an ASM A412 vertical furnace and a low- Extending a previous collaboration on Soitec’s temperature-enhanced Epsilon 3200 reactor, this 300mm Unibond SOI wafers that used Advance July saw the industry’s first 300mm strained sili- 400 Series vertical furnaces from Netherlands- con substrates, the first high-quality sSOI with based ASM International, in May 2003 a joint wafer-level strain rather than local strain, reduc- strained SOI partnership programme was initiat- ing the high level of crystal defects to nearer to ed that combines Soitec’s Smart Cut SOI technol- that of standard SOI and bulk silicon. ogy with strained silicon epi deposition using “Customer and internal evaluations show that ASM’s Epsilon 3000 reactor.This led in July 2003 the strain of s-SOI is very robust, surviving the to industry-first samples of first-generation typical thermal budgets of 65nm CMOS process- strained SOI wafers for 65nm technology. es,”claims CTO Carlos Mazure.“Strained SOI appears to offer the greatest potential for Soitec’s first strained SOI product consists of a improving the performance of ICs with 65nm 200mm fully relaxed SGOI template substrate, and below design rules”, adds Auberton-Hervé. incorporating 20% Ge (with or without growth of the final strained silicon layer).The wafers can Subsequent generations of strained silicon will be tailored for both partially depleted and fully include SGOI with higher Ge content, strained www.three-fives.com 37 TECHNICAL FOCUS Insulated silicon SOI without the SiGe template layer (s-SOI), and and CEO Francois J Henley says it can “signifi- germanium-on-insulator (GeOI) - see Figure 3. cantly enhance mobility over SiGe-based biaxial strain.”It is also compatible with local straining Current relaxed SiGe-based strained silicon and s- techniques and is therefore additive, boosting SOI are based on biaxial wafer-level strain (uniform transistor performance further. SiGen’s process over the substrate’s device fabrication surface). can achieve stress of over 1GPa in a uniaxially But biaxial strain suffers from high defect levels strained silicon layer, either on top of a buried and germanium inter-diffusion, leading to mobili- oxide (s-SOI) or as a bulk Si wafer (s-Si/bulk). ty degradation at high effective gate electric Low-temperature processing yields low defect fields (~1MV/cm) and much lower efficiency in levels. It can be directly integrated on silicon as boosting PMOS transistor performance, contrast an ‘epi-like’ strained bulk wafer or on insulator as in uniaxial strain, where the device silicon film is s-SOI.
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