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Evolution and Expansion of SOI in VLSI Technologies: IEEE International Planar to 3D SOI Conference Dr Evolution and Expansion of SOI in VLSI Technologies: IEEE International Planar to 3D SOI Conference Dr. Gary Patton Oct. 2, 2012 - Napa, CA VP, IBM Semiconductor Research & Development Center 1 © 2012 IBM Corporation 978-1-4673-2691-9/12/$31.00 ©2012 IEEE Evolution and Expansion of SOI in VLSI Technologies: Planar to 3D I. SOI History and Advantages • High Performance Logic Applications • Embedded Memories • Analog Mixed-Signal Applications II. Fully Depleted Devices • Fundamentals •FDSOI •FinFETs III. Business Considerations International SOI Conference Oct. 2, 2012 2 The Marketplace is Expanding 250nm 180nm 130nm 90nm 65nm 45nm 32nm 22nm 14nm IBM High-End Servers Desktop Class Processors & Printers Games Communications & Storage Other Consumer SOI can help take solutions well into the future International SOI Conference Oct. 2, 2012 3 SOI Value Adders • Superior Isolation • High Speed Switching – No Well Taps required – 2X lower junction perimeter capacitance – Smaller circuit foot‐print – Improved Short‐Channel Effects – Latch‐up free operation • Less susceptibility to soft errors • Reduced Variation within Die – SER reduced by 5‐7X – Short‐channel Vt roll‐off suppression – Low power high reliability – Less variation in Vt vs Lgate. – No Well‐Proximity Effects (no deep wells in SOI) International SOI Conference Oct. 2, 2012 4 IBM SOI Technology Roadmap 10nm Scaled FinFET 14nm FinFET rd Generations of technology 22 nm 3 Gen. HiK Leadership 2nd Gen. HiK 32 nm High-K gate dielectric on SOI gy lo 45 nm no eDRAM h ec Ultra Low-k metal dielectrics t Immersion lithography M 65 nm IB in Advanced Strained on Silicon ti 90 nm va no Low-k dielectrics + DSL in ed in 130 nm nd a 2 Gen. H/S PDSOI st Su 180 nm H/S Silicon-on-Insulator International SOI Conference Oct. 2, 2012 5 SOI‐enabled Revolution in Computing Systems Watson meets Jeopardy! Beats two human competitors on the popular U.S. quiz show "Jeopardy!" in a three-day showdown . What’s in Watson? Watson is powered by 10 racks of IBM POWER 750 systems Processor Based on 45 nm SOI Technology with embedded DRAM (eDRAM) memory Watson can operate at 80 teraflops per second – 80 trillion operations per second IBM, Nuance to Tune Watson for Use in Health Care & Other Applications International SOI Conference Oct. 2, 2012 6 Integrating DRAM and Logic Innovations to Obtain High Performance Systems Cu M1 Bitline • Technology: W Array passgate Ct Use SOI buried oxide to simplify process & reduce BOX STI parasitics Deep trench Scale the pass transistor for capacitor higher performance s Bulk SOI • Design: 50 40 TypicalTypical commodity DRAM Address retention through 30 concurrent refresh 20 10 Cycle time (ns) (ns) time time Cycle Cycle Innovative direct sense 0 250 180 130 90 65 45 architecture for performance Node International SOI Conference Oct. 2, 2012 7 How SOI Facilitates eDRAM Process Simplification: ~10-15% Adder Collar process elimination Buried Plate process elimination Plate is now Built into SOI wafer International SOI Conference Oct. 2, 2012 8 Integrated Embedded Memory Solutions . Memory is 50-70% of the die – key to optimizing performance . High Performance eDRAM delivers 3X more memory at same die size & power 3X density benefit vs SRAM > 5X standby power benefit > 1000X SER benefit . Compact decoupling cap for noise reduction and I/O is a great bonus! 100 100 10 80 Power 7+ Process Chip SRAMs – 567mm2 32nm SOI eDRAM 1 60 technology 0.1 Low 40 – Eight processor cores leakage – 80MB on chip eDRAM shared L3 LeakageLeakage (nA) (nA) 0.01 20 eDRAM PerformancePerformance (AU) (AU) – Equivalent function of 5.4B 0.001 0 transistors due to eDRAM 0.5 0.4 0.3 0.2 0.1 0 efficiency International SOI Conference Oct. 2, 2012 9 Cell Size ( m2) eDRAM Scalability • eDRAM continues to scale with Logic • Innovations enabling continued scaling include: – High‐k Trench capacitor – N‐epi plate – FinFET transfer device • Scaling increases leverage over SRAM Hi K node+metal electrode – Trend expected to continue to foreseeable future 1.000 N-epi plate 0.100 Cell Size Cell (um2) 0.010 Schematic of 180 130 90 65 45 32 22 14 10 FIN -DT Technology Node (nm) Integration International SOI Conference Oct. 2, 2012 10 More than Moore PDSOI • SOI is a Value‐Add to mature CMOS base Technologies – Integration of wide variety of applications readily enabled • High‐Voltage: (dielectric isolation eliminates latch‐up and leakage) • High performance analog: ( Complementary Bipolar with low Ccs and dielectric isolation) • RF – intrinsically low isolation capacitances and Low harmonic distortion with appropriate substrate design/engineering • High reliability applications ( greatly reduced soft error rates) – Superior Isolation • High resistivity substrates – Enables high Q passives with low loss – Low Harmonic distortion from coupling between adjacent devices – Reduced coupling from substrate noise • Very High‐temperature Operation – No long‐range carrier collection to swamp devices with thermally‐generated leakages – No Latch‐up concerns • Easy support for Positive AND Negative Voltages on die International SOI Conference Oct. 2, 2012 11 RF SOI for Smartphone Applications IBM technologies Antenna tuner Antenna tuners RF SOI*, RF MEMS Power control Power Single-pole/multi-throw switch control Switch RF CMOS RF SOI* PA PA Cellular front-end module Cellular power amps PA PA integration opportunities RF SOI*, SiGe, RF CMOS RF SOI Cellular transceivers Cellular transceivers / RF CMOS, SiGe Analog baseband Wi-Fi RF switch, LNA RF SOI* Wireless SoC transceiver Wireless SoC Wi-Fi (GPS, Bluetooth, Wi-Fi) transceiver switch / Wi-Fi front-end module RF CMOS, CMOS (GPS, BT, Wi-Fi) LNA integration opportunities SiGe TV tuner PA TV tuner Wi-Fi power amps SiGe, RF CMOS SiGe management Digital baseband processors Processor integration opportunities Power Applications Application processors processors Power management Technology Development Alliance/ Common Platform technology HV CMOS Memory International SOI Conference Oct. 2, 2012 12 IBM CSOI7RF Technology for Switches • Leverage IBM’s proven expertise in SOI of 6 generations (180‐32nm) • Based on 180‐nm Lithography – Combination of SOI server technology G and CMRF7SF BEOL • Custom SOI wafer with high SD resistivity substrate and thick BOX – High switch isolation Floating Body • Technology Features Buried Oxide (BOX) – 2.5V (std) and 1.5V (opt) FETs – MIMcap and High‐Value serpentine Gate Bias resistor Vg – SOI PSP models for accurate analog R = 10K modeling RF signal Wch = 1 mm – ESD protection diodes 1GHz, 10V peak T1 T2 T3 T4 Partially Depleted SOI + - 50 Ohm 2.5V 2.5V 2.5V 2.5V Load G S D Stacked DG nFET for switch BOX 4-cell device shown as example Quasi-neutral Fully-depleted Region Region International SOI Conference Oct. 2, 2012 13 Evolution and Expansion of SOI in VLSI Technologies: Planar to 3D I. SOI History and Advantages • High Performance Logic Applications • Embedded Memories • Analog Mixed-Signal Applications II. Fully Depleted Devices • Fundamentals •FDSOI •FinFETs III. Business Considerations International SOI Conference Oct. 2, 2012 14 Fully Depleted Device Fundamentals Source Drain Source Drain 1V 1V Gate 1V Gate Gate Leak Si Gate PDSOI FDSOI FinFET Gate controls this. Gate controls this. Gates control this. Gate can not control No leakage path. No leakage path. below that. So current can leak through there. Have more Si and thus can carry more current. Better Electrostatics Stronger Gate Control – Lower Vt for the same leakage Gate Drain – Shorter channel for the same Vt . Reduced Channel Doping Better SRAMs Source – Less doping-driven threshold fluctuation – Lower supply voltage (Vmin) – by about 150mV – Lower voltages means lower power – up to 40% International SOI Conference Oct. 2, 2012 15 FDSOI Technologies Electrostatic Issues Electrostatic Recovery Electrostatic Recovery High Sub‐VT slope Low Sub‐VT slope Low Sub‐VT slope High DIBL Low DIBL Low DIBL Electrostatic Issues Isolated Well/Channel Back Gate Biasing Scheme Low Body Biasing Efficiency Low Body Biasing Efficiency High Body Biasing Efficiency International SOI Conference Oct. 2, 2012 16 FDSOI Advantages K. Cheng, et al., IEDM 2009 • Planar technology that leverages conventional CMOS processing and design methodology • Excellent short channel control • Superior performance for low-power (LP) applications • Undoped body means much lower random dopant fluctuations (RDF) • FDSOI with competitive performance demonstrated in 20nm GR International SOI Conference Oct. 2, 2012 Slide17 17 FDSOI Back‐gating for Enhanced Flexibility Independent multi‐gate device allows the following: – Dynamically changing Vt on devices (trade leakage for performance) – Adjust out typical process induced Vt variation (tighter control of Vt) – Device optimization depending on the use condition: Multi‐Vt enablement International SOI Conference Oct. 2, 2012 18 28nm UTBB FDSOI ‐ Process Integration • Gate-first type FEOL, same as ST/ISDA 28LP gate • No HP/G-type complex stressors Thin Silicon film • FE process: 80% common with ST/ISDA 28LP • STI isolation • NW/PW/DNW 20% specific • BPN/BPP • 10% less steps in UTBB vs. 28LP • BOX removed • HK • Same LDD implants for all GO1 devices, incl. SRAM • MG • No pocket implants • SPACER • ~ 20 implant steps saved vs. 28LP (2 VTs case) • EPI (raised S/D) • LDD implantation • S/D implantation • BE process: identical to ST/ISDA 28LP • NiPtSi Silicidation • Already qualified for volume production • Std backend FDSOI BULK BOX 25nm • Same defect density vs. ISDA 28LP • Improved
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