Evolution and Expansion of SOI in VLSI Technologies: IEEE International Planar to 3D SOI Conference Dr

Evolution and Expansion of SOI in VLSI Technologies: IEEE International Planar to 3D SOI Conference Dr. Gary Patton Oct. 2, 2012 - Napa, CA VP, IBM Semiconductor Research & Development Center

I. SOI History and Advantages • High Performance Logic Applications • Embedded Memories • Analog Mixed-Signal Applications II. Fully Depleted Devices • Fundamentals •FDSOI •FinFETs III. Business Considerations

International SOI Conference Oct. 2, 2012 2 The Marketplace is Expanding

250nm 180nm 130nm 90nm 65nm 45nm 32nm 22nm 14nm

IBM High-End Servers

Desktop Class Processors & Printers

Games

Communications & Storage

Other Consumer SOI can help take solutions well into the future

International SOI Conference Oct. 2, 2012 3 SOI Value Adders

• Superior Isolation • High Speed Switching – No Well Taps required – 2X lower junction perimeter capacitance – Smaller circuit foot‐print – Improved Short‐Channel Effects – Latch‐up free operation

• Less susceptibility to soft errors • Reduced Variation within Die – SER reduced by 5‐7X – Short‐channel Vt roll‐off suppression – Low power high reliability – Less variation in Vt vs Lgate. – No Well‐Proximity Effects (no deep wells in SOI)

International SOI Conference Oct. 2, 2012 4 IBM SOI Technology Roadmap

10nm Scaled FinFET 14nm FinFET rd Generations of technology 22 nm 3 Gen. HiK Leadership 2nd Gen. HiK 32 nm High-K gate dielectric on SOI gy lo 45 nm no eDRAM ch Ultra Low-k metal dielectrics te Immersion lithography M 65 nm IB in Advanced Strained on Silicon ti 90 nm va no Low-k dielectrics + DSL in ed in 130 nm nd a 2 Gen. H/S PDSOI st Su 180 nm H/S Silicon-on-Insulator International SOI Conference Oct. 2, 2012 5 SOI‐enabled Revolution in Computing Systems

Watson meets Jeopardy! Beats two human competitors on the popular U.S. quiz show "Jeopardy!" in a three-day showdown .

What’s in Watson? Watson is powered by 10 racks of IBM POWER 750 systems Processor Based on 45 nm SOI Technology with embedded DRAM (eDRAM) memory Watson can operate at 80 teraflops per second – 80 trillion operations per second

IBM, Nuance to Tune Watson for Use in Health Care & Other Applications International SOI Conference Oct. 2, 2012 6 Integrating DRAM and Logic

Innovations to Obtain High Performance Systems

Cu M1 Bitline • Technology: W Array passgate Ct  Use SOI buried oxide to

simplify process & reduce BOX STI

parasitics Deep trench  Scale the pass transistor for capacitor higher performance s

Bulk SOI • Design: 50 40 TypicalTypical commodity DRAM  Address retention through 30 concurrent refresh 20 10 Cycle time (ns) (ns) time time Cycle Cycle  Innovative direct sense 0 250 180 130 90 65 45

architecture for performance Node

International SOI Conference Oct. 2, 2012 7 How SOI Facilitates eDRAM Process Simplification: ~10-15% Adder Collar process elimination Buried Plate process elimination

Plate is now Built into SOI wafer

International SOI Conference Oct. 2, 2012 8 Integrated Embedded Memory Solutions

. Memory is 50-70% of the die – key to optimizing performance . High Performance eDRAM delivers 3X more memory at same die size & power  3X density benefit vs SRAM  > 5X standby power benefit  > 1000X SER benefit . Compact decoupling cap for noise reduction and I/O is a great bonus!

100 100

10 80 Power 7+ Process Chip SRAMs – 567mm2 32nm SOI eDRAM 1 60 technology

0.1 Low 40 – Eight processor cores leakage – 80MB on chip eDRAM shared L3 LeakageLeakage (nA) (nA) 0.01 20 eDRAM PerformancePerformance (AU) (AU) – Equivalent function of 5.4B 0.001 0 transistors due to eDRAM 0.5 0.4 0.3 0.2 0.1 0 efficiency International SOI Conference Oct. 2, 2012 9 Cell Size (m2) eDRAM Scalability

• eDRAM continues to scale with Logic • Innovations enabling continued scaling include: – High‐k Trench capacitor – N‐epi plate – FinFET transfer device • Scaling increases leverage over SRAM Hi K node+metal electrode – Trend expected to continue to foreseeable future 1.000

N-epi plate 0.100 Cell Size Cell (um2)

0.010 Schematic of 180 130 90 65 45 32 22 14 10 FIN -DT Technology Node (nm) Integration International SOI Conference Oct. 2, 2012 10 More than Moore PDSOI

• SOI is a Value‐Add to mature CMOS base Technologies – Integration of wide variety of applications readily enabled • High‐Voltage: (dielectric isolation eliminates latch‐up and leakage) • High performance analog: ( Complementary Bipolar with low Ccs and dielectric isolation) • RF – intrinsically low isolation capacitances and Low harmonic distortion with appropriate substrate design/engineering • High reliability applications ( greatly reduced soft error rates) – Superior Isolation • High resistivity substrates – Enables high Q passives with low loss – Low Harmonic distortion from coupling between adjacent devices – Reduced coupling from substrate noise • Very High‐temperature Operation – No long‐range carrier collection to swamp devices with thermally‐generated leakages – No Latch‐up concerns • Easy support for Positive AND Negative Voltages on die International SOI Conference Oct. 2, 2012 11 RF SOI for Smartphone Applications

IBM technologies Antenna tuner Antenna tuners RF SOI*, RF MEMS

Power control Power Single-pole/multi-throw switch control Switch RF CMOS RF SOI* PA PA Cellular front-end module Cellular power amps PA PA integration opportunities RF SOI*, SiGe, RF CMOS RF SOI Cellular transceivers Cellular transceivers / RF CMOS, SiGe Analog baseband Wi-Fi RF switch, LNA RF SOI* Wireless SoC transceiver Wireless SoC Wi-Fi (GPS, Bluetooth, Wi-Fi) transceiver switch / Wi-Fi front-end module RF CMOS, CMOS (GPS, BT, Wi-Fi) LNA integration opportunities SiGe TV tuner PA TV tuner Wi-Fi power amps SiGe, RF CMOS SiGe

management Digital baseband processors Processor integration opportunities Power Applications Application processors processors Power management Technology Development Alliance/ Common Platform technology HV CMOS Memory

International SOI Conference Oct. 2, 2012 12 IBM CSOI7RF Technology for Switches

• Leverage IBM’s proven expertise in SOI of 6 generations (180‐32nm) • Based on 180‐nm Lithography – Combination of SOI server technology G and CMRF7SF BEOL • Custom SOI wafer with high SD resistivity substrate and thick BOX – High switch isolation Floating Body • Technology Features Buried Oxide (BOX) – 2.5V (std) and 1.5V (opt) FETs – MIMcap and High‐Value serpentine Gate Bias resistor Vg – SOI PSP models for accurate analog R = 10K modeling RF signal Wch = 1 mm – ESD protection diodes 1GHz, 10V peak T1 T2 T3 T4

Partially Depleted SOI + - 50 Ohm 2.5V 2.5V 2.5V 2.5V Load G S D Stacked DG nFET for switch BOX 4-cell device shown as example

Quasi-neutral Fully-depleted Region Region International SOI Conference Oct. 2, 2012 13 Evolution and Expansion of SOI in VLSI Technologies: Planar to 3D

International SOI Conference Oct. 2, 2012 14 Fully Depleted Device Fundamentals

Source Drain Source Drain 1V 1V Gate 1V Gate

Gate Leak Si Gate PDSOI FDSOI FinFET Gate controls this. Gate controls this. Gates control this. Gate can not control No leakage path. No leakage path. below that. So current can leak through there. Have more Si and thus can carry more current. . Better Electrostatics  Stronger Gate Control

– Lower Vt for the same leakage Gate Drain

– Shorter channel for the same Vt

. Reduced Channel Doping  Better SRAMs Source – Less doping-driven threshold fluctuation – Lower supply voltage (Vmin) – by about 150mV – Lower voltages means lower power – up to 40% International SOI Conference Oct. 2, 2012 15 FDSOI Technologies

Electrostatic Issues Electrostatic Recovery Electrostatic Recovery High Sub‐VT slope Low Sub‐VT slope Low Sub‐VT slope High DIBL Low DIBL Low DIBL

Electrostatic Issues Isolated Well/Channel Back Gate Biasing Scheme Low Body Biasing Efficiency Low Body Biasing Efficiency High Body Biasing Efficiency

International SOI Conference Oct. 2, 2012 16 FDSOI Advantages

K. Cheng, et al., IEDM 2009 • Planar technology that leverages conventional CMOS processing and design methodology • Excellent short channel control • Superior performance for low-power (LP) applications • Undoped body means much lower random dopant fluctuations (RDF) • FDSOI with competitive performance demonstrated in 20nm GR

International SOI Conference Oct. 2, 2012 Slide17 17 FDSOI Back‐gating for Enhanced Flexibility

Independent multi‐gate device allows the following: – Dynamically changing Vt on devices (trade leakage for performance) – Adjust out typical process induced Vt variation (tighter control of Vt) – Device optimization depending on the use condition: Multi‐Vt enablement

International SOI Conference Oct. 2, 2012 18 28nm UTBB FDSOI ‐ Process Integration

• Gate-first type FEOL, same as ST/ISDA 28LP

gate • No HP/G-type complex stressors

Thin Silicon film • FE process: 80% common with ST/ISDA 28LP • STI isolation • NW/PW/DNW 20% specific • BPN/BPP • 10% less steps in UTBB vs. 28LP • BOX removed • HK • Same LDD implants for all GO1 devices, incl. SRAM • MG • No pocket implants • SPACER • ~ 20 implant steps saved vs. 28LP (2 VTs case) • EPI (raised S/D) • LDD implantation • S/D implantation • BE process: identical to ST/ISDA 28LP • NiPtSi Silicidation • Already qualified for volume production • Std backend FDSOI BULK BOX 25nm • Same defect density vs. ISDA 28LP • Improved vs. “HP” technologies

Courtesy of

International SOI Conference Oct. 2, 2012 19 28nm UTBB FDSOI ‐ Performance & Power

28nm LP not fast le obi enough, dynamic m ” power penalized P H 2 “ 8 by overdrive usage F D S nm 2 O 8 8 L I 2 P

LP OI 2 8 S 8n 2 m 28nm “HP” “HP” 28FD mo DVFS not efficient bile

28LP 28LP

Courtesy of

International SOI Conference Oct. 2, 2012 20 Why Double‐Gate CMOS

Bulk, PDSOI, UTTB-SOI Double-Gate FET

Gate T Gate T INV INV L L SD SD

XD TINV Substrate Gate

• No voltage divider action with substrate

Near‐ideal sub‐threshold swing ( lower VT for same off‐current)

• Scale to smallest LPOLY for a given TOX and TSi Source shielded from drain by two gates • Net: Improved density, performance, power.

International SOI Conference Oct. 2, 2012 21 Why FinFET is the Double‐Gate Solution

Drain Many intrinsic advantages in FinFET Gate t Quasi‐planar processing enables n e n rr i u w F C o • self‐aligned double gates Source fl • dense front side contacts to both gates FinFET • symmetric front‐side access to both sides of source‐drain

Added benefit: “fin effect” means

Weff larger than footprint

International SOI Conference Oct. 2, 2012 22 FinFET Advantages Performance Example of Device Benefit of FinFET at 20nm Node

Lgate Tinv Tfin Ssat DIBL Lgate Tinv Tfin Ssat DIBL (nm) (nm) (nm) (mV/dec.) (mV/V) (nm) (nm) (nm) (mV/dec.) (mV/V) FinFET 30 1.3 13 66 25 FinFET 30 1.8 10 79 82 Planar 30 1.3 n/a 80 82 Planar 30 1.3 n/a 80 82 High-Speed Benefit Low-Power Benefit (Better SCEs for same Lgate/Tinv) (Equivalent SCEs for higher Tinv) Lower SRAM power

• Undoped fin minimizes dopant contribution to variability • Other mechanisms such as work‐function variations remain extant • Net: Large overall reduction in mismatch

International SOI Conference Oct. 2, 2012 23 A Decade of FinFET R&D at IBM/Alliance

Conformal doping in FinFET FinFET (2011) fully-depleted RO demo FinFET (2003) CMOS demo High speed (2002) FinFET device 0.063um2 SRAM N&P with FinFET (2010) (2001) Functional SRAM 0.22um2 (2002)

International SOI Conference Oct. 2, 2012 24 SOISOI FinFETs:FinFETs: ProcessingProcessing InnovationsInnovations

es t Key Innovations: a G . Highly scaled FIN defined by Sidewall-Image- F Transfer (SIT) ins . RMG w/ new metal fill solution and reliability package . Dual in-situ doped epitaxial source/drain for low resistance

World’s Smallest Flycell w/ Optical Litho GATE FINs

FIN

70C 64CPP 64CPP 70CPPPP 0.04u 0.06um0.06 2 0.04umm2 2 um2

IBM CONFIDENTIAL 25 Junction‐isolated Bulk FinFET

FIN Height Gate High K Variation

Source/Drain Isolation

illustrations courtesy of GSS Substrate Gate FINFET Variability

Gate X Capacitance Source/Drain Leakage FIN TEM courtesy of UBM TechInsights GSS TEM courtesy of Chipworks

Several Key power / performance issues of junction-isolated bulk FinFETs: o Gate Height Variation from STI recess degrades performance o Gate Capacitance degrades performance and adds power o Source / Drain Leakage increases power (junction and GIDL)

International SOI Conference Oct. 2, 2012 26 FinFET Isolation Schemes Junction-Isolated Dielectric-Isolated Dielectric-Isolated Bulk FinFET SOI FinFET (FOX) Bulk FinFET (FOX) Gate Electrode Gate Electrode Gate Electrode

Replacement Fin Fin Oxide fill Fin

dep/etch ox. BOX dep/etch ox. Punch-through stop

silicon substrate silicon substrate silicon substrate

Fin on bulk Fin on SOI Fin on oxide over bulk – Fin height controlled by ox – Fin height set by – Doping isolation etch substrate requirement removed – Complex isolation scheme – Simpler isolation – Isolation scheme still – Fin doping control possible scheme complex issue – Requires SOI wafer – Uses bulk wafer – Uses bulk wafer International SOI Conference Oct. 2, 2012 27 SOI ‐ Bulk FinFET Comparison

Metric Comparative Analysis History Effect No floating body in either: timing like Bulk planar CMOS Isolation Biggest challenge for bulk FinFET. Capacitance/leakage tradeoff. Variability Height control very challenging in bulk fin. Isolation doping requirement also adds within‐fin nonuniformity.

Analog FETs No body contact in either. SOI better due to uniform fin doping. Self‐heating Worse in SOI FinFET – minor consideration for most applications. High duty factor circuits may suffer up to 5% drive current penalty. Passives Bulk FinFET can more easily introduce bulk planar passives. SOI FinFET enables planar passives with superior isolation properties.

• FUNDAMENTALLY the same – design for both not a problem. • SIGNIFICANT issues in manufacturing – will be addressed by future generation dielectric isolation or other scheme.

International SOI Conference Oct. 2, 2012 28 Junction‐isolated FinFET Tradeoffs

1.E-09 low-leakage (10nm delta Xod) S/D Isolation Methods high-speed (no delta Xod)

1.E-10 High Doping Deep Gate leakage floor BTBT

Imin/Weff (A/um) Imin/Weff minimizes Cgate low leakage floor high leakage floor Cgate penalty 1.E-11 1.E+17 1.E+18 1.E+19 H/S applications  L/P applications Doping (1/cm3)

SOI FinFET

H/S H H Active Fin Active Fin bulk fin

XOD XOD L/P HParasitic Fin HParasitic Fin bulk fin Application-intense lifetime

Standby lifetime International SOI Conference Oct. 2, 2012 29 SOI vs Junction‐isolated FinFETs

1.2DesignDesign MarginMargin (qualitative)(qualitative) 0.2 VmaxVmax (FOx) (SOI) 0.18 1.1 0.16

Vmax (bulk) 0.14 1 Vmax (Gen1 bulk) 0.12 0.9 0.1 δVt-rdfVt-rdf (bulk) (Gen1 bulk) 0.08 VmaxVmax (V) (V) 0.8 0.06 δVt-rdfVt-rdf (SOI) (Gen2 FOx) Vt-rdfVt-rdf V / V / Nfin^.5) Nfin^.5) 0.7 0.04 δδ 0.02 0.6 0 0.01 0.1 1 10 100 Channel Off current (nA/um)

• VDD Range is modulated by isolation design • High channel doping increases RDFs (AVT) Higher Vmin for SRAM.

• High channel doping Increases EOX for given VT  Lower Vmax (BTI and TDDB). • High AVT also increases Die Iddq for given Ioff  Increased product leakage spec.

International SOI Conference Oct. 2, 2012 30 FinFET Variability and Manufacturing Challenges

International SOI Conference Oct. 2, 2012 31 FinFET Variability and Manufacturing Challenges

Challenge Solution Results Fin Profile Three SOI benefits: Variability Natural height stop Near ideal ‐ Shape/taper Relaxed etch shape ‐ Height control requirements for straighter profile No fill/etch‐back needed for isolation 200 NFET Lgate=25nm End Fin Cut‐last process to 150 Conventional SIT process Variability eliminates end‐fin 100 DIBL

DIBL (mV) DIBL systematic offset 50 New SIT process improvement Yamashita, VLSI 2011 0 0 5 10 15 20 25 30 35 FinFin number number

International SOI Conference Oct. 2, 2012 32 FinFET Variability and Manufacturing Challenges

DIBL (mV) DIBL systematic offset 50 New SIT process improvement Yamashita, VLSI 2011 0 0 5 10 15 20 25 30 35 FinFin number number Fin Doping Conformal doping 1.4 1.3 NFET 1.2 ‐ Vertical techniques 1.1 1 Implanted nonuniformity 0.9 Rodlin 0.8 0.7 in extn and S/D Ron Normalized reduction 0.6 conformal doping 0.5 Yamashita, VLSI 2011 ‐ Doping damage 0.4 15 20 25 30 35 in thin body Lgate (nm) International SOI Conference Oct. 2, 2012 33 Fully Depleted Devices for the Next Node

FDSOI: –Excellent Short Channel Control –Conventional planar processing FDSOI –Back Gate control possible – helps multi-Vt –Body thickness may limit ultimate scalability –Strong potential for today’s expanding Low Power Applications market

FinFET: –Excellent Short Channel Control FinFET –Complex process -- variability & manufacturability challenges –Width Quantization can pose SRAM design challenges –Device electrically wider than physical footprint –Better Scalability: 2x or more relaxation in body thickness requirement –Capability to meet long-term density, performance, & power requirements

International SOI Conference Oct. 2, 2012 34 Evolution and Expansion of SOI in VLSI Technologies: Planar to 3D

International SOI Conference Oct. 2, 2012 35 SOI Advantages & Challenges

PDSOI SOI vs Bulk Device Performance ++ Device Leakage = Cost (substrate + process) ‐‐ Design compatibility ‐‐ Manufacturability (variability, CLY, complexity, cycle time, TTM) = Supply Chain (high volume, multi‐ sourcing, industry perception) ‐‐

International SOI Conference Oct. 2, 2012 36 Paradigm Shift in SOI Value Proposition

PDSOI FINFET SOI vs Bulk SOI vs Bulk Device Performance ++ + Device Leakage = + Cost (substrate + process) ‐‐ = Design compatibility ‐‐ = Manufacturability (variability, CLY, complexity, cycle time, TTM) = ++ Supply Chain (high volume, multi‐ sourcing, industry perception) ‐‐ =

International SOI Conference Oct. 2, 2012 37 SOI ‐ Bulk FinFET Cost Comparison

14nm FINFET SOI vs. Bulk (Implant Isolation)

Bulk Unique Process Adds Comments Substrate Contact ($0‐$30) savings Substrate contact Well contacts $125‐$175 (2.5% ‐ 3.5%) Area impact from well contacts STI Isolation $175‐$300 Liner / Fill / CMP / Etch Back / Cleans 10:1 STI aspect ratio Isolation Implant $60‐$180 (2 ‐ 6) Extra Implants for well isolation

Total $360‐$655

• Assumption of high volume full wafer processing cost at 22nm process is $5000 • Analysis does not include any yield (CLY) benefit of improved variability with SOI FINFETs

International SOI Conference Oct. 2, 2012 38 There3 SOI are least / FOX3 FOX Substrat Substratee wafers suppliers Suppliers ready : SOITEC, ReadyMEMC, SEH

SOITEC AND SHIN-ETSU HANDOTAI ANNOUNCE NEW SMART CUT PARTNERSHIP AND EXTENDED TECHNOLOGY COOPERATION This agreement will accelerate the development and capacity expansion for silicon on insulator (SOI) wafers to meet the market opportunity for FinFETs on SOI and Fully Depleted planar circuits

The combined capacity of the existing suppliers is 2.3-2.4 million wafers/yr by 2014 (substantially early) Additional factory capacity can be put in place by the substrate suppliers :  With a 12 months notification, incremental capacity of 3 million wafers/yr

International SOI Conference Oct. 2, 2012 39 Courtesy of Summary

 SOI has enabled industry leadership in planar CMOS exemplified by both digital and analog mixed-signal applications

 Innovative future opportunities for SOI as Industry moves to Fully Depleted Architectures and beyond Uniformity and Variability control are at the forefront!

 Paradigm shift in SOI value proposition as FinFET era arrives

Acknowledgments: D. Harame, T. Hook, S. Iyer, J. Jagannathan, A. Kumar, E. Nowak

International SOI Conference Oct. 2, 2012 40