Fabrication of Low Cost and Low Temperature Poly-Silicon Nanowire Sensor Arrays for Monolithic Three-Dimensional Integrated Circuits Applications

nanomaterials

Article Fabrication of Low Cost and Low Temperature Poly-Silicon Nanowire Sensor Arrays for Monolithic Three-Dimensional Integrated Circuits Applications

Siqi Tang 1,2, Jiang Yan 1,*, Jing Zhang 1, Shuhua Wei 1, Qingzhu Zhang 2 , Junjie Li 2 , Min Fang 1, Shuang Zhang 1, Enyi Xiong 1, Yanrong Wang 1, Jianglan Yang 3, Zhaohao Zhang 2,*, Qianhui Wei 3,*, Huaxiang Yin 2,4 , Wenwu Wang 2,4 and Hailing Tu 3 1 School of Information Science and Technology, North China University of Technology, Beijing 100144, China; [email protected] (S.T.); [email protected] (J.Z.); [email protected] (S.W.); [email protected] (M.F.); [email protected] (S.Z.); [email protected] (E.X.); [email protected] (Y.W.) 2 Advanced Integrated Circuits R&D Center, Institute of Microelectronic of the Chinese Academy of Sciences, Beijing 100029, China; [email protected] (Q.Z.); [email protected] (J.L.); [email protected] (H.Y.); [email protected] (W.W.) 3 State Key Laboratory of Advanced Materials for Smart Sensing, General Research Institute for Nonferrous Metals, Beijing 101402, China; [email protected] (J.Y.); [email protected] (H.T.) 4 School of Microelectronics, University of Chinese Academy of Sciences, Beijing 100049, China * Correspondence: [email protected] (J.Y.); [email protected] (Z.Z.); [email protected] (Q.W.); Tel.: +86-010-8880-2600 (J.Y.)

Received: 4 November 2020; Accepted: 7 December 2020; Published: 11 December 2020

Abstract: In this paper, the poly-Si nanowire (NW) field-effect transistor (FET) sensor arrays were fabricated by adopting low-temperature annealing (600 ◦C/30 s) and feasible spacer image transfer (SIT) processes for future monolithic three-dimensional integrated circuits (3D-ICs) applications. Compared with other fabrication methods of poly-Si NW sensors, the SIT process exhibits the characteristics of highly uniform poly-Si NW arrays with well-controlled morphology (about 25 nm in width and 35 nm in length). Conventional metal silicide and implantation techniques were introduced to reduce the parasitic resistance of source and drain (SD) and improve the conductivity. Therefore, the obtained sensors exhibit >106 switching ratios and 965 mV/dec subthreshold swing (SS), which exhibits similar results compared with that of SOI Si NW sensors. However, the poly-Si NW FET sensors show the V shift as high as about 178 1 mV/pH, which is five times larger than that of th ± the SOI Si NW sensors. The fabricated poly-Si NW sensors with 600 ◦C/30 s processing temperature and good device performance provide feasibility for future monolithic three-dimensional integrated circuit (3D-IC) applications.

Keywords: silicon nanowire (Si NW); monolithic three-dimensional integrated circuits (M3D-ICs); spacer image transfer (SIT); sensitivity

1. Introduction In recent years, the application of semiconductor ﬁeld-eﬀect transistors (FET) sensors have attracted a lot of attention because of their ability to translate the interaction with target molecules on the FET surface to an electrical signal directly [1–4]. Silicon nanowires (Si NW) sensors have been considered as one of the most promising candidates for biochemical sensors [5–9], due to their large surface to volume (S/V) ratio, high sensitivity, and good biocompatibility [10,11]. In recent years,

Nanomaterials 2020, 10, 2488; doi:10.3390/nano10122488 www.mdpi.com/journal/nanomaterials Nanomaterials 2020, 10, x FOR PEER REVIEW 2 of 11 Nanomaterials 2020, 10, 2488 2 of 11 NW field-effect-transistor (FET) sensors have been used for the very high sensitivity detection of pH [12–14],Si NWgases field-e [15–17]ffect-transistor and DNA (FET)[18–20]. sensors However, have been the conventional used for the very fabrication high sensitivity process detection with silicon- of on-insulatorpH [12– (SOI)14], gases materials [15–17 is] andcomplex DNA and [18– high-c20]. However,ost, and the nanometer conventional pa fabricationtterns are processusually withformed by traditionalsilicon-on-insulator low-efficiency (SOI) materialselectron is beam complex lith andography high-cost, (EBL) and process, the nanometer which patterns does arenot usuallymeet the demandsformed of future by traditional mass production low-efficiency with electron a low beam cost lithography and low efficiency. (EBL) process, The whichspacer does image not meettransfer (SIT) theprocess demands (also of named future mass self-aligned production double with a or low quadruple cost and low patterning) efficiency. Thecould spacer achieve image nanometer transfer array (SIT)with processhigh efficiency (also named and self-aligned low cost, which double are or quadruple widely used patterning) in foundries could achieve[21–23]. nanometer In addition, array there are nowith reports high effionciency the design and low or cost, fabrication which are widelyof Si NW used sensors in foundries for [monolithic21–23]. In addition, three-dimensional there are integratedno reports circuits on the(3D-ICs) design orapplication, fabrication ofwhich Si NW is sensorsone of forthe monolithic most convincing three-dimensional candidates integrated for future circuits (3D-ICs) application, which is one of the most convincing candidates for future application application (see Figure 1). In order to achieve better performance of the system, the fabrication of top (see Figure1). In order to achieve better performance of the system, the fabrication of top devices devices (Si NW sensor) usually need low-temperature processes to avoid a degradation on (Si NW sensor) usually need low-temperature processes to avoid a degradation on characteristics of characteristicsbottom circuits of bottom (logic circuits circuits (logic and memory circuits in and Figure memory1)[ 24]. in However, Figure 1) there [24]. areHowever, no reports there on theare no reportsdesign on the or design fabrication or fabrication of Si NW sensor of Si for NW monolithic sensor for 3D-ICs monolithic application. 3D-ICs application.

FigureFigure 1. Illustration 1. Illustration of ofmonolithic monolithic three-dimensionalthree-dimensional integrated integrated circuits ci (3D-ICs):rcuits (3D-ICs): bottom logic bottom circuits; logic circuits;middle middle memory memory and topand silicon top si nanowirelicon nanowire (Si NW) (Si sensors. NW) sensors.

In this paper, poly-silicon NW sensors with low cost and high efficiency are designed and fabricated In this paper, poly-silicon NW sensors with low cost and high efficiency are designed and using advanced spacer image transfer (SIT) [22–24] and low-temperature silicide techniques for fabricated using advanced spacer image transfer (SIT) [22–24] and low-temperature silicide monolithic 3D-IC application. The highest annealing temperature is not over 600 ◦C, which overcomes techniquesthe problems for monolithic of overheating 3D-IC the application. bottom transistor The andhighest the wires. annealing The achieved temperature poly-silicon is not NW over sensors 600 °C, whichhave overcomes good electrical the problems properties, of such overheating as over six ordersthe bottom of magnitude transistor in on-o andff ratiothe wires. and 932 The mV /achieveddec of poly-siliconsubthreshold NW sensors swing (SS) have by good bias back-gate electrical voltages. properties, such as over six orders of magnitude in on- off ratio and 932 mV/dec of subthreshold swing (SS) by bias back-gate voltages. 2. Materials and Methods 2. MaterialsTwo and types Methods of Si NW sensors (poly-silicon and silicon-on-insulator (SOI)) were designed and fabricated, and the detailed fabrication flow is illustrated in Figure2. The poly-silicon NW sensors were Two types of Si NW sensors (poly-silicon and silicon-on-insulator (SOI)) were designed and manufactured on p-type 200 mm Si (100) silicon wafers (see Figure2a): Firstly, 145 nm SiO 2 and 40 nm fabricated,poly-silicon and the were detailed deposited, fabrication respectively flow (see is Figureillustrated2b). The in SOIFigure Si NW 2. The sensors poly-silicon were manufactured NW sensors were manufacturedon 200 mm SOI waferson p-type featured 200 mm with Si a 145-nm-thick(100) silicon buriedwafers oxide (see Figure layer (BOX) 2a): Firstly, and a 40-nm-thick 145 nm SiO top2 and 40 nmsilicon poly-silicon layer. The were fabrication deposited, process respectively of the two types (see of devicesFigure was2b). allThe the sameSOI Si in theNW flowing sensors steps. were manufacturedDuring the on fabrication 200 mm ofSOI the wafers Si NWs, featured a spacer imagewith transfera 145-nm-thick (SIT) technology buried wasoxide chosen layer to (BOX) form NW and a 40-nm-thickarrays patterns top silicon with layer. high eThefficiency fabrication [25–27], process and the detailedof the two fabrication types of process devices flow was is describedall the same as in the flowingfollows: steps. sequential During multi-layer the fabrication SiO2/amorphous of the Si NWs, Si (α-Si) a spacer/Si3N4 filmsimage were transfer deposited (SIT) (see technology Figure2c). was chosenNext, to form the conventionalNW arrays pattern photolithographys with high process efficiency (i-line) [25–27] and dry, and etching the detailed processes fabrication were used process to form rectangular arrays of Si N and α-Si films (see Figure2d). The top Si N hard masks (HMs) flow is described as follows: sequential3 4 multi-layer SiO2/amorphous Si 3 (α4-Si)/Si3N4 films were were removed by a hot H PO solution at 140 C (see Figure2e). A 30 nm Si N film was deposited by deposited (see Figure 2c). Next,3 4 the conventional◦ photolithography process3 4 (i-line) and dry etching processes were used to form rectangular arrays of Si3N4 and α-Si films (see Figure 2d). The top Si3N4 hard masks (HMs) were removed by a hot H3PO4 solution at 140 °C (see Figure 2e). A 30 nm Si3N4 film was deposited by plasma-enhanced chemical vapor deposition (PECVD) approach and then the corresponding Si3N4 reactive ion etching (RIE) was performed to form two SiNx spacers on both sides of α-Si (see Figure 2f,g). The α-Si material between two Si3N4 spacers was removed by

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plasma-enhanced chemical vapor deposition (PECVD) approach and then the corresponding Si3N4 reactive ion etching (RIE) was performed to form two SiNx spacers on both sides of α-Si (see Figure2f,g). TheNanomaterialsα-Si material 2020, 10 between, x FOR PEER two REVIEW Si3N4 spacers was removed by tetramenthylammonium hydroxide3 of 11 (TMAH) (see Figure2h). In order to obtain Si NW arrays, dry etching processes of SiO 2 and Si weretetramenthylammonium carried out, respectively hydroxide (see Figure (TMAH)2h). (see Afterward, Figure 2h). the In toporder HMs to obtain were removedSi NW arrays, using dry hot phosphoricetching processes acid and of diluted SiO2 and hydrofluoroacid Si were carried (DHF) out, respectively solution, respectively (see Figure 2h). (see Afterward, Figure2i). Afterthe top the Si NWHMs formation,were removed a 5-nm-thick using hot SiO phosphoric2 was deposited acid and on thediluted Si NW hydrofluoroacid followed by the(DHF) deposition solution, of a respectively (see Figure 2i). After the Si NW formation, a 5-nm-thick SiO2 was deposited on the Si thick layer of Si3N4 (see Figure2j,k). The Si 3N4 film was etched by dry etching processes. A nickel NW followed by the deposition of a thick layer of Si3N4 (see Figure 2j,k). The Si3N4 film was etched platinum alloy (Ni0.95Pt0.05) was used to form metal silicide in the source and drain regions to reduce theby parasitic dry etching of Si processes. nanowires A nickel (see Figure platinum2l,m). alloy Afterward, (Ni0.95Pt0.05) BF was2+ usedions to with form a metal heavy silicide dose andin the low 2+ energysource were and implanted drain regions into to the reduce top silicided the parasitic Si NWs of Si and nanowires activated (see by lowFigure temperature 2l,m). Afterward, rapid thermal BF ions with a heavy dose and low energy were implanted into the top silicided Si NWs and activated annealing (RTA) to form Schottky barrier source and drain (SBSD) (about 600 ◦C/30 s annealing). For a by low temperature rapid thermal annealing (RTA) to form Schottky barrier source and drain (SBSD) better combination, the aluminum electrode was prepared by a sputtering process and the RIE process (about 600 °C/30 s annealing). For a better combination, the aluminum electrode was prepared by a was performed (see Figure2n,o). Subsequently, a layer of thick SiO was deposited, and the source sputtering process and the RIE process was performed (see Figure 22n,o). Subsequently, a layer of drain contact holes were opened by photolithography and etching processes (see Figure2p,q). Finally, thick SiO2 was deposited, and the source drain contact holes were opened by photolithography and µ theetching gate with processes different (see channel Figure lengths 2p,q). Finally, (5, 10 and the 15gatem) with was different defined channel by photolithography lengths (5, 10 and and 15 the μm) open gatewas trench defined of the by sensorphotolithography to expose theand sensitive the open area gate wastrench achieved of the sensor by RIE to processes. expose the The sensitive bounding area of SDwas contact achieved was carriedby RIE outprocesses. and a layer The bounding of 20-nm-thick of SD HfO contact2 was was deposited carried out on theand surface a layer ofof the20-nm- device (seethick Figure HfO2r).2 was Figure deposited2s is a on schematic the surface top of view the ofdevice the device. (see Figure Except 2r). for Figure the source2s is a drainschematic and top gate trenchview of of the the devices, device. otherExcept areas for the were source covered drain by and a thick gate SiO trench2, which of the helps devices, to improve other areas the stabilitywere andcovered reliability by a of thick the SiO solution.2, which helps to improve the stability and reliability of the solution.

FigureFigure 2. 2.Fabrication Fabrication flow flow of of Si Si NW NW sensors. sensors. ( a()a) 200 200 mm mm a a p-type p-type (100) (100) silicon silicon wafers,wafers, ((bb)) depositiondeposition of SiOof2 SiOand2 andα-Si α films,-Si films, (c) deposition(c) deposition of of multi-layer multi-layer SiO SiO2/2α/α-Si-Si/Si/Si33NN4 films,films, ( (dd) )conventional conventional lithography lithography andand reactive reactive ion ion etching etching (RIE) (RIE) ofof Si3N44/α/α-Si,-Si, (e ()e )removal removal of ofphotoresist photoresist (PR) (PR) and and Si3N Si4 hard3N4 hardmask, mask, (f) (f)deposited of Si 3NN44 thinthin film, film, ( (gg) )anisotropic anisotropic RIE RIE of of Si Si3N3N4 4toto form form nanometer nanometer Si Si3N34N spacers,4 spacers, (h) ( hremove) remove thetheα-Si α-Si and and RIE RIE SiO SiO2 and2 and Si Si films, films, ( i()i) removal removal ofof toptop hard masks (HMs), (HMs), (j ()j )deposition deposition of of 5 5nm nm SiO SiO2 2 film,film, (k )(k deposition) deposition of of Si 3SiN3N4 4and and i-line i-linelithography, lithography, ((ll)) RIERIE ofof SiSi33N44, ,((mm)) RIE RIE of of Si Si3N3N4 and4 and forms forms metal metal silicide,silicide, (n )(n sputter) sputter metal, metal, ( o()o) RIE RIE of of metal, metal, ((pp)) depositiondeposition of HfO HfO22 film,film, (q (q) )formation formation of of source source and and draindrain contact contact hole, hole, (r )(r formation) formation of of Si Si NW NW channelchannel and bonding and and (s (s) )top top view view of of the the designed designed Si Si NWNW sensors. sensors.

TheThe cross-sectional cross-sectional views views and and top top views views of of the the device’s device’s structures structures were were observed observed using using S-5500 S-5500 and S-4800and scanningS-4800 scanning electron electron microscopes microscopes (SEM, Hitachi,(SEM, Hitachi, Tokyo, Tokyo, Japan), Japan), respectively. respectively. The cross-sectional The cross- proﬁlessectional of the profiles ﬁnal deviceof the final were device performed were perform using transmissioned using transmission electron microscopyelectron microscopy (TEM, FEI (TEM, Talos, Brno,FEI Czech)Talos, Brno, and energy-dispersiveCzech) and energy-dispersive X-ray spectroscopy X-ray spectroscopy (EDX, FEI (EDX, Talos, FEI Brno, Talos, Czech). Brno, Czech). The electrical The electrical characterization was performed using a B1500A (Keysight, Santa Rosa, CA, USA) semiconductor parameter analyzer.

Nanomaterials 2020, 10, 2488 4 of 11 characterization was performed using a B1500A (Keysight, Santa Rosa, CA, USA) semiconductor parameterNanomaterials analyzer. 2020, 10, x FOR PEER REVIEW 4 of 11

3.3. ResultsResults andand DiscussionDiscussion TheThe imagesimages ofof thethe fabricatedfabricated poly-Sipoly-Si NWsNWs sensors by the SIT process are shown in Figure3 3.. FigureFigure3 3a,ba,b shows shows top top views views of of poly-Si poly-Si NW NW arrays arrays by by SEM SEM measurement. measurement. As As can can been been seen seen from from the the images,images, highlyhighly uniformuniform poly-Sipoly-Si NWNW arraysarrays withoutwithout anyany landinglanding padspads areare achieved. achieved. TheThe achievedachieved poly-Sipoly-Si NWNW arraysarrays usingusing thethe SITSIT approachapproach havehave highhigh eefficiency,ﬃciency, lowlow costcost andand smallersmaller sizessizes comparedcompared withwith thatthat ofof fabricatedfabricated usingusing thethe EBLEBL process.process. Figure3 3ccshows showsa across-sectional cross-sectionalview viewof of poly-Sipoly-Si NWs.NWs. ContrastedContrasted with previous previous work work [28,29], [28,29], the the dimens dimensionsions and and the the morphology morphology of the of thefabricated fabricated Si NW Si NWarrays arrays are well are wellcontrolled controlled and extraordinarily and extraordinarily small, small, theoretically theoretically providing providing higher higher sensitivity sensitivity for the forfabricated the fabricated poly-Si poly-SiNW sensor. NW Figure sensor. 3d,e Figure shows3d,e top shows views top of poly-Si views of NW poly-Si sensors NW arrays. sensors The arrays. length The length of the electrode is 2 mm; the gate lengths (L ) of poly-Si NW FETs are 5 µm, 10 µm, of the electrode is 2 mm; the gate lengths (LGs) of poly-SiGs NW FETs are 5 μm, 10 μm, and 15 μm, andrespectively. 15 µm, respectively. The sensor The current sensor is currentincreased is increased and the device’s and the device’svariations variations are reduced are reduced for the formulti- the multi-channelchannel poly-Si poly-Si NW sensors. NW sensors.

FigureFigure 3. ImagesImages of ofpoly-Si poly-Si NW NW sensors. sensors. (a,b) (SEMa,b) images SEM images of poly-Si of poly-Si NW array NW in arraytop view, in top (c) cross- view, (sectionalc) cross-sectional SEM image SEM of imagepoly-Si of NWs, poly-Si (d) top NWs, view (d) of top poly-Si view NW of poly-Si arrays NWsensor arrays by optical sensor microscope, by optical microscope,(e) SEM image (e) SEMof the image final poly-Si of the ﬁnal NW poly-Siarrays sensor NW arrays in top sensor view. in top view.

FigureFigure4 shows4 shows the the cross-sectional cross-sectional TEM TEM image image and the and electron the electron scattering scattering spectrum (EDS)spectrum elemental (EDS) mappingselemental ofmappings the poly-Si of the NWs poly-Si channel. NWs According channel. toAc thecording TEM to image, the TEM the thicknessesimage, the thicknesses of HfO2/SiO of2 layersHfO2/SiO are2 19.34 layers nm are and 19.34 5.25 nm,nm respectively.and 5.25 nm, The respective sizes ofly. the The well-controlled sizes of the regular well-controlled rectangle poly-Siregular NWrectangle is about poly-Si 25 nm NW in is width about and 25 nm 35 nmin width in length. and 35 Furthermore, nm in length. the Furthermore, EDS analysis the of EDS Hf, O,analysis poly-Si, of andHf, O, N elementspoly-Si, and demonstrates N elements that demonstrates the HfO2 and that SiO the2 HfOfilms2 and are verySiO2 uniformfilms are andvery the uniform interfaces and arethe clearinterfaces and flat are withoutclear and inter-di flat withoutffusion. inter-diffusion. The well-controlled The well-controlled insulation layer insulation could reduce layer could the leakage reduce currentthe leakage from current liquid tofrom device, liquid providing to device, a robustprovidin detectiong a robust environment detection environment in the liquid. in the liquid. InitialInitial measurements measurements of transferof transfer and outputand output curves curves (ID-VG (IandD-V IGD -VandD) wereID-VD performed) were performed by applying by aapplying bias gate a voltage. bias gate In thevoltage. measurement In the measurement of the ID-VG curve,of the IIDD-VwasG curve, measured ID was at constant measured drain at voltagesconstant (VdrainD = voltages0.2 V, 1.2(VD V, = −0.22.2 V, V), − and1.2 V, the − gate2.2 V), voltage and the was gate swept voltage from was 0 to swept30 V. from In the 0 measurement to −30 V. In the of − − − − themeasurement ID-VD curves, of the the I drainD-VD curves, current the was drain measured current at constantwas measured gate voltages at constant (VG gatefrom voltages 0 to 20 (V V withG from a − 02 to V − step),20 V with and thea −2 V VD step),was swept and the from VD 0was to swept5 V with from a 00.2 to V−5V step. with a −0.2 V step. − − − The ID-VG and ID-VD curves by bias gate voltages of the p-type poly-Si NW sensors are shown in Figure 5. Figure 5a–c shows typical ID-VG curves of 5-μm-LG, 10-μm-LG and 15-μm-LG poly-Si NW devices, respectively. As can be seen from the images, smooth and uniform p-type MOSFET curves were achieved for the sensors fabricated at low temperature. The Ion/Ioff ratios of poly-Si NW devices with the 5-μm-LG, 10-μm-LG and 15-μm-LG are 5.68 × 106, 2.84 × 106 and 2.31 × 106, respectively. The corresponding extracted values of subthreshold swing (SS) are estimated to be 1070 mV/dec, 965

Nanomaterials 2020, 10, x FOR PEER REVIEW 5 of 11 mV/dec and 956 mV/dec, respectively. Figure 5d depicts the ID-VD curves of poly-Si NW device 10- μm-LG. The drain current increases with increasing VG bias, implying that the carrier’s concentration Nanomaterialsinside Si NWs2020 ,can10, 2488be linearly adjusted, and devices prepared at low temperatures exhibit good5 FET of 11 electrical performance.

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mV/dec and 956 mV/dec, respectively. Figure 5d depicts the ID-VD curves of poly-Si NW device 10- μm-LG. The drain current increases with increasing VG bias, implying that the carrier’s concentration inside Si NWs can be linearly adjusted, and devices prepared at low temperatures exhibit good FET electrical performance.

Figure 4. (a) TEM image of poly-Si NW channel of the device, ( b) EDS elemental mappings of of O, O, Si, Hf and N, respectively.

The ID-VG and ID-VD curves by bias gate voltages of the p-type poly-Si NW sensors are shown in Figure5. Figure5a–c shows typical I D-VG curves of 5-µm-LG, 10-µm-LG and 15-µm-LG poly-Si NW devices, respectively. As can be seen from the images, smooth and uniform p-type MOSFET curves were achieved for the sensors fabricated at low temperature. The Ion/Ioﬀ ratios of poly-Si NW devices with the 5-µm-L , 10-µm-L and 15-µm-L are 5.68 106, 2.84 106 and 2.31 106, respectively. G G G × × × The corresponding extracted values of subthreshold swing (SS) are estimated to be 1070 mV/dec, 965 mV/dec and 956 mV/dec, respectively. Figure5d depicts the I D-VD curves of poly-Si NW device 10-µm-LG. The drain current increases with increasing VG bias, implying that the carrier’s concentration inside Si NWsFigure can4. (a) be TEM linearly image of adjusted, poly-Si NW and channel devices of the prepared device, (b) at EDS low elemental temperatures mappings exhibit of O, Si, good FET electricalHf performance. and N, respectively.

Figure 5. (a–c) ID-VG curves of the fabricated 5-μm-LG, 10-μm-LG and 15-μm-LG p-type poly-Si NW sensors by back bias gate voltage, (d) typical ID-VD of the fabricated 10-μm-LG p-type poly-Si NW sensors.

The ID-VG and ID-VD curves of the SOI Si NW for 5-μm-LG, 10-μm-LG and 15-μm-LG are shown in Figure 6, respectively. As can be seen from the images, smooth p-type MOSFET curves are achieved for the sensors fabricate at low temperature. The Ion/Ioff ratios of 5-μm-LG, 10-μm-LG and 15-μm-LG SOI Si NW devices are 1.47 × 108, 1.29 × 107 and 6.34 × 104, respectively, and extracted values of SSs

FigureFigure 5. ( a5.– c(a)I–cD) -VID-VG Gcurves curves of the the fabricated fabricated 5-μ 5-m-Lµm-LG, 10-G,μ 10-m-LµGm-L andG 15-andμm-L 15-G µp-typem-LG poly-Sip-type NW poly-Si NW sensors by by back back bias bias gate gate voltage, voltage, (d) (typicald) typical ID-VD ID of-V theD of fabricated the fabricated 10-μm-L 10-G p-typeµm-LG poly-Sip-type NW poly-Si NW sensors.sensors.

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The ID-VG and ID-VD curves of the SOI Si NW for 5-µm-LG, 10-µm-LG and 15-µm-LG are shown in Figure6, respectively. As can be seen from the images, smooth p-type MOSFET curves are achieved for the sensors fabricate at low temperature. The Ion/Ioﬀ ratios of 5-µm-LG, 10-µm-LG and 15-µm-LG Nanomaterials 2020, 10, x FOR PEER REVIEW 6 of 11 SOI Si NW devices are 1.47 108, 1.29 107 and 6.34 104, respectively, and extracted values of SSs × × × areare estimated estimated to to be be 686 686 mVmV/dec,/dec, 767 767 mV/dec mV/dec and and 1120 1120 mV/dec, mV/ respectively.dec, respectively. Figure 6d Figure depicts6d the depicts ID- the ID-VVDD curves of of the the 10- 10-μm-Lµm-LG poly-SiG poly-Si NWNW device. device.

FigureFigure 6. (6.a –(ac–)c typical) typical I DID-V-VGG curves of of the the fabricated fabricated 5-μ 5-m-Lµm-LG, 10-G,μ 10-m-Lµm-LG andG 15-andμm-L 15-µG m-Lp-typeG p-type SOI Si SOI Si NW sensors by back gate bias, respectively, (d) typical ID-VD curves of the fabricated 10-μm-LG p-type NW sensors by back gate bias, respectively, (d) typical ID-VD curves of the fabricated 10-µm-LG p-type SOISOI Si NWSi NW sensors. sensors.

FigureFigure7 shows 7 shows the the extracted extracted typicaltypical parameter comparison comparison between between the thepoly-Si poly-Si NW and NW SOI and Si SOI Si NW sensors, e.g., the threshold voltage (Vth), SS, on-stage current (Ion) and Ion/off ratio, respectively. NW sensors, e.g., the threshold voltage (Vth), SS, on-stage current (Ion) and Ion/off ratio, respectively. The Vths of 5-μm-LG, 10-μm-LG and 15-μm-LG poly-Si NW devices are −8.06 V, −8.125 V and −7.87 V, The Vths of 5-µm-LG, 10-µm-LG and 15-µm-LG poly-Si NW devices are 8.06 V, 8.125 V and 7.87 V, respectively. The Vth of 5-μm-LG, 10-μm-LG and 15-μm-LG SOI Si NW devices− are −7.67− V, −7.95 V and− respectively. The V of 5-µm-L , 10-µm-L and 15-µm-L SOI Si NW devices are 7.67 V, 7.95 V −7.8 V, respectively.th The valuesG of Vths of poly-siliconG devicesG with different LGs are similar− to those− andof the7.8 SOI V, respectively.devices. The values The of values SSs of of SOI V thdevicess of poly-silicon are smaller than devices those withof poly-Si different devices LG ands are the similar − to thoseIon/Ioff is of also the larger. SOI devices. The performance The values of SOI of devices SSs of is SOI slightly devices better are than smaller that of thanlow-temperature those of poly-Si devicespoly-silicon and the devices, Ion/Ioff whichis also is larger. caused Theby the performance monocrystalline of SOI silicon devices channel is slightly with a betterlow channel than that of low-temperatureresistance. The poly-siliconachieved results devices, imply which that the is causedpoly-Si byNW the sensors monocrystalline could be applied silicon for channel future with a lowmonolithic channel resistance. 3D-IC application The achieved. results imply that the poly-Si NW sensors could be applied for future monolithic 3D-IC application. Figure8 shows the typical sensing characteristics of the poly-silicon nanowire sensors by analyzing different stranded pH solutions. In the measurement of the ID-VG curve and the gate voltage was swept from 0 to 10 V by top solution (see Figure8a inserted image). The detection principle is to convert the − sensor surface potential change introduced by a different pH solution into the current change in the semiconductor Si NW channel. The actual amount of charges depends on the concentration of specific ions in the solution (the concentration of H+ ion in the manuscripts). Therefore, the pH of the solutions could modulate the surface charge of the insulator/semiconducting interface consequently, resulting in a shift of the threshold voltage. The scheme of the test using the top liquid gate is shown in the inserted figure of Figure8a. Due to the change of film surface potential of the channel, the poly-silicon nanowire sensors exhibit Vth shifts (see Figure8a). If the added solution is acidic (alkaline), the I D-VG curve will shift to the right (left). After adding different pH buffers, the real-time response of ID is shown in Figure8b. Taking the bu ffer solution with pH = 7 as a reference, when the pH buffer is acidic, a positive

Nanomaterials 2020, 10, 2488 7 of 11 charge is introduced and the current of the p-type poly-silicon nanowire sensor increases. When the pH buﬀer is alkaline, a negative charge is introduced and the current decreases. The results are consistent with the transfer curve of the p-type poly-silicon nanowire sensor increases. The extracted change values of Vth and ID as a function of pH values are shown in Figure8c,d, respectively. The changes of Vth and ID have approximate linearity with the pH values, and the sensitivity as high as about 178 1 mV/pH, which is caused by the small size in Si NW and large surface to volume ratio. ± Nanomaterials 2020, 10, x FOR PEER REVIEW 7 of 11

FigureFigure 7. Comparison 7. Comparison between between low-temperature low-temperature poly-s poly-siliconilicon devices devices and SOI and Si SOI NWSi devices. NW devices. (a) SS, (a) SS, (b) Vth, (c) Ion and (d) Ion/Ioff ratio. (b)Vth,(c)Ion and (d)Ion/Ioﬀ ratio. Nanomaterials 2020, 10, x FOR PEER REVIEW 8 of 11 Figure 8 shows the typical sensing characteristics of the poly-silicon nanowire sensors by analyzing different stranded pH solutions. In the measurement of the ID-VG curve and the gate voltage was swept from 0 to −10 V by top solution (see Figure 8a inserted image). The detection principle is to convert the sensor surface potential change introduced by a different pH solution into the current change in the semiconductor Si NW channel. The actual amount of charges depends on the concentration of specific ions in the solution (the concentration of H+ ion in the manuscripts). Therefore, the pH of the solutions could modulate the surface charge of the insulator/semiconducting interface consequently, resulting in a shift of the threshold voltage. The scheme of the test using the top liquid gate is shown in the inserted figure of Figure 8a. Due to the change of film surface potential of the channel, the poly-silicon nanowire sensors exhibit Vth shifts (see Figure 8a). If the added solution is acidic (alkaline), the ID-VG curve will shift to the right (left). After adding different pH buffers, the real-time response of ID is shown in Figure 8b. Taking the buffer solution with pH = 7 as a reference, when the pH buffer is acidic, a positive charge is introduced and the current of the p- type poly-silicon nanowire sensor increases. When the pH buffer is alkaline, a negative charge is introduced and the current decreases. The results are consistent with the transfer curve of the p-type poly-silicon nanowire sensor increases. The extracted change values of Vth and ID as a function of pH values are shown in Figure 8c,d, respectively. The changes of Vth and ID have approximate linearity with the pH values, and the sensitivity as high as about 178 ± 1 mV/pH, which is caused by the small size in Si NW and large surface to volume ratio.

Figure 8.Figure(a) 8. The (a) The transfer transfer curves curves ofof the poly-Si poly-Si NW NW sensor sensor by analyzing by analyzing different di pHfferent solutions, pH ( solutions,b) real-time response of ID when adding different pH solutions, the inserted figure the transfer curves of (b) real-time response of ID when adding different pH solutions, the inserted figure the transfer the bias back gate voltage, (c,d) threshold voltage and drain current change under different pH curves of the bias back gate voltage, (c,d) threshold voltage and drain current change under different solutions. pH solutions. Figure 9 shows the typical sensing characteristics of the SOI nanowire sensors by analyzing different stranded pH solutions. In the measurement of the ID-VG curve, the gate voltage was swept

from 0 to −4 V by the top solution. Figure 9a shows that the threshold voltage shifts with the pH of the solution. The extracted threshold change is linear with the pH of the solution (see Figure 9b). A similar trend of Vth shift is obtained, but the values of changes are only about a fifth of the poly-silicon nanowire.

Figure 9. (a) The transfer curves of the silicon-on-insulator (SOI) sensor with different pH solutions, (b) threshold voltage under different pH solutions.

Table 1 shows system parameters comparison of the relevant reported results in recent years and our fabricated poly-silicon nanowire sensors. The SIT technique is used to form poly-silicon NW sensor arrays with 25 nm in width and 35 nm in length, which exhibits high efficiency and low cost than that of formed by EBL. Furthermore, the resistance and the device performance- the poly-silicon

Nanomaterials 2020, 10, x FOR PEER REVIEW 8 of 11

Figure 8. (a) The transfer curves of the poly-Si NW sensor by analyzing different pH solutions, (b)

real-time response of ID when adding different pH solutions, the inserted figure the transfer curves of the bias back gate voltage, (c,d) threshold voltage and drain current change under different pH solutions. Nanomaterials 2020, 10, 2488 8 of 11

Figure 9 shows the typical sensing characteristics of the SOI nanowire sensors by analyzing differentFigure stranded9 shows pH the solutions. typical sensingIn the measurement characteristics of ofthe the ID-V SOIG curve, nanowire the gate sensors voltage by was analyzing swept fromdiﬀerent 0 to stranded−4 V by the pH top solutions. solution. In Figure the measurement 9a shows that of thetheI Dthreshold-VG curve, voltage the gate shifts voltage with wasthe pH swept of thefrom solution. 0 to 4 VThe by extracted the top solution. threshold Figure change9a shows is linear that with thethreshold the pH of voltage the solution shifts with(see Figure the pH 9b). of the A − similarsolution. trend The of extracted Vth shiftthreshold is obtained, change but the is linearvalues with of changes the pH are of the only solution about (seea fifth Figure of the9b). poly-silicon A similar nanowire.trend of Vth shift is obtained, but the values of changes are only about a ﬁfth of the poly-silicon nanowire.

FigureFigure 9. 9. ((aa)) The The transfer transfer curves curves of of the the si silicon-on-insulatorlicon-on-insulator (SOI) (SOI) sensor sensor with with different diﬀerent pH pH solutions, solutions, ((bb)) threshold threshold voltage voltage under under different diﬀerent pH solutions.

TableTable 11 showsshows systemsystem parametersparameters comparisoncomparison ofof thethe relevantrelevant reportedreported resultsresults inin recentrecent yearsyears andand our our fabricated fabricated poly-silicon poly-silicon nanowi nanowirere sensors. The The SIT SIT technique technique is is used used to to form form poly-silicon poly-silicon NW NW sensorsensor arrays arrays with with 25 25 nm nm in in width width and and 35 35 nm nm in in length, length, which which exhibits exhibits high high efficiency eﬃciency and and low low cost cost thanthan that that of of formed formed by by EBL. EBL. Furthe Furthermore,rmore, the the resistance resistance and and the the devic devicee performance- performance- the the poly-silicon poly-silicon NW sensor is greatly improved by introducing SBSD techniques, which is attributed to achieve a larger

Ion/Ioﬀ ratio and smaller values of SSs. The results indicate that the poly-silicon NWs sensor fabricated by low-temperature annealing has much better characteristics than those of the sensors prepared by other methods, which attributed to its application for future monolithic 3D-IC applications.

Table 1. A comparison of silicon nanowire sensors in recent years.

2011 [30] 2012 [31] 2014 [32] 2016 [33] 2020 [34] This Work

Insulation material SiO2 SiNx SiO2 SiO2/Si3N4 SiO2/Si3N4/SiO2 SiO2 SOI Insulation thickness 100 nm - 80 nm 50/65 nm -/150/7 nm 145 nm NWs material Si Si poly-Si poly-Si poly-Si poly-Si Si Si NWs fabrication VLS RIE sidewall spacer RIE EBL SIT SIT approach

Processing temperature - - - 600 ◦C 1050 ◦C 600 ◦C 600 ◦C NWs size ~90 nm - - ~40 nm 40~50 nm ~30 nm ~30 nm

LG - - 100 nm 10 µm 400 nm 10 µm 10 µm 5 4 5 5 6 7 Ion/I ~10 ~10 - 2.03 10 2.5 10 2.84 10 1.29 10 oﬀ × × × × SS (mV/dec) 2500 2300–3000 - 975 1030 965 767

Vth change (V) - - 0.087 0.0437 - 0.178 0.0688

4. Conclusions In summary, low cost poly-Si NW sensors arrays are fabricated through an advanced SIT process with high efficiency than that formed by electron beam lithography, and the morphology of Si NW is well controlled with small sizes. Furthermore, a low-temperature flow (600 ◦C) with silicide and implantation is designed and carried out. Benefiting from the silicide and isolation processes, the poly-Si NW FET sensors show six orders of magnitude in switching ratio and a SS of 965 mV/dec, which is similar to the counterpart of the SOI Si NW sensor. In addition, the poly-Si NW FET sensors Nanomaterials 2020, 10, 2488 9 of 11 show the V shift as high as about 178 1 mV/pH, which is five times larger than that of the SOI Si th ± NW sensors. Therefore, the design and fabricated poly-Si NW sensor arrays approach provides a good option for its potential application of the monolithic 3D-ICs in the future.

Author Contributions: Conceptualization, S.T., Q.Z., J.Z., J.Y. (Jiang Yan); methodology, S.T., Q.Z., J.Z., J.L., S.W., Y.W., Z.Z., Q.W., H.Y., J.Y. (Jianglan Yang), M.F., S.Z., E.X.; data curation, S.T. and Q.Z.; writing original draft preparation, S.T.; writing review and editing, S.T., Q.Z. and Z.Z.; supervision, W.W., J.Y. (Jiang Yan) and H.T.; project administration, W.W.; funding acquisition, W.W. All authors have read and agreed to the published version of the manuscript. Funding: This work was supported in part by the Natural Science Foundation of Beijing, China (4182021), the Science and technology program of Beijing Municipal Science and Technology Commission under grants Z201100006820084 and Z201100004220001, in part by the National Key Project of Science and Technology of China under grant 2017ZX02301007-001 and 2017ZX02315001-001, the Youth Innovation Promotion Association, Chinese Academy of Sciences under grant Y9YQ01R004, the National Natural Science Foundation of China under grants 61874002 and 61904194, and 6187032253, and in part by the Opening Project of Key Laboratory of Microelectronic Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences under Grant Y9YS05X002 and E0YS01X001. Acknowledgments: We thank the Integrated Circuit Advanced Process Center (ICAC) at the Institute of Microelectronics of the Chinese Academy of Sciences for the devices fabricated on their advanced 200 mm CMOS platform. Conﬂicts of Interest: The authors declare no conﬂict of interest.

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