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Fabrication of Low Cost and Low Temperature Poly-Silicon Nanowire Sensor Arrays for Monolithic Three-Dimensional Integrated Circuits Applications

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Fabrication of Low Cost and Low Temperature Poly-Silicon Nanowire Sensor Arrays for Monolithic Three-Dimensional Integrated Circuits Applications nanomaterials Article Fabrication of Low Cost and Low Temperature Poly-Silicon Nanowire Sensor Arrays for Monolithic Three-Dimensional Integrated Circuits Applications Siqi Tang 1,2, Jiang Yan 1,*, Jing Zhang 1, Shuhua Wei 1, Qingzhu Zhang 2 , Junjie Li 2 , Min Fang 1, Shuang Zhang 1, Enyi Xiong 1, Yanrong Wang 1, Jianglan Yang 3, Zhaohao Zhang 2,*, Qianhui Wei 3,*, Huaxiang Yin 2,4 , Wenwu Wang 2,4 and Hailing Tu 3 1 School of Information Science and Technology, North China University of Technology, Beijing 100144, China; [email protected] (S.T.); [email protected] (J.Z.); [email protected] (S.W.); [email protected] (M.F.); [email protected] (S.Z.); [email protected] (E.X.); [email protected] (Y.W.) 2 Advanced Integrated Circuits R&D Center, Institute of Microelectronic of the Chinese Academy of Sciences, Beijing 100029, China; [email protected] (Q.Z.); [email protected] (J.L.); [email protected] (H.Y.); [email protected] (W.W.) 3 State Key Laboratory of Advanced Materials for Smart Sensing, General Research Institute for Nonferrous Metals, Beijing 101402, China; [email protected] (J.Y.); [email protected] (H.T.) 4 School of Microelectronics, University of Chinese Academy of Sciences, Beijing 100049, China * Correspondence: [email protected] (J.Y.); [email protected] (Z.Z.); [email protected] (Q.W.); Tel.: +86-010-8880-2600 (J.Y.) Received: 4 November 2020; Accepted: 7 December 2020; Published: 11 December 2020 Abstract: In this paper, the poly-Si nanowire (NW) field-effect transistor (FET) sensor arrays were fabricated by adopting low-temperature annealing (600 ◦C/30 s) and feasible spacer image transfer (SIT) processes for future monolithic three-dimensional integrated circuits (3D-ICs) applications. Compared with other fabrication methods of poly-Si NW sensors, the SIT process exhibits the characteristics of highly uniform poly-Si NW arrays with well-controlled morphology (about 25 nm in width and 35 nm in length). Conventional metal silicide and implantation techniques were introduced to reduce the parasitic resistance of source and drain (SD) and improve the conductivity. Therefore, the obtained sensors exhibit >106 switching ratios and 965 mV/dec subthreshold swing (SS), which exhibits similar results compared with that of SOI Si NW sensors. However, the poly-Si NW FET sensors show the V shift as high as about 178 1 mV/pH, which is five times larger than that of th ± the SOI Si NW sensors. The fabricated poly-Si NW sensors with 600 ◦C/30 s processing temperature and good device performance provide feasibility for future monolithic three-dimensional integrated circuit (3D-IC) applications. Keywords: silicon nanowire (Si NW); monolithic three-dimensional integrated circuits (M3D-ICs); spacer image transfer (SIT); sensitivity 1. Introduction In recent years, the application of semiconductor field-effect transistors (FET) sensors have attracted a lot of attention because of their ability to translate the interaction with target molecules on the FET surface to an electrical signal directly [1–4]. Silicon nanowires (Si NW) sensors have been considered as one of the most promising candidates for biochemical sensors [5–9], due to their large surface to volume (S/V) ratio, high sensitivity, and good biocompatibility [10,11]. In recent years, Nanomaterials 2020, 10, 2488; doi:10.3390/nano10122488 www.mdpi.com/journal/nanomaterials Nanomaterials 2020, 10, x FOR PEER REVIEW 2 of 11 Nanomaterials 2020, 10, 2488 2 of 11 NW field-effect-transistor (FET) sensors have been used for the very high sensitivity detection of pH [12–14],Si NWgases field-e [15–17]ffect-transistor and DNA (FET)[18–20]. sensors However, have been the conventional used for the very fabrication high sensitivity process detection with silicon- of on-insulatorpH [12– (SOI)14], gases materials [15–17 is] andcomplex DNA and [18– high-c20]. However,ost, and the nanometer conventional pa fabricationtterns are processusually withformed by traditionalsilicon-on-insulator low-efficiency (SOI) materialselectron is beam complex lith andography high-cost, (EBL) and process, the nanometer which patterns does arenot usuallymeet the demandsformed of future by traditional mass production low-efficiency with electron a low beam cost lithography and low efficiency. (EBL) process, The whichspacer does image not meettransfer (SIT) theprocess demands (also of named future mass self-aligned production double with a or low quadruple cost and low patterning) efficiency. Thecould spacer achieve image nanometer transfer array (SIT)with processhigh efficiency (also named and self-aligned low cost, which double are or quadruple widely used patterning) in foundries could achieve[21–23]. nanometer In addition, array there are nowith reports high effionciency the design and low or cost, fabrication which are widelyof Si NW used sensors in foundries for [monolithic21–23]. In addition, three-dimensional there are integratedno reports circuits on the(3D-ICs) design orapplication, fabrication ofwhich Si NW is sensorsone of forthe monolithic most convincing three-dimensional candidates integrated for future circuits (3D-ICs) application, which is one of the most convincing candidates for future application application (see Figure 1). In order to achieve better performance of the system, the fabrication of top (see Figure1). In order to achieve better performance of the system, the fabrication of top devices devices (Si NW sensor) usually need low-temperature processes to avoid a degradation on (Si NW sensor) usually need low-temperature processes to avoid a degradation on characteristics of characteristicsbottom circuits of bottom (logic circuits circuits (logic and memory circuits in and Figure memory1)[ 24]. in However, Figure 1) there [24]. areHowever, no reports there on theare no reportsdesign on the or design fabrication or fabrication of Si NW sensor of Si for NW monolithic sensor for 3D-ICs monolithic application. 3D-ICs application. FigureFigure 1. Illustration 1. Illustration of ofmonolithic monolithic three-dimensionalthree-dimensional integrated integrated circuits ci (3D-ICs):rcuits (3D-ICs): bottom logic bottom circuits; logic circuits;middle middle memory memory and topand silicon top si nanowirelicon nanowire (Si NW) (Si sensors. NW) sensors. In this paper, poly-silicon NW sensors with low cost and high efficiency are designed and fabricated In this paper, poly-silicon NW sensors with low cost and high efficiency are designed and using advanced spacer image transfer (SIT) [22–24] and low-temperature silicide techniques for fabricated using advanced spacer image transfer (SIT) [22–24] and low-temperature silicide monolithic 3D-IC application. The highest annealing temperature is not over 600 ◦C, which overcomes techniquesthe problems for monolithic of overheating 3D-IC the application. bottom transistor The andhighest the wires. annealing The achieved temperature poly-silicon is not NW over sensors 600 °C, whichhave overcomes good electrical the problems properties, of such overheating as over six ordersthe bottom of magnitude transistor in on-o andff ratiothe wires. and 932 The mV /achieveddec of poly-siliconsubthreshold NW sensors swing (SS) have by good bias back-gate electrical voltages. properties, such as over six orders of magnitude in on- off ratio and 932 mV/dec of subthreshold swing (SS) by bias back-gate voltages. 2. Materials and Methods 2. MaterialsTwo and types Methods of Si NW sensors (poly-silicon and silicon-on-insulator (SOI)) were designed and fabricated, and the detailed fabrication flow is illustrated in Figure2. The poly-silicon NW sensors were Two types of Si NW sensors (poly-silicon and silicon-on-insulator (SOI)) were designed and manufactured on p-type 200 mm Si (100) silicon wafers (see Figure2a): Firstly, 145 nm SiO 2 and 40 nm fabricated,poly-silicon and the were detailed deposited, fabrication respectively flow (see is Figureillustrated2b). The in SOIFigure Si NW 2. The sensors poly-silicon were manufactured NW sensors were manufacturedon 200 mm SOI waferson p-type featured 200 mm with Si a 145-nm-thick(100) silicon buriedwafers oxide (see Figure layer (BOX) 2a): Firstly, and a 40-nm-thick 145 nm SiO top2 and 40 nmsilicon poly-silicon layer. The were fabrication deposited, process respectively of the two types (see of devicesFigure was2b). allThe the sameSOI Si in theNW flowing sensors steps. were manufacturedDuring the on fabrication 200 mm ofSOI the wafers Si NWs, featured a spacer imagewith transfera 145-nm-thick (SIT) technology buried wasoxide chosen layer to (BOX) form NW and a 40-nm-thickarrays patterns top silicon with layer. high eThefficiency fabrication [25–27], process and the detailedof the two fabrication types of process devices flow was is describedall the same as in the flowingfollows: steps. sequential During multi-layer the fabrication SiO2/amorphous of the Si NWs, Si (α-Si) a spacer/Si3N4 filmsimage were transfer deposited (SIT) (see technology Figure2c). was chosenNext, to form the conventionalNW arrays pattern photolithographys with high process efficiency (i-line) [25–27] and dry, and etching the detailed processes fabrication were used process to form rectangular arrays of Si N and α-Si films (see Figure2d). The top Si N hard masks (HMs) flow is described as follows: sequential3 4 multi-layer SiO2/amorphous Si 3 (α4-Si)/Si3N4 films were were removed by a hot H PO solution at 140 C (see Figure2e). A 30 nm Si N film was deposited by deposited (see Figure 2c). Next,3 4 the conventional◦ photolithography process3 4 (i-line) and dry etching processes were used to form rectangular arrays of Si3N4 and α-Si films (see Figure 2d). The top Si3N4 hard masks (HMs) were removed by a hot H3PO4 solution at 140 °C (see Figure 2e). A 30 nm Si3N4 film was deposited by plasma-enhanced chemical vapor deposition (PECVD) approach and then the corresponding Si3N4 reactive ion etching (RIE) was performed to form two SiNx spacers on both sides of α-Si (see Figure 2f,g).
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