22Nm Ultra-Thin Body and Buried Oxide FDSOI RF Noise Performance

RMo1B-5 22nm Ultra-Thin Body and Buried Oxide FDSOI RF Noise Performance

Ousmane M. Kane#1, Luca Lucci$, Pascal Scheiblin$, Sylvie Lepilliet*, François Danneville* #CEA Leti, Lille University, France $CEA Leti, France *CNRS, Université Lille, ISEN, Université Valenciennes, UMR 8520 - IEMN, Lille, France [email protected]

Abstract—The drastic downscaling of the transistor size along lower Cgg capacitance and a higher transconductance, resulting with advances in material sciences allowed the development of low from enhanced stress response [4]. Each NMOS device was power CMOS technologies with competitive RF figure of merits accompanied by a dedicated open and short structure for de- suitable for millimeter applications. In this context, this paper embedding at lower metal reference plane and all of these presents the RF and noise characterization (up to 110 GHz) of an transistors were characterized. But, a selected device, whose advanced 22 nm UTBB FDSOI technology developed by Globalfoundries. In addition to the excellent DC performance, the dimensions are reported in Table 1, was chosen for this paper. technology presents promising RF characteristics. Indeed, a Table 1. Device geometry maximum transconductance of 1.78 S/mm and a Fmax of 435 GHz are achieved. The technology also offers a state-of-the-art Gate length Unit gate finger Number of gate Total gate width minimum noise figure (NFmin) of 0.45 dB at 20 GHz (with an (Lg) [nm] width (Wf) [µm] fingers (Nf) (Wtot) [µm] associated Gain of 13 dB) for a drain current of 185 mA/mm. 18 0.3 192 57.60 Keywords— CMOS, FDSOI, noise measurement, millimeter wave. Poly I. INTRODUCTION pitch Increasing demand in wireless telecommunication combined with low power consumption for internet-of-things (IoT) applications require the development of new electronic devices. In this context, a CMOS technology of interest is the 22 nm ultra-thin body and back-oxide (UTBB) fully-depleted silicon-on-insulator (FDSOI) technology from Globalfoundries (22FDX). Fig. 1.a shows an illustrative cross section for a NMOS. a. b. Work reported in [1-3] already showed competitive RF Fig. 1. (a) Typical cross section of a 22 nm FDSOI [2] (b) FET layout schematic performances for this technology in millimeter wave (mmW) showing gate poly pitch. applications, including IoT, 5G, and radar. In [1-3], values for The drain current and the transconductance as a function of the transit frequency (F ) and the maximum oscillation t gate voltage are shown in Fig. 2. A maximum DC normalized frequency (F ) were already extracted. Though such figure- max drain current of 787 mA/mm and a maximum DC of-merit were reported, this paper focuses not only on the radio transconductance of 1.78 S/mm are obtained. frequency performance, but also on broadband noise one. This paper is organized as follows. The second section presents the device geometry for the best selected NMOS transistor, and its DC and RF (Ft, Fmax) performance. The third section focuses on the extraction of the small signal equivalent circuit (SSEC) as well as the extraction of the drain noise temperature. In section four, a presentation of the noise performance and a validation of this extraction in mmW range is shown. This paper ends with a benchmarking of the CMOS 22 nm UTBB FDSOI with the state-of-the-art.

II. DC AND RF PERFORMANCE Many NMOS transistors have been measured having different unit finger widths varying between 0.3 µm and 1.07 µm. Also devices with relaxed poly pitch (Fig. 1.b) were Fig. 2. Drain current (Id) and transconductance (Gm) as a function of gate voltage (Vg) for a drain-source voltage Vds=0.8 V. measured; this has a considerable impact on Ft because of a

978-1-7281-1701-0/19/$31.00 © 2019 IEEE 35 2019 IEEE Radio Frequency Integrated Circuits Symposium For the RF characterization, S parameters are measured up proportional to an input equivalent noise temperature Tin and to 50 GHz using Keysight network analyser PNAX N5245B. A ഥଶ ଓௗ is proportional to an output equivalent noise temperature Tout. short-open-load-reciprocal thru calibration is performed to Tin is usually set to room temperature. In order to extract Tout bring the reference plane to the probe tips. For the de- through 50 Ω noise figure data (NF50), the lumped equivalent embedding of the pad and metallic interconnections circuit of the pads and metallic interconnections surrounding contribution, a Pad-Short-Open (PSO) de-embedding [6] is the device, which are modeled using the PSO de-embedding performed, a simple Open-Short (OS) de-embedding not being procedure, must be added to the small signal model appropriate for our types of device structures. (represented by DUT in Fig. 5, which shows the model that was As it is shown in Fig. 3, peak Ft/Fmax of 332/435 GHz are used). The values of the different elements are given in Table 2. extracted from current gain (H21) and mason gain (U) at a drain current of Id=347mA/mm (this current density approximately corresponds to the maximum of the DC transconductance).

-20 dB/decade Fig. 5. Equivalent model of the pads and interconnections (shows the reference plane for NF50 measurement). Fmax > 400GHz

Table 2. Impedance and admittance values of the pads and interconnections Ft ~ 332GHz Cpad1 Cpad3 Cvias1 Cvias2 Cvias3 Ls1 Ls3 fF pH 44 41.6 29 19.7 34.5 27 30

Fig. 3. Current gain (H21) and Mason gain (U) at Id=347mA/mm

III. RF SSEC AND NOISE MODEL EXTRACTION A. RF SSEC Extraction The small signal equivalent circuit (SSEC) of the transistor, The SSEC was extracted using the methodology described which includes the HF noise sources in chain representation, is in [5] and [7]. The series resistances (Rg, Rs, Rd) are extracted given in Fig. 4. The F50 method [15] was used to extract Tout; first at cold bias (Vds=0V). The values of the extrinsic and intrinsic elements are given in Table 3. once Tout is determined, the four noise parameters (NFmin, Rn, Γopt) of the transistor are known. Note that an accurate SSEC is Table 3. Extrinsic and intrinsic parameters values of the transistor required for this method (we shall return to this point in section Rg Rd Rs Lg Ld Ls Cpd Cpg III.B). The noise figure was measured with the PNAX N5245B, Ω pH fF which has an integrated noise source at its port 2. And the noise 5.78 1.38 1.02 0.5 0.5 1.31 9.5 5.6 calibration was done using the Keysight power meter U8487A.

Cgd Cgs gm gd Ri fF mS Ω 14.52 38.81 121 7 4

The voltage gain of the transistor (gm/gd) is equal to 17, signature of an excellent channel control. Values for the residual capacitances after de-embedding (Cpg and Cpd) are due to the multiplicity of cells for the RF device, which is equal to 6 (because of the large number of fingers). As observed in Fig. 6, Cpg and Cpd are almost flat over the entire frequency range using a PSO de-embedding. The SSEC with the pads and metallic interconnection Fig. 4. MOSFET SSEC including noise sources. models has been implemented on Agilent Advanced Design Systems (ADS) software and S parameters were simulated up For noise temperature extraction Pospiezalski’s noise to 50 GHz. Fig. 7 presents a comparison of the S parameters model [11-12] was used. The thermal noise of the device is between measurement and ADS simulation. A good agreement modeled by two uncorrelated noise sources: an input voltage is obtained up to 50 GHz. തതଶത ഥଶ തതଶത noise source (݁௚ ) and an output current noise source (ଓௗ). ݁௚ is

36 curve is used to tune Tout until the simulated NF50 (using ADS) reproduces NF50 measured data (in shape and magnitude). This process is repeated and validated for different drain currents. It is important to point out that the NF50 measurement reference planes are at the probe tips (Fig. 5). The resulting Tout as function of Id is shown in Fig. 8. Tout increases monotonically from 780 K to 1860 K, when Id increases from 100 to 800 mA/mm. These values are comparable results extracted in Bulk technologies [8].

IV. NOISE PERFORMANCE, ROBUSTNESS OF THE EXTRACTION

The extraction of Tout allows to extract the four noise Fig. 6. Cpd and Cpg versus frequency after a Pad-Short-Open (PSO) parameters. In Fig. 9, the minimum noise figure (NFmin) and the deembedding and after an Open-Short (OS) deembedding. associated gain (Gassoc) are reported as a function of drain current @ 20 GHz, while the equivalent noise resistance (Rn) is reported in Fig. 10 and the optimum source admittance (Γopt) is reported in Fig. 11. The lowest values for NFmin/Rn, 0.45 dB/17 Ω are obtained for Id=185mA/mm. For this current, the associated gain is almost at its maximum (13 dB).

S22 S11

S21 S12

Fig. 9. Minimum noise figure and associated gain versus Id @ 20 GHz

Fig. 7. S parameters comparison between measurement and ADS simulation B. Tout Extraction തതଶത After the validation of the SSEC, the two noise sources (݁௚ ഥଶ and ଓௗ ) were added to the circuit with Tin set to room temperature. In order to determine Tout, the NF50 measurement

Fig. 10. Equivalent resistance versus Id @ 20 GHz

In order to check the validity of the extraction, NF50 measurements were performed in W band. The measurement was done with the instruments presented in [14]. Fig. 12 shows that the simulated NF50 data (using ADS) in W band compares well with measured data, which validates the robustness of our noise extraction. Fig. 8. Tout as a function of Id

37 VI. CONCLUSION In this paper, a high frequency noise characterization of the 22 nm FDSOI technology, preceded by its SSEC extraction, was presented and validated up to 110 GHz. The device achieves a Ft/Fmax of 332/435 GHz, and very good noise properties with an NFmin/Rn of 0.45dB/17Ω @ 20 GHz for a drain current of 185 mA/mm, and an associated gain of almost 13 dB.

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Fig. 13. Benchmarking with previous CMOS