FD-SOI OFFERS ALTERNATIVE TO FINFET GlobalFoundries Leads With Cost-Sensitive Manufacturing Option By Linley Gwennap (August 15, 2016) ................................................................................................................... Although many high-performance chips have forged The Second Coming of SOI ahead to expensive FinFET manufacturing nodes, others SOI has been in production since the 1990s (see MPR continue to use 28nm planar technology because of its low 8/24/98, “SOI to Rescue Moore’s Law”). IBM brought the cost per transistor. But these latter products have been industry’s first SOI-based processors to production in stuck at 28nm, in some cases for years, without any man- 2000, and AMD adopted the technology for all of its x86 ufacturing options for improving their cost or power. With microprocessors starting in 2001. Since then, IBM has Moore’s Law breached, GlobalFoundries is offering a new continued to use SOI for many of its internal processors technology that could fill this gap. and also in its ASIC offerings, including processors for the FD-SOI is a variant of silicon-on-insulator (SOI) tech- PlayStation 3, Xbox 360, and Wii game consoles. AMD nology that adds a very thin oxide layer beneath the silicon steadfastly rode the technology from 130nm all the way transistor, as Figure 1 shows, greatly reducing leakage cur- down to 32nm. After spinning off from AMD (see MPR rent versus traditional bulk CMOS. The new SOI version 9/27/10, “GlobalFoundries Pushes Boundaries”), Global- requires no doping in the channel, making it fully depleted Foundries continued to manufacture AMD’s SOI designs. (FD). It also enables operation at lower voltages than planar It recently acquired IBM’s fabs, giving it additional SOI CMOS transistors can achieve, reducing active power. resources. As a planar (flat) technology, FD-SOI requires fewer Instead of building directly on a bulk silicon wafer, processing steps than FinFET nodes to form the transistor; SOI starts with a wafer that is topped with a layer of silicon it also requires less double patterning. As a result, the pro- oxide (an insulator). Another silicon layer (typically cessing cost for FD-SOI is lower. Although the SOI wa- 150nm thick) is placed on the insulator before the wafer fers are much more expensive than plain CMOS wafers, ships to the foundry, which constructs the transistors and GlobalFoundries says its 22nm FD-SOI process, called other circuits in the usual fashion. Owing to the process of 22FDX, can deliver lower die cost than 16nm FinFET. The new process is similar in die Bulk FD-SOI CMOS cost to 28nm HKMG while greatly reducing Gate Gate power. Source e- Drain Source e- Drain These advantages make 22FDX particu- Ultrathin Buried Oxide larly appealing for many IoT products that require the lowest possible cost but must also minimize power. In addition, the technology has some interesting analog characteristics. Figure 1. Traditional CMOS versus FD-SOI. As a bulk-CMOS transistor gets Samsung and STMicroelectronics also offer smaller, electrons can jump from the source to the drain even when the gate FD-SOI, but neither TSMC nor Intel favors is off, creating leakage current. In the FD-SOI transistor, the buried oxide this approach. layer blocks most of the leakage. © The Linley Group • Microprocessor Report August 2016 2 FD-SOI Offers Alternative to FinFET adding the extra layers, SOI wafers cost considerably more. Lower Power Than Planar CMOS Soitec (pronounced “soy-tek”), the leading manufacturer A major benefit of FD-SOI is its low power. Because the of SOI wafers, declines to publish its prices, but we esti- circuit need not charge the source/drain capacitance, the mate them at $400–$500, as opposed to about $130 for a total dynamic power falls. Furthermore, unlike ST’s original bulk wafer. FD-SOI design, 22FDX uses a compressively strained chan- From an electrical standpoint, the oxide barrier com- nel in the PFETs as well as raised source drains in both the pletely isolates the transistor body from the base substrate NFETs and PFETs. These optimizations reduce power by (ground). The floating body can thus accumulate charge up to 55% compared with 28nm FD-SOI at the same fre- over time, changing its threshold voltage. Removing the quency. GF has tested 22FDX designs down to 0.3V oper- dopant from the channel (thereby fully depleting it) elimi- ation, although it has determined the minimum power oc- nates its ability to hold charge, solving the floating-body curs at 0.4V because leakage current begins to dominate problem. But undoped transistors are highly sensitive to below that point. Even so, 0.4V compares favorably with variations in the silicon-layer thickness. To simplify man- 28nm LP transistors, which typically reach minimum pow- ufacturing, IBM and AMD originally implemented a par- er at 0.65V. tially depleted (PD) channel, but the floating-body effect Operating the transistors at this low voltage requires complicated the circuit design of their PD-SOI processors. body biasing. As Figure 2 shows, applying a bias voltage to On the plus side, the insulating layer greatly reduces the substrate below the transistor affects the voltage of the source and drain capacitance, minimizing the power spent body, causing the transistor to switch at a lower effective charging these capacitors. As a result, in early PD-SOI voltage. (Bulk-CMOS processes also employ body bias, but nodes such as 180nm, dynamic (switching) power dropped the effect is smaller.) The use of body biasing is optional in by about 50% at the same speed, or the speed increased by 22FDX, as the bias generators and extra routing add 2–3% 25%. As transistors shrank over time, however, so did PD- to the die area. A forward bias (positive voltage) reduces SOI’s benefits; the speed gain is negligible at 28nm. the threshold voltage (thereby raising the switching speed) More recently, Soitec developed a technique to de- but increases leakage current, whereas a reverse bias re- posit a much thinner (e.g., 15nm) silicon layer with just duces static leakage when high performance is unnecessary. 3% variance (5 angstroms). To take advantage of this work, A chip can dynamically adjust the bias voltage—for ex- the French company began working with a local partner, ample, when it enters a low-power sleep mode—to optimize STMicroelectronics, to develop a complete manufacturing power consumption. process. The highly consistent silicon thickness enabled ST Like some other GF processes, 22FDX is constructed to fully deplete the channel. In 2014, the company de- gate first. This approach simplifies analog integration, ployed the new 28nm FD-SOI process in its Crolles making the technology well suited to mixed-signal SoCs. (France) fab, licensing the technology to Samsung as a sec- Although some gate-first processes have suffered yield ond source. problems, GF expects the defect rate (per mm2) will be GlobalFoundries (GF) also licensed ST’s FD-SOI similar for 22FDX and its previous 28nm HKMG node. technology. But instead of bringing it directly to produc- The combination of gate-first design and SOI also tion, GF melded the technology with its own SOI devel- improves certain analog characteristics. For example, the opments and advanced fabrication techniques to create a process has a high ratio of transconductance to drive cur- 22nm FD-SOI process. It expects to achieve low-volume rent (Gm/I), reducing power in circuits such as power am- production in 1Q17, with initial customer products enter- plifiers and RF dividers. Furthermore, the faster transistors ing full production around 2H17. are well suited to high-frequency RF signals. GF has meas- ured a maximum oscillation frequency (Fmax) in excess of 310GHz, and it expects further improvement. RF transis- Gate tors must operate at 3x to 5x the base frequency, so 22FDX Bias can easily handle millimeter-wave applications such as the Voltage new 5G radio (see MCR 8/8/16, “U.S. Government Acts Source Drain on 5G”), satellite communications, microwave backhaul, Ultrathin Buried Oxide and radar. Less Expensive Than FinFETs Despite its prior focus on PD-SOI, GlobalFoundries has developed bulk-CMOS processes at the 28nm node and beyond. Its first FinFET offering, a 14nm technology that it Figure 2. Body bias in FD-SOI. Applying a bias voltage can licensed from Samsung, is now in production, with cus- reduce the threshold voltage of the transistor, causing it to tomer products ramping later this year. The company switch faster. plans to skip 10nm and deploy a 7nm FinFET process that © The Linley Group • Microprocessor Report August 2016 FD-SOI Offers Alternative to FinFET 3 is scheduled for production by the end of 2018, with cus- tomer products ramping in 2019. These advanced nodes Price and Availability target high-performance devices such as AMD’s PC pro- GlobalFoundries’ 22FDX process is expected to be- cessors, but the cost of achieving this performance level gin risk production 4Q16; full production is expected in continues to rise. 1Q17, leading to customer volume production in 2H17. The 22nm FD-SOI process logically fits between GF’s The company withheld wafer pricing. For more informa- 28nm and 20nm technologies. Compared with 28SLP (a tion, access www.globalfoundries.com/22fdx. 28nm HKMG process), 22FDX reduces the gate pitch by 9% to 104nm, a size that a single patterning cycle (litho- etch) can still manage. The new technology offers a total of FD-SOI Gains Design Wins eight metal layers. The only two layers in the entire process Over the past two decades, PD-SOI technology made some that require double patterning are the first two metal layers, progress but never achieved widespread adoption. Back which have an 80nm pitch, as Table 1 shows.