State-Of-The-Art and Future of Silicon on Insulator Technologies, Materials, and Devices Sorin Cristoloveanu *

Microelectronics Reliability 40 (2000) 771±777 www.elsevier.com/locate/microrel

State-of-the-art and future of silicon on insulator technologies, materials, and devices Sorin Cristoloveanu *

Laboratoire de Physique des Composants a Semiconducteurs (UA±CNRS & INPG), ENSERG, B.P. 257, 38016 Grenoble Cedex 1, France

Abstract The context of SOI technologies is brie¯y presented in terms of wafer fabrication, con®guration/performance of typical SOI devices, and operation mechanisms in partially and fully depleted MOSFETs. The future of SOI is ten- tatively explored, by discussing the further scalability of SOI transistors as well as the innovating architectures proposed for the ultimate generations of SOI transistors. Ó 2000 Elsevier Science Ltd. All rights reserved.

1. Introduction 2. Synthesis of SOI wafers

Silicon on insulator (SOI) technology, originally de- In the last 20 years, a variety of SOI structures have veloped for the niche of radiation-hard circuits, has ex- been conceived with the aim of separating, using a perienced three decades of continuous improvement in buried oxide (BOX), the active device volume from the material quality, device physics, and processing. Re- Si substrate. cently, SOI has joined the microelectronics roadmap: Silicon-on-sapphire (SOS, Fig. 1a1) is fabricated by SOI circuits are indeed attractive because of their epitaxial growth of a Si ®lm on Al2O3. The electrical enhanced performance (higher speed, lower power- properties may suer from lateral stress, in-depth inho- voltage) and scalability. mogeneity of the ®lm, and defective transition layer at The aim of this article is to provide a synthetic view the interface [1,2]. SOS ®lms have been improved by of the present status and future developments in SOI solid-phase epitaxial regrowth (implantation-induced technologies and devices. The fabrication methods for amorphisation and annealing). Good quality 100 nm SOI materials and the family of SOI devices will be re- thick ®lms, on 600 SOS wafers [3], are now available. The viewed in Sections 2 and 3, respectively. Section 4 will be `in®nite' thickness of the insulator renders SOS prom- dedicated to the main mechanisms involved in the op- ising for the integration of RF (66 MHz, low noise [3]) eration of fully and partially depleted SOI MOSFETs. and radiation-hard circuits. In Section 5, it will be demonstrated that, based on The epitaxial lateral overgrowth (ELO) method con- scalability and ¯exibility arguments, SOI is capable of sists of growing a single-crystal Si ®lm on a seeded and further extending the limits and performance of bulk patterned oxide (Fig. 1a2). The ELO process requires a silicon technology. post-epitaxy thinning of the Si ®lm and is limited by the Revolutionary SOI solutions include: ground-plane, lateral extension of defect-free, single-crystal regions. double-gate, and ultra-thin transistors, dynamic-thresh- The ELO technique serves for the integration of 3-D old MOSFETs, 3-D structures, and microsensors. stacked circuits. In the last decade, the dominant SOI technology was SIMOX which is synthesized by internal oxidation during the deep implantation of oxygen ions into a Si wafer. Annealing at a high temperature (1320C, for 6 h) restores the crystalline quality of the ®lm. 800 SIMOX * Fax: +33-476-856070. wafers have good thickness uniformity, low defect den- E-mail address: [email protected] (S. Cristoloveanu). sity (except threading dislocations: 104±106 cm2), sharp

second wafer (Fig. 1a3) being recyclable, UNIBOND is a single-wafer process, (iii) only conventional equipment is needed for mass production, (iv) relatively inexpensive 1200 wafers are manufacturable, and (v) unlimited com- binations of BOX and ®lm thicknesses can be achieved in order to match most device con®gurations (ultra-thin CMOS or thick-®lm power transistors and sensors). The defect density in the ®lm is very low, the electrical properties are excellent, and the BOX quality is com- parable with that of the original thermal oxide. The Smart-Cut process is adaptable to a variety of materials: SiC or III±V compounds on insulator, silicon on dia- mond, etc. Other SOI technologies are full isolation by oxidized porous silicon (FIPOS) and zone melting recrystalliza- tion (ZMR) [1].

3. SOI devices

SOI circuits consist of single-device islands dielectri- cally isolated from one another and from the underlying substrate (Fig. 4a). The lateral isolation oers more compact design and simpli®ed technology than in bulk silicon: there is no need of wells or interdevice trenches. In addition, the vertical isolation renders the latch-up Fig. 1. Part of the SOI family: (a) SOS, ZMR, and wafer mechanism impossible. bonding, (b) SIMOX variants. The source/drain regions extend down to the buried oxide, hence the junction surface, leakage current and

Si±SiO2 interface, robust BOX, and high carrier mobility junction capacitance are minimized. Obvious implica- [4]. SIMOX comes in several ¯avors (Fig. 1b): (i) thin tions are improved speed, lower power dissipation, and thick Si ®lms fabricated by adjusting the implant wider temperature range, and attenuated short-channel energy, (ii) low-dose (4 Â 1017 O/cm2) SIMOX with a eects.

0.1 lm thick BOX (Fig. 1b1), (iii) standard oxygen dose As far as the reliability is concerned, SOI MOSFETs (1:8 Â 1018 O/cm2) SIMOX where the thicknesses of are extremely robust to transient radiation eects. It is the Si ®lm and BOX are 0.2 and 0.4 lm, respectively the permanent radiation-induced damage in the BOX

(Fig. 1b2), (iv) double SIMOX (Fig. 1b3, where the Si which may be an issue. Another problem is the integrity layer sandwiched between the two oxides serves for in- of the gate oxide which is governed by the defect density terconnects, wave guiding, additional gates, or electric in the ®lm. Assistance of specialists in dielectrics is still shielding, (v) interrupted oxides (Fig. 1b4) which can be needed for understanding the reliability aspects and the viewed as SOI regions integrated into a bulk Si wafer. microstructure of the buried oxide. Wafer bonding (WB) and etch-back is another ma- It is in the highly competitive domain of low power/ ture SOI technology. An oxidized Si wafer is mated to a voltage circuits that SOI is most attractive. SOI oers second Si wafer (Fig. 1a4). After bonding, the structure the possibility to achieve a quasi-ideal subthreshold is thinned down to reach the target thickness of the slope (60 mV/decade at room temperature), hence a silicon ®lm. Etch-stop layers can be achieved by doping threshold voltage below 0.3 V. Low leakage currents steps (P/P, P/N) or porous silicon (Eltran) [5]. limit the static power dissipation, as compared to bulk The recent, revolutionary UNIBOND process uses Si, whereas the dynamic power dissipation is minimized the deep implantation of hydrogen (dotted line in by the combined eects of low parasitic capacitances

Fig. 1a3) to generate microcavities [6]. After bonding and reduced voltage supply. and annealing, the wafers separate naturally at a depth It has been repeatedly demonstrated that SOI circuits de®ned by the location of hydrogen microcavities. This of generation n and bulk-Si circuits from the next mechanism, referred to as Smart-Cut, is completed by generation n 1 perform comparably. The speed re- touch-polishing. cord is for a CMOS technology with excellent short- The Smart-Cut approach has several outstanding channel behavior down to L 45 nm, and 8 ps inverter advantages: (i) the etch-back step is avoided, (ii) the delay [7,8]. More complex mainstreaming SOI circuits S. Cristoloveanu / Microelectronics Reliability 40 (2000) 771±777 773 have also been fabricated: 0.5 V±200 MHz micropro- whole transistor body and does not extend with gate cessor [9], 4 Mbit SRAM [10], 16 Mbit and 1 Gbit bias. A strong coupling develops between the gate bias DRAM [11], etc. [1,12]. Several companies (IBM, and the inversion charge, leading to enhanced drain Motorola, Sharp) have announced the imminent com- current. The front- and back-surface potentials become mercial deployment of `SOI-enhanced' PC processors coupled too and the electrical characteristics of one and mobile communication devices. channel vary remarkably with the bias applied to the The family of SOI devices also includes bipolar opposite gate [16]. This interface coupling causes the transistors (with a lateral con®guration), high-voltage front-gate measurements to depend on the back gate DMOS, smart power devices, and 3-D circuits [13]. bias and quality of the BOX oxide and interface. Totally

Most innovative devices make use of the possibility to new ID VG relations apply to fully depleted SOI (i) combine bulk Si and SOI on a single chip (Fig. 2a), MOSFETs. (ii) adjust the thickness of the Si overlay and buried The threshold voltage decreases linearly with V , the G2 oxide, and (iii) implement additional gates in the buried subthreshold slope is a maximum for depletion at oxide (Fig. 2b). The interrupted BOX (Fig. 1b4) allows the back interface, and the transconductance re¯ects the controlling of the vertical power devices, located in the possible activation of the back channel. the bulk region of the wafer, by a low-power CMOS on SOI (Fig. 2a). Double SIMOX (Fig. 1b3) has also been 4.2. Partially depleted SOI transistors used to achieve a double-shielded, intelligent, high- voltage circuit [14]. In partially depleted SOI MOSFETs, the depletion SOI is an ideal material for microsensors (pressure, charge does not extend from an interface to the other, acceleration, gas ¯ow, temperature, radiation, magnetic and a neutral region subsists. If body contacts are not ®eld, etc.) because the Si/BOX interface gives a perfect supplied, the so-called ¯oating-body eects arise, leading etch-stop mark, making it possible to fabricate very thin to detrimental consequences. The kink eect (Fig. 3a) is membranes, as shown in Fig. 2c [1,15]. due to majority carriers, generated by impact ionization, The Gate all±around (GAA) transistor is fabricated which collect in the body and increase the body potential by etching a cavity into the BOX and wrapping the (lower threshold voltage). In weak inversion and for oxidized transistor body by a poly-Si gate (Fig. 2d) [12]. high drain bias, a similar positive feedback is responsible

for negative resistance regions, hysteresis in log ID VG curves, and eventually transistor latch (Fig. 3b). 4. Special mechanisms in SOI MOSFETs The ¯oating body may also induce transient eects. A drain current overshoot is observed when the gate is 4.1. Fully-depleted SOI transistors turned on (Fig. 3c). Majority carriers are expelled from the depletion region and collect in the neutral body. The In SOI MOSFETs, inversion channels can be acti- drain current decreases gradually with time during electron±hole recombination. A reciprocal undershoot vated at both the front Si±SiO2 interface and the back Si±BOX interface (back-gate biasing V , Fig. 4a). Full G2 depletion means that the depletion region covers the

Fig. 2. Examples of innovative SOI devices: (a) combined bi- Fig. 3. Parasitic eects in partially depleted SOI MOSFETs: polar (or high power) bulk-Si transistor with low-voltage SOI (a) kink in ID VD curves, (b) latch in ID VG curves, (c) drain CMOS control circuit, (b) dual-gate transistors, (c) pressure current overshoot and undershoot, (d) premature breakdown sensor, and (d) GAA MOSFET. and self-heating. 774 S. Cristoloveanu / Microelectronics Reliability 40 (2000) 771±777 occurs when the gate is switched from strong to weak doping reduces the threshold voltage roll-o DVT L re- inversion: the current now increases with time (Fig. 3c) sulting from both CSE and DIBL. There is no in¯uence as the majority carrier generation allows the depletion of the ®lm thickness as long as the device is partially depth to shrink gradually. depleted. The worst case occurs for a doping±thickness combination that corresponds to the transition between partial and full depletion. 5. Ultimate SOI MOSFETs In fully depleted (FD) MOSFETs, the thinning of the ®lm is always bene®cial. The possibility to use ultra-thin 5.1. Short-channel eects ®lms, with lower doping (i.e. higher mobility), is actually

the main asset of SOI, as long as the VT roll-o is of In both fully and partially depleted MOSFETs with primary concern. However, the control of the nominal submicron length, the lateral bipolar transistor is easily threshold voltage and DIBL becomes more dicult in activated leading to positive (extra current) or negative low-doped ®lms [21]. To extend the design window, mid- (premature breakdown, vertical arrow in Fig. 3d) con- gap metal gates and thin buried oxides (reduced self- sequences. The breakdown voltage is especially lowered heating and DIVSB, but increased parasitic capacitance) for n-channels, shorter devices, thinner ®lms, and higher are being considered. temperatures [17]. The self-heating eect, induced by the poor thermal 5.3. Innovating architectures conductivity of the buried oxide, is responsible for the mobility degradation, threshold voltage shift, and neg- 5.3.1. Dynamic-threshold MOSFET ative dierential conductance (Fig. 3d). The DT-MOSFET is a partially depleted transistor, The threshold voltage is reduced by charge sharing where the gate and the body are interconnected. As the eect (CSE) and drain-induced barrier lowering (DIBL). gate voltage increases in weak inversion, the simulta- An extra DIBL eect is due to the ®eld penetration into neous increase in body potential makes the threshold the buried oxide and Si substrate. Fringing ®elds are voltage to decrease. DT-MOSFETs achieve perfect gate- responsible for an increase in the potential at the inter- charge coupling, maximum subthreshold slope, and face, ®lm±BOX, as if the back gate (substrate) was enhanced current, which are attractive features for sub- driven from depletion to weak inversion. This drain- 0.6 V CMOS circuits. A simple model compares the induced virtual substrate biasing (DIVSB) is critical in performance of DT and body-grounded (BG) MOS- sub-0.1 lm FD MOSFETs, where the front-channel FETs using an analytically de®ned enhancement factor threshold voltage is lowered and the subthreshold swing k: V V =k, S S =k, and l l Â k [22]. is degraded [18]. DT BG DT BG DT BG The hot-carrier degradation mechanisms are more complex in SOI MOSFETs than in bulk Si for several 5.3.2. Ground-plane MOSFET reasons: presence of two oxides, two channels and re- Initially, the ground plane (GP) for SOI was imag- lated coupling mechanisms, dierent ®eld distributions, ined as a highly conducting layer, made by pulse doping, and additional BOX damage which can aect the at the interface, ®lm±BOX (Fig. 4b) [23]. Such a GP properties of integrated circuits [19]. In n-channels, the cancels the fringing ®eld, by providing an equipotential defects are created at the interface where the electrons reference at the back interface which terminates the ¯ow; exceptionally, injection into the opposite interface potential contours. A dierent approach consists in may arise when the transistor is biased in the breakdown region. Although the device lifetime is relatively similar in bulk Si and SOI, the in¯uence of stressing bias is dierent: SOI MOSFETs degrade less than bulk Si

MOSFETs for VG ' VD=2 (i.e for maximum substrate current) and more for VG ' VT (i.e enhanced hole injection). The device aging is accelerated by accumulating the back interface [19]. In p-channels, the electrons generated by front-channel impact ionisation may be trapped into the buried oxide. An apparent degradation of the front interface occurs via coupling [19].

5.2. Scalability of SOI MOSFETs Fig. 4. Schematic structures envisioned as ultimate SOI The key parameters in SOI are the doping level, MOSFETs: (a) fully depleted, (b) pulsed doping, (c) ®eld plate, ®lm thickness, and BOX thickness [20]. Increasing the (d) ground plane, (e) dynamic threshold, and (f) double gate. S. Cristoloveanu / Microelectronics Reliability 40 (2000) 771±777 775 locating a ®eld plate underneath a very thin BOX dierence is explained using the Poisson and (<6 nm, Fig. 4c) [24]. The ®eld plate can be biased (i.e. Schrodinger equations, solved self-consistently. second gate) to adjust the back channel potential and As the ®lm (or quantum well) becomes thinner, the control the front channel threshold . energy levels and their separation increase [31]. The An alternative GP, more compatible with the present diculty to populate the upper levels explains the `ab- technology, can easily be fabricated, by ion implantation normal' increase in threshold voltage observed in sub- or bonding, underneath a conventional buried oxide 10 nm thick SOI MOSFETs [32]. (Fig. 4d). An optimum MOSFET architecture can be In DG-MOSFETs, the in-depth potential pro®le is achieved by combining such a GP, with a 50±100 nm symmetrical, and the vertical ®eld cancels in the middle thick BOX, a low-®lm doping and a mid-gap gate [18]. of the ®lm. The quantization eects are essentially Additional improvements are expected from the use of thickness-de®ned, hence lesser than in SG-MOSFETs. buried insulators with lower dielectric constant, includ- In DG mode, VT is lower and several subbands are ing buried air gap structures [25]. populated, whereas in SG mode, only the ground level is involved in charge transport. 5.3.3. Double-gate MOSFETs The spatial distribution of charge is symmetrical in The operation of double-gate (DG) SOI MOSFETs DG-MOSFETs and most of the carriers ¯ow in the is based on the concept of volume inversion [26]: the middle of the ®lm (Fig. 5b). In other words, quantum formation of front and back inversion channels causes, calculations reinforce the volume inversion concept by continuity, the spreading of minority carriers in the as compared to the classical viewpoint: the Poisson- volume of a thin SOI ®lm [26]. As many minority car- de®ned distribution showed more carriers at the ®lm riers ¯ow in the middle of the ®lm, surface scattering is interfaces. The subthreshold swing in DG mode is ideal reduced, enabling a higher transconductance and a re- (60 mV/decade), better than in SG mode. In strong duced 1=f noise. inversion, the total charge in DG mode is marginally It is admitted that the DG-MOSFET will represent higher than twice the inversion charge in SG mode. This the ®nal metamorphosis of an MOS transistor [27]. This implies that the dierence in transconductance between is so because the scalability is improved by the double SG and DG modes is related to the carrier mobility gate potential control which lowers both CSE and DIBL rather than to a charge eect. [23,27]. DG-MOSFETs with symmetrical con®guration A ®rst-order model predicts the impact of carrier and have been fabricated with GAA [12], Delta [28], and ®eld distributions on the mobility [30]. The electric ®eld lateral epitaxial growth [29] technologies. is negligible in the middle of the DG-MOSFET where We now discuss the case of ultimately thin (down to most of the inversion charge is located. As electron± 1 nm!) MOSFETs, fabricated by sacri®cial oxidation. phonon scattering strongly depends on the ®eld, the Their characteristics, in single-gate or double-gate mobility is presumably enhanced in the center of the modes, are very well behaved. It is fascinating that just a ®lm. It is also assumed that surface roughness degrades few monolayers of silicon are still able to maintain an the mobility near each interface (gray areas in Fig. 5b). MOS-like functionality. The calculations show that the average ®eld-eect mo- When biased in volume inversion, with bility is far higher in DG mode than twice the value in V t =t V , the 3-nm thick transistors reveal SG mode, where the vertical ®eld is stronger and many G2 ox2 ox1 G1 an outstanding increase in transconductance as com- carriers ¯ow in the `rough' region near the front inter- pared to single-gate (SG) operation (Fig. 5a) [30]. This face (Fig. 5b).

6. Conclusions

SOI technology oers the opportunity to integrate high performance and/or innovative devices which can push away the present frontiers of the CMOS down- scaling. SOI actually appears as the ®nal relay of the Si-based microelectronics. The short-term prospects of SOI depend on the penetration rate of SOI circuits into the market. Not only does SOI oer enhanced perfor- Fig. 5. (a) Drain current and transconductance measured in mance, but also most of SOI disadvantages (self-heating, a 3 nm SOI MOSFET operated in SG and DG modes. hot-carriers, early breakdown, etc.) disappear for oper- (b) Quantum distributions of minority carriers and electric ®eld ation at low voltage. But the key challenge to SOI

(VG VT 2 V); in the gray regions, the carrier mobility is designers, process engineers, and managers is still to presumably degraded by surface roughness. overcome the bulk-Si monopoly. 776 S. Cristoloveanu / Microelectronics Reliability 40 (2000) 771±777

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