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Modeling and Spice Implementation of Silicon-On-Insulator (Soi) Four Gate (G4fet) Transistor

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Modeling and Spice Implementation of Silicon-On-Insulator (Soi) Four Gate (G4fet) Transistor University of Tennessee, Knoxville TRACE: Tennessee Research and Creative Exchange Doctoral Dissertations Graduate School 8-2017 MODELING AND SPICE IMPLEMENTATION OF SILICON-ON- INSULATOR (SOI) FOUR GATE (G4FET) TRANSISTOR Md Sakib Hasan University of Tennessee, Knoxville, [email protected] Follow this and additional works at: https://trace.tennessee.edu/utk_graddiss Part of the Engineering Commons Recommended Citation Hasan, Md Sakib, "MODELING AND SPICE IMPLEMENTATION OF SILICON-ON-INSULATOR (SOI) FOUR GATE (G4FET) TRANSISTOR. " PhD diss., University of Tennessee, 2017. https://trace.tennessee.edu/utk_graddiss/4626 This Dissertation is brought to you for free and open access by the Graduate School at TRACE: Tennessee Research and Creative Exchange. It has been accepted for inclusion in Doctoral Dissertations by an authorized administrator of TRACE: Tennessee Research and Creative Exchange. For more information, please contact [email protected]. To the Graduate Council: I am submitting herewith a dissertation written by Md Sakib Hasan entitled "MODELING AND SPICE IMPLEMENTATION OF SILICON-ON-INSULATOR (SOI) FOUR GATE (G4FET) TRANSISTOR." I have examined the final electronic copy of this dissertation for form and content and recommend that it be accepted in partial fulfillment of the equirr ements for the degree of Doctor of Philosophy, with a major in Electrical Engineering. Syed K. Islam, Major Professor We have read this dissertation and recommend its acceptance: Benjamin J. Blalock, Nicole McFarlane, Ramakrishnan Kalyanaraman Accepted for the Council: Dixie L. Thompson Vice Provost and Dean of the Graduate School (Original signatures are on file with official studentecor r ds.) MODELING AND SPICE IMPLEMENTATION OF SILICON-ON-INSULATOR (SOI) FOUR GATE (G4FET) TRANSISTOR A Dissertation Presented for the Doctor of Philosophy Degree The University of Tennessee, Knoxville Md Sakib Hasan August 2017 DEDICATION This dissertation is dedicated to my parents, Zahir Uddin Ahmed and Shirin Akhter Lovely. ii ACKNOWLEDGMENTS I would like to express my earnest gratitude to my advisor Dr. Syed K. Islam for all the help and guidance he has provided me throughout my years of graduate study. His advice on matters, both technical and non-technical, has taught me how to grow as a successful engineer. Without his constant encouragement and direction, this journey would not have been possible. Special thanks go to Dr. Benjamin J. Blalock for his guidance and support as well as for the excellent courses he taught. I have benefited greatly from the conversations we had about circuit design and G4FET. I would like to extend my gratitude to Dr. Nicole McFarlane for serving on my committee and for her insightful suggestions about improving the work. I would also like to thank Dr. Ramakrishnan Kalyanaraman for finding time from his busy schedule to serve on my Ph.D. committee. I am grateful to The Institute of Biomedical Engineering at the University of Tennessee and the Min H. Kao Department of Electrical Engineering and Computer Science at the University of Tennessee, Knoxville for their financial support. I have had the good fortune of benefiting from important discussions with various people which have helped me a lot in my research. I would specially like to thank Ifana Mahbub, Khandakar Abdullah Al Mamun, Md Habibullah Habib, Riyasat Azim, Ishtiaque Hossain and Shamim Ara for making my graduate life enjoyable. Finally, I would like to express my deepest gratitude to my parents, Zahir Uddin Ahmed and Shirin Akhter Lovely, my brother Rajib Hasan and my friends Arunodoy, Avijit, Shibani, Himadri, Zisan, Farah, Babu bhai, Sanjib , Dulal, Ratna and Monir vai. iii ABSTRACT As the device dimensions have reduced from micrometer to nanometer range, new bulk silicon devices are now facing many undesirable effects of scaling leading device engineers to look for new process technologies. Silicon-on-insulator (SOI) has emerged as a very promising candidate for resolving the major problems plaguing the bulk silicon technology. G4FET [G4FET] is a SOI transistor with four independent gates. Although G4FET has already shown great potential in different applications, the widespread adoption of a technology in circuit design is heavily dependent upon good SPICE (Simulation Program with Integrated Circuit Emphasis) models. CAD (Computer Aided Design) tools are now ubiquitous in circuit design and a fast, robust and accurate SPICE model is absolutely necessary to transform G4FET into a mainstream technology. The research goal is to develop suitable SPICE models for G4FET to aid circuit designers in designing innovative analog and digital circuits using this new transistor. The first phase of this work is numerical modeling of the G4FET where four different numerical techniques are implemented, each with its merits and demerits. The first two methods are based on multivariate Lagrange interpolation and multidimensional Bernstein polynomial. The third numerical technique is based on multivariate regression polynomial to aid modeling with dense gridded data. Another suitable alternative namely multidimensional linear and cubic spline interpolation is explored as the fourth numerical modeling approach to solve some of the problems resulting from single polynomial approximation. The next phase of modeling involves developing a macromodel combining already existing SPICE models of MOSFET (metal–oxide–semiconductor field-effect transistor) and JFET (junction-gate field-effect transistor). This model is easy to implement in circuit simulators and iv provides good results compared to already demonstrated experimental works with innovative G4FET circuits. The final phase of this work involves the development of a physics-based compact model of G4FET with some empirical fitting parameters. A model for depletion-all-around operation is implemented in circuit simulator based on previous work. Another simplified model, combining MOS and JFET action, is implemented in circuit simulator to model the accumulation mode operation of G4FET. v TABLE OF CONTENTS Chapter 1 – Introduction ............................................................................................................. 1 1.1 Motivation ........................................................................................................................................................... 1 1.2 Research Goal ..................................................................................................................................................... 5 1.3 Dissertation Overview ........................................................................................................................................ 6 Chapter 2 - Literature Review ..................................................................................................... 7 2.1 Previous Works on G4FET .................................................................................................................................. 7 2.2 Previous Works on Numerical Modeling .......................................................................................................... 10 2.3 Previous Works on Macromodels ..................................................................................................................... 13 2.4 Previous Works on Physics-based Compact Modeling ..................................................................................... 15 Chapter 3 - Device Structure and Operating Mechanism of G4FET ..................................... 21 3.1 Multiple Independent Gate Silicon-On-Insulator (SOI) Transistor................................................................... 21 3.2 G4FET Device Structure ................................................................................................................................... 23 3.3 Principle of Operation ....................................................................................................................................... 24 3.4 Effect of Gate Bias on Conduction Path ........................................................................................................... 26 3.5 Chapter Summary ............................................................................................................................................. 29 Chapter 4 - Numerical Modeling of G4FET ............................................................................. 30 4.1 Overview ........................................................................................................................................................... 30 4.2 Numerical Method 1 (Multivariate Lagrange Interpolation Polynomial Model) .............................................. 31 4.2.1 Model Formulation ................................................................................................................................... 31 4.2.2 Model Validation ....................................................................................................................................... 34 4.2.2.1 An n-Channel G4FET Simulated with TCAD Sentaurus (Device 1) ................................................................... 34 4.2.2.2 Experimental Data from an n-Channel G4FET (Device 2) .................................................................................. 37 4.2.2.3 A p-Channel G4FET Simulated Using TCAD Sentaurus (Device 3) .................................................................. 39 vi 4.2.2.4 Experimental Data from a p-Channel
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