Elastic Strain Engineering in Silicon and Silicon-Germanium Nanomembranes
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Strained Silicon Devices M. Reiche , O. Moutanabbir , J. Hoentschel , U
Solid State Phenomena Vols. 156-158 (2010) pp 61-68 Online available since 2009/Oct/28 at www.scientific.net © (2010) Trans Tech Publications, Switzerland doi:10.4028/www.scientific.net/SSP.156-158.61 Strained Silicon Devices M. Reiche 1a , O. Moutanabbir 1b, J. Hoentschel 2c , U. Gösele 1d, S. Flachowsky 2e and M. Horstmann 2f 1 Max Planck Institute of Microstructure Physics, Weinberg 2, D – 06120 Halle, Germany 2 GLOBALFOUNDRIES Fab 1, Wilschdorfer Landstraße 101, D – 01109 Dresden, Germany a [email protected], b [email protected], c [email protected], d [email protected], e stefan.flachowsky@ globalfoundries.com, f [email protected] Keywords: strained silicon, mobility enhancement, process-induced strain, global strain, SSOI. Abstract. Strained silicon channels are one of the most important Technology Boosters for further Si CMOS developments. The mobility enhancement obtained by applying appropriate strain provides higher carrier velocity in MOS channels, resulting in higher current drive under a fixed supply voltage and gate oxide thickness. The physical mechanism of mobility enhancement, methods of strain generation and their application for advanced VLSI devices is reviewed. Introduction The ordinary device scaling was the most important principle of performance enhancement in Si CMOS for more than 30 years. However, starting with 90 nm technologies the performance enhancements of CMOS started to diminish through standard device scaling such as shrinking the gate length and thinning the gate oxide due to several physical limitations in miniaturization of MOSFETs. For example, thinning the gate oxide requires a reduction of the supply voltage and an increase of the gate tunneling current occurs. -
Mobility Enhancement of Strained Si Transistors by Transfer Printing on Plastic Substrates
OPEN NPG Asia Materials (2016) 8, e256; doi:10.1038/am.2016.31 www.nature.com/am ORIGINAL ARTICLE Mobility enhancement of strained Si transistors by transfer printing on plastic substrates Wonho Lee1, Yun Hwangbo2, Jae-Hyun Kim2 and Jong-Hyun Ahn1 Strain engineering has been utilized to overcome the limitation of geometric scaling in Si-based thin-film transistor (TFT) technology by significantly improving carrier mobility. However, current strain engineering methods have several drawbacks: they generate atomic defects in the interface between Si and strain inducers, they involve high-cost epitaxial depositions and they are difficult to apply to flexible electronics with plastic substrates. Here, we report the formation of a strained Si membrane with oxidation-induced residual strain by releasing a host Si substrate of a silicon-on-insulator (SOI) wafer. The construction of the suspended Si/SiO2 structures induces 40.5% tensile strain on the top Si membrane. The fabricated TFTs with strained Si channels are transferred onto plastics using a roll-based transfer technique, and they exhibit a mobility enhancement factor of 1.2–1.4 compared with an unstrained Si TFT. NPG Asia Materials (2016) 8, e256; doi:10.1038/am.2016.31; published online 25 March 2016 INTRODUCTION substrates. A strained Si nanomembrane is fabricated by releasing the A critical path in the development of advanced silicon electronics bilayer of Si and SiO2 from the host Si layer of a silicon-on-insulator involves a reduction in the dimensions of device geometries such as (SOI) wafer. The oxidation-induced compressive strain in the SiO2 the channel thickness, channel length and gate dielectric thickness to layer of the SOI wafer is activated by forming a suspended structure increase the operating speed with lower power consumption and via the etching of the host Si that leads to planar expansion of the 1–4 the density of integration in circuits. -
Stress Mapping in Strain-Engineered Silicon P-Type MOSFET Device: a Comparison Between Process Simulation and Experiments Christophe Krzeminski
Stress mapping in strain-engineered silicon p-type MOSFET device: A comparison between process simulation and experiments Christophe Krzeminski To cite this version: Christophe Krzeminski. Stress mapping in strain-engineered silicon p-type MOSFET device: A com- parison between process simulation and experiments. Journal of vaccum Science and Technology B, 2012, 30 (2), pp.022203-1. 10.1116/1.3683079. hal-00624131 HAL Id: hal-00624131 https://hal.archives-ouvertes.fr/hal-00624131 Submitted on 13 Feb 2012 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. APS/xxxxx Stress mapping in strain-engineered silicon pMOSFET device using process simulation C. Krzeminski1 Institut d’Electronique de Micro´electronique et de Nanotechnologie (IEMN-UMR CNRS 8520), D´epartement ISEN, Avenue Poincar´e, 59650 Villeneuve d’Ascqa) Strain engineering is the main technological booster used by semiconductor companies for the 65 and 45nm technology nodes to improve the channel mobility and the electrical performance of logic devices. For 32 and 22nm nodes, intense research work focuses on the integration and optimisation of these different techniques by cumulating the effects of different stressors. To estimate the level and the distribution of the stress field generated in the transistor channel by such multiple processing steps is a complex issue. -
Strained Silicon Layer in CMOS Technology
ELECTRONICS, VOL. 18, NO. 2, DECEMBER 2014 63 Strained Silicon Layer in CMOS Technology Tatjana Pešić-Brđanin, Branko L. Dokić However, the other demands of designing integrated circuits Abstract— Semiconductor industry is currently facing with the with ultra large scale of integration, such as, for example, the fact that conventional submicron CMOS technology is increase in density on the chip and reducing the size of the approaching the end of their capabilities, at least when it comes to chip, have led to the scaling of other transistor dimensions. scaling the dimensions of the components. Therefore, much attention is paid to device technology that use new technological Fig. 1 shows the trend of reducing the gate length that has led structures and new channel materials. Modern technological to the emergence of new technologies [1]. Reducing the gate processes, which mainly include ultra high vacuum chemical length caused a simultaneous scaling of other technological vapor deposition, molecular beam epitaxy and metal-organic parameters, in order to meet the required performances of molecular vapor deposition, enable the obtaining of ultrathin, integrated circuits regarding high speed and low power crystallographically almost perfect, strained layers of high purity. consumption, or the desired degree of integration. However, In this review paper we analyze the role that such layers have in modern CMOS technologies. It’s given an overview of the with recent CMOS technologies, in which the gate length is characteristics of both strain techniques, global and local, with less than 90 nm, this performance improvement becomes more special emphasis on performance of NMOS biaxial strain and difficult due to physical limitations in miniaturization of MOS PMOS uniaxial strain. -
Strain Engineering for Advanced Transistor Structure
STRAIN ENGINEERING FOR ADVANCED TRANSISTOR STRUCTURE TAN KIAN MING NATIONAL UNIVERSITY OF SINGAPORE 2008 STRAIN ENGINEERING FOR ADVANCED TRANSISTOR STRUCTURE TAN KIAN MING (B. ENG. (HONS.)), NUS (M. ENG.), NUS A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY DEPARTMENT OF ELECTRICAL AND COMPUTING ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE 2008 Acknowledgements First and foremost, I would like to thank my supervisor, Dr. Yeo Yee-Chia who has provided much support and encouragement throughout the course of my Ph.D candidature. I have benefited a lot from the numerous discussions that we have. I would also like to thank all my co-supervisors, A/P Yoo Won Jong, Dr Lap Chan, Dr Narayanan Balasubramanian and Dr Patrick Lo who have always been generous in helping me in whatever ways they can. In addition, I will also like to thank A/P Ganesh S. Samudra for giving his advice and suggestions during our research group meetings. Special thanks to Dr Yang Mingchu for constantly provide the support and help, which we need in using the FCVA system. My work is mainly done in 2 laboratories in this period of time, Semiconductor Processing Technology (SPT) Lab at the Institute of Microelectronics (IME), and the Silicon Nano Device Lab (SNDL) at the National University of Singapore (NUS). I am very grateful to all the staffs in both laboratories as they have provided assistance in one way or another which made my work possible. I have also learnt a lot from the friends that I have made from Chartered, SNDL and IME. In particularly, I am extremely thankful that the development of FinFET process flow is done together with Tsung-Yang (Jason). -
Electron Effective Mobility in Strained Si/Si1-Xgex MOS Devices Using Monte Carlo Simulation
Electron effective mobility in strained Si/Si1-xGex MOS devices using Monte Carlo simulation V. Aubry-Fortuna, P. Dollfus, S. Galdin-Retailleau Institut d'Electronique Fondamentale, CNRS UMR 8622, Bât. 220, Université Paris-Sud, 91405 Orsay cedex, France. E-mail : [email protected] Abstract Based on Monte Carlo simulation, we report the study of the inversion layer mobility in n-channel strained Si/ Si1-xGex MOS structures. The influence of the strain in the Si layer and of the doping level is studied. Universal mobility curves µeff as a function of the effective vertical field Eeff are obtained for various state of strain, as well as a fall-off of the mobility in weak inversion regime, which reproduces correctly the experimental trends. We also observe a mobility enhancement up to 120 % for strained Si/ Si0.70Ge0.30, in accordance with best experimental data. The effect of the strained Si channel thickness is also investigated: when decreasing the thickness, a mobility degradation is observed under low effective field only. The role of the different scattering mechanisms involved in the strained Si/ Si1-xGex MOS structures is explained. In addition, comparison with experimental results is discussed in terms of SiO2/ Si interface roughness, as well as surface roughness of the SiGe substrate on which strained Si is grown. Keywords strained Si, effective mobility, Monte Carlo simulation, MOSFET PACS codes 72.20.Dp, 72.20.Fr, 85.30.Tv -1- 1. Introduction The use of strained-Si channel pseudomorphically grown on a SiGe virtual substrate is becoming a promising way to accelerate the improvement of CMOS performance. -
Sige CVD, Fundamentals and Device Applications
SiGeSiGe CVD,CVD, fundamentalsfundamentals andand devicedevice applicationsapplications DrDr DerekDerek HoughtonHoughton AixtronAixtron IncInc ICPS,ICPS, FlagstaffFlagstaff JulyJuly 20042004 . OVERVIEW 1.1. Introduction Introduction 2.2. SiGe SiGe Market Market SurveySurvey 3.3. Fundamentals Fundamentals ofof SiGeSiGe CVDCVD 4.4. CVD CVD EquipmentEquipment forfor SiGeSiGe 5.5. Device Device aplicationsaplications andand commercializationcommercialization 6.6. SiGe SiGe materialsmaterials engineering,engineering, metrologymetrology 7.7. Summary Summary and and DiscussionDiscussion SiGe’s Market Opportunity... Si CMOS/BJTs SiGe HBTs/CMOS? III-V FETs/HBTs Automotive Road Collision Pricing Avoidance Navigation/Areospace GPS x-band Radar Communications GSM DCS ISM DECT FRA WLAN DTH WLAN OC-48 DBS FRA G-Ethernet OC-192 LMDS 0.1 0.2 0.5 1 2 5 10 20 50 100 Frequency (GHz) SiGe HBT device structure and process description KeyKey figures figures of of SiGe SiGe HBT HBT process process •• SiGe SiGe BiCMOSBiCMOS uses uses SiGeSiGe HBT HBT ++ SiSi CMOSCMOS •• SiGe SiGe HBT HBT showsshows samesame processprocess asas SiSi BT BT withwith exceptionexception ofof 30-8030-80 nmnm thinthin SiGeSiGe base base layerlayer (Ge(Ge <25%) <25%) •• Growth Growth ratesrates usedused areare aboutabout 3030 nm/minnm/min (~(~ 22 minmin forfor basebase layer)layer) •• Typically, Typically, samesame LPCVDLPCVD growthgrowth chamberschambers cancan depositedeposite both both SiSi and and SiGeSiGe layers layers Only difference: Base SiGe replaces Silicon •• Depending Depending -
Maximizing Uniaxial Tensile Strain in Large-Area Silicon-On-Insulator Islands on Compliant Substrates ͒ R
JOURNAL OF APPLIED PHYSICS 100, 023537 ͑2006͒ Maximizing uniaxial tensile strain in large-area silicon-on-insulator islands on compliant substrates ͒ R. L. Petersona Princeton Institute for the Science and Technology of Materials, Princeton University, Princeton, New Jersey 08540 and Department of Electrical Engineering, Princeton University, Princeton, New Jersey 08544 K. D. Hobart Naval Research Laboratory, Washington, DC 20375 H. Yin Princeton Institute for the Science and Technology of Materials, Princeton University, Princeton, New Jersey 08540 and Department of Electrical Engineering, Princeton University, Princeton, New Jersey 08544 F. J. Kub Naval Research Laboratory, Washington, DC 20375 J. C. Sturm Princeton Institute for the Science and Technology of Materials, Princeton University, Princeton, New Jersey 08540 and Department of Electrical Engineering, Princeton University, Princeton, New Jersey 08544 ͑Received 24 November 2005; accepted 3 May 2006; published online 31 July 2006; publisher error corrected 27 September 2006͒ Recently we have demonstrated a process for generating uniaxial tensile strain in silicon. In this work, we generate uniaxially strained silicon and anisotropically strained silicon germanium on insulator with strain in both ͗100͘ and ͗110͘ in-plane directions. The strain is uniform over fairly large areas, and relaxed silicon-germanium alloy buffers are not used. The magnitude of uniaxial strain generated by the process is very dependent on the in-plane crystal direction, and can be modeled accurately using the known mechanical properties of silicon and germanium. A maximum uniaxial silicon strain of 1.0% in the ͗100͘ direction is achieved. Numerical simulations of the dynamic strain generation process are used to identify process windows for achieving maximum uniaxial silicon strain for different structural geometries. -
Challenges and Innovations in Nano‐CMOS Transistor Scaling
Challenges and Innovations in Nano‐CMOS Transistor Scaling Tahir Ghani Intel Fellow Logic Technology Development October, 2009 Nikkei Presentation 1 Outline • Traditional‐Scaling ‐ Traditional Scaling Limiters, Device Implications ‐ Intel’s Response • Post “Traditional‐Scaling” Innovations ‐ Mobility Booster: Uniaxial Strain - Poly Depletion Elimination: Metal Gate - Gate Leakage Reduction: HiK • Future Challenges and Options - Power Limitation - Potential New Transistor Structures and Materials 40+ Years of Moore’s Law at INTEL: From Few to Billions of Transistors 2X transistors every 2 years Transistor Count has Doubled Every Two Years 40+ Years of Moore’s Law at INTEL: From Few to Billions of Transistors 2X transistors every 2 years Traditional Scaling Era END OF TRADITIONAL SCALING ERA ~ 2003 Lasted ~40 YEARS Top “Traditional-Scaling” Enablers R. Dennard et.al. IEEE JSSC, 1974 • Gate Oxide Thickness Scaling - Key enabler for Lgate scaling • Junction Scaling - Another enabler for Lgate scaling - Improved abruptness (REXT reduction) • Vcc Scaling - Reduce XDEP (improve SCE) - However, did not follow const E field 1990’s: Golden Era of Scaling Vcc, Tox & Lg scaling & increasing Idsat Year 2000: INTEL 90nm CMOS Pathfinding End of “Traditional-Scaling” Era Gate oxide running Mobility degrades out of atoms with scaling 1.E+04 Jox limit VLSI Symp. 2000 300 Universal 1.E+03 NA= Mobility 3x1017 ] 1.E+02 SiO 250 2 2 /(V.s) [Lo et. al, EDL97] 2 1.E+01 18 200 1.3x10 [A/cm 130nm 1.E+00 1.8x1018 OX J 1.E-01 18 150 2.5x10 18 1.E-02 Nitrided SiO2 180nm 3.3x10 1.E-03 Mobility (cm 100 0.51.01.52.02.5 0 0.5 1 1.5 TOX Physical [nm] E EFF [MV/cm] • Gate Oxide Leakage • Universal Mobility Model direct tunneling limited • Ionized impurity scattering T. -
A Survey on Multi Gate MOSFETS
ISSN (Online) : 2319 - 8753 ISSN (Print) : 2347 - 6710 International Journal of Innovative Research in Science, Engineering and Technology Volume 3, Special Issue 3, March 2014 2014 International Conference on Innovations in Engineering and Technology (ICIET’14) 21st & 22nd March Organized by K.L.N. College of Engineering, Madurai, Tamil Nadu, India A Survey on Multi Gate MOSFETS B.Buvaneswari Department Of CSE , K.L.N College of engineering ,Madurai, , India (small MOSFETs demonstrate higher outflow currents, ABSTRACT— This paper presents the various device and lower output resistance). A multigate device or structure of MOSFETs like SOI-MOSFET, Double gate multiple gate junction transistor (MuGFET) refers to a Mosfet, Trigate mosfet, Multigate mosfet ,Nanowire MOSFET (metal–oxide–semiconductor field-effect Mosfets,High-K Mosfets& their deserves. To grasp transistor) which includes quite one gate into a sole during a easy means, mathematical ideas of device device. The multiple gates could also be controlled by physics skipped. one gate.conductor, whereby the multiple gate surfaces act electrically as one gate, or by freelance gate INDEX TERMS-DG-MOSFET, GAA, MuG electrodes. A multigate device using freelance gate MOSFETS. electrodes is usually referred to as a Multiple Insulated Gate Field impact electronic transistor (MIGFET). Multigate transistors square measure one in every of I.INTRODUCTION quite an few ways being developed by CMOS semiconductor makers to form ever-smaller Over the past decades, the Metal oxide Semiconductor microprocessors and memory cells, conversationally (MOSFET) has repeatedly been scaled down in size[1]; spoken as extending Moore's Law.[1]Development classic MOSFET channel lengths were once many efforts into multigate transistors are reported by AMD, micrometers, however fashionable integrated circuits Hitachi, IBM, Infineon Technologies, Intel Corporation, square measure incorporating MOSFETs with channel TSMC, Free scale Semiconductor, University of lengths of tens of nanometers. -
Effect of Ge Concentration on the On-Current Boosting of Logic P-Type MOSFET with Sigma-Shaped Source/Drain
coatings Article Effect of Ge Concentration on the On-Current Boosting of Logic P-Type MOSFET with Sigma-Shaped Source/Drain Eunjung Ko 1,2, Juhee Lee 1,2, Seung-Wook Ryu 2, Hyunsu Shin 1, Seran Park 1 and Dae-Hong Ko 1,* 1 Department of Material Science and Engineering, Yonsei University, Seoul 03722, Korea; [email protected] (E.K.); [email protected] (J.L.); [email protected] (H.S.); [email protected] (S.P.) 2 R&D Division, SK Hynix Inc., Icheon-si 17336, Korea; [email protected] * Correspondence: [email protected]; Tel.: +82-2-2123-2853; Fax: +82-2-312-5375 Abstract: Silicon german ium (SiGe) has attracted significant attention for applications in the source/drain (S/D) regions of p-type metal-oxide-semiconductor field-effect transistors (p-MOSFETs). However, in SiGe, as the Ge concentration increases, high-density defects are generated, which limit its applications. Therefore, several techniques have been developed to minimize defects; however, these techniques require relatively thick epitaxial layers and are not suitable for gate-all-around FETs. This study examined the effect of Ge concentration on the embedded SiGe source/drain region of a logic p-MOSFET. The strain was calculated through nano-beam diffraction and predictions through a simulation were compared to understand the effects of stress relaxation on the change in strain applied to the Si channel. When the device performance was evaluated, the drain saturation current was approximately 710 µA/µm at an off current of 100 nA/µm with a drain voltage of 1 V, indicating that the current was enhanced by 58% when the Ge concentration was optimized. -
MOSFET Channel Engineering Using Strained Si, Sige, and Ge Channels
MOSFET Channel Engineering using Strained Si, SiGe, and Ge Channels Eugene A. Fitzgerald, Minjoo L. Lee, Christopher W. Leitz, and Dimitri A. Antoniadis* Dept of Materials Science and Engineering, MIT, Cambridge, MA 02139, *Dept of Electrical Engineering and Computer Science, MIT, Cambridge, MA 02139 Ge, saturating at roughly 80% enhancement.[7] For strained Abstract—Biaxial tensile strained Si grown on SiGe virtual Si on virtual substrates with greater than 20% Ge content, the substrates will be incorporated into future generations of CMOS subband splitting in the conduction band is large enough to technology due to the lack of performance increase with scaling. completely suppress intervalley scattering (figure 1a). Holes Compressively strained Ge-rich alloys with high hole mobilities also have increased mobility in strained Si due to subband can also be grown on relaxed SiGe. We review progress in splitting (figure 1b); however, greater strain levels in the strained Si and dual channel heterostructures, and also introduce strained Si are required to achieve the same hole mobility high hole mobility digital alloy heterostructures. By optimizing growth conditions and understanding the physics of hole and enhancement as achieved for electrons. Unlike electrons, the electron transport in these devices, we have fabricated nearly in-plane and out-of-plane mobility of holes in strained Si also symmetric mobility p- and n-MOSFETs on a common Si0.5Ge0.5 increases, resulting in a more complicated picture of hole virtual substrate. transport. Fig. 2 shows the carrier mobility enhancement factors for electrons and holes as a function of Ge Index Terms—SiGe, strained silicon, germanium, MOSFETs, concentration in the relaxed Si1-xGex.