DOCSLIB.ORG

Stress Modeling of Nanoscale Mosfet

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Stress Modeling of Nanoscale Mosfet STRESS MODELING OF NANOSCALE MOSFET By NIRAV SHAH A THESIS PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF SCIENCE UNIVERSITY OF FLORIDA 2005 Copyright 2005 by Nirav Shah This work is dedicated to my parents for their unconditional love and support, and without whom, I could not have achieved what I have. ACKNOWLEDGMENTS First and foremost, I would like to thank my advisor, Dr. Scott E. Thompson, for all the support, encouragement and assistance he has given me throughout my graduate studies, and for the opportunity to work with him in the SWAMP group. Despite being really busy, he always found time for his students to discuss research and other technical deliberations. I will always adore his innovative thinking and diligent commitment to research, which I tried to imbibe during my work tenure. I am also very grateful to Dr. Mark E. Law and Dr. William R. Eisenstadt for supporting my research activities and for their guidance and support as my supervisory committee. This research could not have been completed without the financial support of the Semiconductor Research Corporation and Applied Materials Inc. I would like to thank the University of Florida and Department of Electrical and Computer Engineering for giving me an opportunity to explore the wide horizons of the technical arena. I would like to thank the SWAMP group and all its members for their warm support during my research. I appreciate the efforts of Teresa Stevens for being an excellent program assistant. I am grateful to Russ Robison for his assistance to get me acquainted with FLOOPS and his continuous support thereafter. I would like to thank Ljubo Radic for being a good friend and helping me solve problems during my research work. I am especially thankful to Heather Randell, for her help all throughout my research work and then after to compile my thesis. I would like to thank Sagar Suthram, iv Guangyu Sun, Nidhi Mohta and Kehuey Wu for their availability for research related discussions. I thank my loving parents and each member of my family, without whose support and motivation, my achievements would have been incomplete. Last but not least, I would specifically like to thank all my roommates, friends, colleagues and teachers in the United States, and back home, for their overwhelming love and trust in my efforts, and for standing by me whenever I needed them the most. v TABLE OF CONTENTS page ACKNOWLEDGMENTS ................................................................................................. iv LIST OF TABLES........................................................................................................... viii LIST OF FIGURES ........................................................................................................... ix ABSTRACT....................................................................................................................... xi CHAPTER 1 INTRODUCTION ........................................................................................................1 1.1 History and Motivation...........................................................................................1 1.2 Strained Silicon Physics .........................................................................................3 1.3 Modifications in Conventional MOSFET Equation due to Strain..........................5 1.4 Summary.................................................................................................................6 2 SIMULATION MECHANICS.....................................................................................7 2.1 Basics of Engineering Mechanics...........................................................................7 2.2 Relationship between Stress and Strain..................................................................8 2.3 Software Approach To Engineer Stress................................................................10 2.3.1 ISE-FLOOPS Background .........................................................................10 2.3.2 How to use ISE-FLOOPS...........................................................................11 2.3.3 Computation of Mechanical Stress using ISE-FLOOPS............................11 2.3.4 Finite Element Method (FEM) ...................................................................12 2.3.5 Boundary Conditions..................................................................................15 2.4 Material Parameter Sensitivity .............................................................................15 2.5 Summary...............................................................................................................17 3 STRESS GENERATION TECHNIQUES IN ADVANCED CMOS ........................18 3.1 Types of Process Induced Stresses .......................................................................18 3.1.1 Thermal Mismatch Stress...........................................................................18 3.1.2 Intrinsic Stress ............................................................................................19 3.1.3 Dopant Induced Stress................................................................................20 3.2 Biaxial Stress Generation Technique....................................................................20 3.3 Uniaxial Stress Generation Technique .................................................................23 vi 3.4 Effect of Varying Geometrical Parameters...........................................................24 3.4.1 Critical Dimension Scaling.........................................................................25 3.4.2 Polysilicon Gate Scaling.............................................................................26 3.4.3 Effect of Buffer Layer on NMOS Channel Stress......................................27 3.4.4 Effect of Salicide ........................................................................................28 3.5 Summary...............................................................................................................29 4 CASES OF TECHNOLOGICAL IMPORTANCE AND RELATED ISSUES.........30 4.1 Strained-Silicon-On-Insulator (SSOI) ..................................................................30 4.2 Uniaxially Strained Device Issues........................................................................32 4.2.1 Effect of Varying Silicon Nitride Thickness ..............................................32 4.2.2 Multiple Gate Structure ..............................................................................34 4.2.3 Stress Relaxation Due to the Presence of STI ............................................35 4.2.4 Stress Relaxation due to Contact Etching ..................................................37 4.2.5 Effect of Raised Source/Drain in PMOS Device .......................................39 4.2.6 SOI vs Bulk Technology ............................................................................40 4.2.7 Effect on Stress by Boron Doping in p-channel Devices...........................42 4.3 Prospective Stress Generation Techniques...........................................................44 4.3.1 Stress Variation Along the Device Width ..................................................45 4.3.2 Stress Engineering by STI Depth ...............................................................46 4.3.3 Stress Engineering by STI Width...............................................................47 4.3.4 Stress Dependence on STI Topology .........................................................48 4.3.5 Stress Dependence on STI Densification ...................................................49 4.4 Summary...............................................................................................................49 5 SUMMARY, CONCLUSIONS, AND RECOMMENDATIONS FOR FUTURE WORK ........................................................................................................................51 5.1 Summary and Conclusions ...................................................................................51 5.2 Recommendations for Future Work .....................................................................56 5.2.1 3D Modeling...............................................................................................57 5.2.2 Additivity Issue ..........................................................................................57 5.2.3 Stress Generation due to Thermal Mismatch and Material Growth...........58 5.2.4 Better Understanding of Novel Stress Generation Techniques..................58 LIST OF REFERENCES...................................................................................................60 BIOGRAPHICAL SKETCH .............................................................................................65 vii LIST OF TABLES Table page 2-1 Material Parameter Sensitivity Results ....................................................................16 2-2 Material Properties at Room Temperature ...............................................................17 3-1 Longitudinal and Transverse Piezoresistance Coefficients Evaluated for Standard Layout and Wafer Orientation (Units of 10-12 cm2 dyne-1).......................21 3-2 Effect of Salicide on NMOS Channel Stress ...........................................................29 viii LIST OF FIGURES Figure page 1-1 Prediction by Dr. Gordon E. Moore, also known as Moore’s Law............................1 1-2 Transistor size
Load more

Recommended publications
  • Study of Nickel Silicide Processes for Advanced CMOS Applications
    Curanovi~, Branislav 2 ~ Annual Microelectronic Engineering Conference, May 2003 Study of Nickel Suicide Processes for Advanced CMOS Applications Branislav Curanovid, Student Member, IEEE PMOS transistors. In general, today’s CMOS processes Abstract—A study has been performed to determine have many uses for silicides, and are predicted by the critical mechanisms involved in formation of nickel International Technology Roadmap for Semiconductors suicides. The process parameters under investigation were (ITRS) [11 to be very important and relevant for several silicidation temperature, presilicide N5~ implant, and the years into the future. presence of a titanium capping layer. Contact sheet The choice of metals for suicide formation is resistance phosphorous-implanted silicon was measured and determined to degrade with high silicidation becoming crucial, as certain metals have started to temperature. Titanium capping was found to improve approach physical limits associated with their properties. contact resistance and compensate for the effects of high There are three metals that are most frequently used in temperature treatment for polycides. The nitrogen modern suicide formation: titanium, cobalt, and nickel. incorporation via implant shows a degradation in Titanium suicide (TiSi2) has been a long-time resistivity for both silicides and polycides. dominant suicide technology, but has reached extinction in modern deep sub-micrometer CMOS applications. Index Terms—Ni silicidation, nitrogen implant, RTP Although it offers low resistivity when properly formed, TiSi2 exhibits several critical failures. One such failure is the silicon-diffusion dominated formation of silicides I. INTRODUCTION that can lead to problems of bridging. Secondly, TiSi2 exhibits a strong narrow-line effect due to incomplete S microelectronicILICIDES haveindustrybeen usedto forcircumventmany yearsthe inhighthe transition from a high-resistivity C49 phase to the low- resistivity seen when contacting metal to poly gates and resistivity C50 phase.
    [Show full text]
  • Strained Silicon Devices M. Reiche , O. Moutanabbir , J. Hoentschel , U
    Solid State Phenomena Vols. 156-158 (2010) pp 61-68 Online available since 2009/Oct/28 at www.scientific.net © (2010) Trans Tech Publications, Switzerland doi:10.4028/www.scientific.net/SSP.156-158.61 Strained Silicon Devices M. Reiche 1a , O. Moutanabbir 1b, J. Hoentschel 2c , U. Gösele 1d, S. Flachowsky 2e and M. Horstmann 2f 1 Max Planck Institute of Microstructure Physics, Weinberg 2, D – 06120 Halle, Germany 2 GLOBALFOUNDRIES Fab 1, Wilschdorfer Landstraße 101, D – 01109 Dresden, Germany a [email protected], b [email protected], c [email protected], d [email protected], e stefan.flachowsky@ globalfoundries.com, f [email protected] Keywords: strained silicon, mobility enhancement, process-induced strain, global strain, SSOI. Abstract. Strained silicon channels are one of the most important Technology Boosters for further Si CMOS developments. The mobility enhancement obtained by applying appropriate strain provides higher carrier velocity in MOS channels, resulting in higher current drive under a fixed supply voltage and gate oxide thickness. The physical mechanism of mobility enhancement, methods of strain generation and their application for advanced VLSI devices is reviewed. Introduction The ordinary device scaling was the most important principle of performance enhancement in Si CMOS for more than 30 years. However, starting with 90 nm technologies the performance enhancements of CMOS started to diminish through standard device scaling such as shrinking the gate length and thinning the gate oxide due to several physical limitations in miniaturization of MOSFETs. For example, thinning the gate oxide requires a reduction of the supply voltage and an increase of the gate tunneling current occurs.
    [Show full text]
  • Mobility Enhancement of Strained Si Transistors by Transfer Printing on Plastic Substrates
    OPEN NPG Asia Materials (2016) 8, e256; doi:10.1038/am.2016.31 www.nature.com/am ORIGINAL ARTICLE Mobility enhancement of strained Si transistors by transfer printing on plastic substrates Wonho Lee1, Yun Hwangbo2, Jae-Hyun Kim2 and Jong-Hyun Ahn1 Strain engineering has been utilized to overcome the limitation of geometric scaling in Si-based thin-film transistor (TFT) technology by significantly improving carrier mobility. However, current strain engineering methods have several drawbacks: they generate atomic defects in the interface between Si and strain inducers, they involve high-cost epitaxial depositions and they are difficult to apply to flexible electronics with plastic substrates. Here, we report the formation of a strained Si membrane with oxidation-induced residual strain by releasing a host Si substrate of a silicon-on-insulator (SOI) wafer. The construction of the suspended Si/SiO2 structures induces 40.5% tensile strain on the top Si membrane. The fabricated TFTs with strained Si channels are transferred onto plastics using a roll-based transfer technique, and they exhibit a mobility enhancement factor of 1.2–1.4 compared with an unstrained Si TFT. NPG Asia Materials (2016) 8, e256; doi:10.1038/am.2016.31; published online 25 March 2016 INTRODUCTION substrates. A strained Si nanomembrane is fabricated by releasing the A critical path in the development of advanced silicon electronics bilayer of Si and SiO2 from the host Si layer of a silicon-on-insulator involves a reduction in the dimensions of device geometries such as (SOI) wafer. The oxidation-induced compressive strain in the SiO2 the channel thickness, channel length and gate dielectric thickness to layer of the SOI wafer is activated by forming a suspended structure increase the operating speed with lower power consumption and via the etching of the host Si that leads to planar expansion of the 1–4 the density of integration in circuits.
    [Show full text]
  • Stress Mapping in Strain-Engineered Silicon P-Type MOSFET Device: a Comparison Between Process Simulation and Experiments Christophe Krzeminski
    Stress mapping in strain-engineered silicon p-type MOSFET device: A comparison between process simulation and experiments Christophe Krzeminski To cite this version: Christophe Krzeminski. Stress mapping in strain-engineered silicon p-type MOSFET device: A com- parison between process simulation and experiments. Journal of vaccum Science and Technology B, 2012, 30 (2), pp.022203-1. 10.1116/1.3683079. hal-00624131 HAL Id: hal-00624131 https://hal.archives-ouvertes.fr/hal-00624131 Submitted on 13 Feb 2012 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. APS/xxxxx Stress mapping in strain-engineered silicon pMOSFET device using process simulation C. Krzeminski1 Institut d’Electronique de Micro´electronique et de Nanotechnologie (IEMN-UMR CNRS 8520), D´epartement ISEN, Avenue Poincar´e, 59650 Villeneuve d’Ascqa) Strain engineering is the main technological booster used by semiconductor companies for the 65 and 45nm technology nodes to improve the channel mobility and the electrical performance of logic devices. For 32 and 22nm nodes, intense research work focuses on the integration and optimisation of these different techniques by cumulating the effects of different stressors. To estimate the level and the distribution of the stress field generated in the transistor channel by such multiple processing steps is a complex issue.
    [Show full text]
  • Microfabrication and Microfluidics for 3D Brain-On-Chip
    Microfabrication and microfluidics for 3D brain-on-chip Bart Schurink Microfabrication and microfluidics for 3D brain-on-chip Bart Schurink i Members of the committee: Chairman Prof. dr. ir. J.M.W. Hilgenkamp (voorzitter) Universiteit Twente Promotor Prof. dr. J.G.E. Gardeniers Universiteit Twente Co-promotor/supervisor Dr. R. Luttge Universiteit Eindhoven Members Prof. dr. J.C.T. Eijkel University of Twente Prof. dr. H.B.J. Karperien University of Twente Prof. dr. A.S. Holmes Imperial College London Prof. dr. ir. J.M.J. den Toonder Technical University of Eindhoven Prof. dr. ir. R. Dekker Delft University of Technology The work in this thesis was carried out in the Mesoscale Chemical Systems group and MESA+ Institute for Nanotechnology, University of Twente. It is part of the MESOTAS project financially supported by ERC, Starting Grant no. 280281 Title: Microfabrication and microfluidics for 3D brain-on-chip Author: Bart Schurink ISBN: 978-90-365-4142-8 DOI: 10.3990/1.9789036541428 Publisher: Gildeprint, Enschede, The Netherlands Copyright © 2016 by Bart Schurink, Enschede, The Netherlands. No part of the this book may be copied, photocopied, reproduced, translated or reduced to any electronic medium or machine-readable form, in whole or in part, without specific permission of the author. ii Microfabrication and microfluidics for 3D brain-on-chip PROEFSCHRIFT ter verkrijging van de graad van doctor aan de Universiteit Twente, op gezag van de rector magnificus, Prof. dr. H. Brinksma, volgens besluit van het College voor Promoties in het openbaar te verdedigen op donderdag 23 juni 2016 door Bart Schurink Geboren op 6 november 1982 te Oldenzaal, Nederland iii Dit proefschrift is goedgekeurd door de promotor: Prof.
    [Show full text]
  • Strained Silicon Layer in CMOS Technology
    ELECTRONICS, VOL. 18, NO. 2, DECEMBER 2014 63 Strained Silicon Layer in CMOS Technology Tatjana Pešić-Brđanin, Branko L. Dokić However, the other demands of designing integrated circuits Abstract— Semiconductor industry is currently facing with the with ultra large scale of integration, such as, for example, the fact that conventional submicron CMOS technology is increase in density on the chip and reducing the size of the approaching the end of their capabilities, at least when it comes to chip, have led to the scaling of other transistor dimensions. scaling the dimensions of the components. Therefore, much attention is paid to device technology that use new technological Fig. 1 shows the trend of reducing the gate length that has led structures and new channel materials. Modern technological to the emergence of new technologies [1]. Reducing the gate processes, which mainly include ultra high vacuum chemical length caused a simultaneous scaling of other technological vapor deposition, molecular beam epitaxy and metal-organic parameters, in order to meet the required performances of molecular vapor deposition, enable the obtaining of ultrathin, integrated circuits regarding high speed and low power crystallographically almost perfect, strained layers of high purity. consumption, or the desired degree of integration. However, In this review paper we analyze the role that such layers have in modern CMOS technologies. It’s given an overview of the with recent CMOS technologies, in which the gate length is characteristics of both strain techniques, global and local, with less than 90 nm, this performance improvement becomes more special emphasis on performance of NMOS biaxial strain and difficult due to physical limitations in miniaturization of MOS PMOS uniaxial strain.
    [Show full text]
  • Strain Engineering for Advanced Transistor Structure
    STRAIN ENGINEERING FOR ADVANCED TRANSISTOR STRUCTURE TAN KIAN MING NATIONAL UNIVERSITY OF SINGAPORE 2008 STRAIN ENGINEERING FOR ADVANCED TRANSISTOR STRUCTURE TAN KIAN MING (B. ENG. (HONS.)), NUS (M. ENG.), NUS A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY DEPARTMENT OF ELECTRICAL AND COMPUTING ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE 2008 Acknowledgements First and foremost, I would like to thank my supervisor, Dr. Yeo Yee-Chia who has provided much support and encouragement throughout the course of my Ph.D candidature. I have benefited a lot from the numerous discussions that we have. I would also like to thank all my co-supervisors, A/P Yoo Won Jong, Dr Lap Chan, Dr Narayanan Balasubramanian and Dr Patrick Lo who have always been generous in helping me in whatever ways they can. In addition, I will also like to thank A/P Ganesh S. Samudra for giving his advice and suggestions during our research group meetings. Special thanks to Dr Yang Mingchu for constantly provide the support and help, which we need in using the FCVA system. My work is mainly done in 2 laboratories in this period of time, Semiconductor Processing Technology (SPT) Lab at the Institute of Microelectronics (IME), and the Silicon Nano Device Lab (SNDL) at the National University of Singapore (NUS). I am very grateful to all the staffs in both laboratories as they have provided assistance in one way or another which made my work possible. I have also learnt a lot from the friends that I have made from Chartered, SNDL and IME. In particularly, I am extremely thankful that the development of FinFET process flow is done together with Tsung-Yang (Jason).
    [Show full text]
  • Electron Effective Mobility in Strained Si/Si1-Xgex MOS Devices Using Monte Carlo Simulation
    Electron effective mobility in strained Si/Si1-xGex MOS devices using Monte Carlo simulation V. Aubry-Fortuna, P. Dollfus, S. Galdin-Retailleau Institut d'Electronique Fondamentale, CNRS UMR 8622, Bât. 220, Université Paris-Sud, 91405 Orsay cedex, France. E-mail : [email protected] Abstract Based on Monte Carlo simulation, we report the study of the inversion layer mobility in n-channel strained Si/ Si1-xGex MOS structures. The influence of the strain in the Si layer and of the doping level is studied. Universal mobility curves µeff as a function of the effective vertical field Eeff are obtained for various state of strain, as well as a fall-off of the mobility in weak inversion regime, which reproduces correctly the experimental trends. We also observe a mobility enhancement up to 120 % for strained Si/ Si0.70Ge0.30, in accordance with best experimental data. The effect of the strained Si channel thickness is also investigated: when decreasing the thickness, a mobility degradation is observed under low effective field only. The role of the different scattering mechanisms involved in the strained Si/ Si1-xGex MOS structures is explained. In addition, comparison with experimental results is discussed in terms of SiO2/ Si interface roughness, as well as surface roughness of the SiGe substrate on which strained Si is grown. Keywords strained Si, effective mobility, Monte Carlo simulation, MOSFET PACS codes 72.20.Dp, 72.20.Fr, 85.30.Tv -1- 1. Introduction The use of strained-Si channel pseudomorphically grown on a SiGe virtual substrate is becoming a promising way to accelerate the improvement of CMOS performance.
    [Show full text]
  • Sige CVD, Fundamentals and Device Applications
    SiGeSiGe CVD,CVD, fundamentalsfundamentals andand devicedevice applicationsapplications DrDr DerekDerek HoughtonHoughton AixtronAixtron IncInc ICPS,ICPS, FlagstaffFlagstaff JulyJuly 20042004 . OVERVIEW 1.1. Introduction Introduction 2.2. SiGe SiGe Market Market SurveySurvey 3.3. Fundamentals Fundamentals ofof SiGeSiGe CVDCVD 4.4. CVD CVD EquipmentEquipment forfor SiGeSiGe 5.5. Device Device aplicationsaplications andand commercializationcommercialization 6.6. SiGe SiGe materialsmaterials engineering,engineering, metrologymetrology 7.7. Summary Summary and and DiscussionDiscussion SiGe’s Market Opportunity... Si CMOS/BJTs SiGe HBTs/CMOS? III-V FETs/HBTs Automotive Road Collision Pricing Avoidance Navigation/Areospace GPS x-band Radar Communications GSM DCS ISM DECT FRA WLAN DTH WLAN OC-48 DBS FRA G-Ethernet OC-192 LMDS 0.1 0.2 0.5 1 2 5 10 20 50 100 Frequency (GHz) SiGe HBT device structure and process description KeyKey figures figures of of SiGe SiGe HBT HBT process process •• SiGe SiGe BiCMOSBiCMOS uses uses SiGeSiGe HBT HBT ++ SiSi CMOSCMOS •• SiGe SiGe HBT HBT showsshows samesame processprocess asas SiSi BT BT withwith exceptionexception ofof 30-8030-80 nmnm thinthin SiGeSiGe base base layerlayer (Ge(Ge <25%) <25%) •• Growth Growth ratesrates usedused areare aboutabout 3030 nm/minnm/min (~(~ 22 minmin forfor basebase layer)layer) •• Typically, Typically, samesame LPCVDLPCVD growthgrowth chamberschambers cancan depositedeposite both both SiSi and and SiGeSiGe layers layers Only difference: Base SiGe replaces Silicon •• Depending Depending
    [Show full text]
  • Maximizing Uniaxial Tensile Strain in Large-Area Silicon-On-Insulator Islands on Compliant Substrates ͒ R
    JOURNAL OF APPLIED PHYSICS 100, 023537 ͑2006͒ Maximizing uniaxial tensile strain in large-area silicon-on-insulator islands on compliant substrates ͒ R. L. Petersona Princeton Institute for the Science and Technology of Materials, Princeton University, Princeton, New Jersey 08540 and Department of Electrical Engineering, Princeton University, Princeton, New Jersey 08544 K. D. Hobart Naval Research Laboratory, Washington, DC 20375 H. Yin Princeton Institute for the Science and Technology of Materials, Princeton University, Princeton, New Jersey 08540 and Department of Electrical Engineering, Princeton University, Princeton, New Jersey 08544 F. J. Kub Naval Research Laboratory, Washington, DC 20375 J. C. Sturm Princeton Institute for the Science and Technology of Materials, Princeton University, Princeton, New Jersey 08540 and Department of Electrical Engineering, Princeton University, Princeton, New Jersey 08544 ͑Received 24 November 2005; accepted 3 May 2006; published online 31 July 2006; publisher error corrected 27 September 2006͒ Recently we have demonstrated a process for generating uniaxial tensile strain in silicon. In this work, we generate uniaxially strained silicon and anisotropically strained silicon germanium on insulator with strain in both ͗100͘ and ͗110͘ in-plane directions. The strain is uniform over fairly large areas, and relaxed silicon-germanium alloy buffers are not used. The magnitude of uniaxial strain generated by the process is very dependent on the in-plane crystal direction, and can be modeled accurately using the known mechanical properties of silicon and germanium. A maximum uniaxial silicon strain of 1.0% in the ͗100͘ direction is achieved. Numerical simulations of the dynamic strain generation process are used to identify process windows for achieving maximum uniaxial silicon strain for different structural geometries.
    [Show full text]
  • Challenges and Innovations in Nano‐CMOS Transistor Scaling
    Challenges and Innovations in Nano‐CMOS Transistor Scaling Tahir Ghani Intel Fellow Logic Technology Development October, 2009 Nikkei Presentation 1 Outline • Traditional‐Scaling ‐ Traditional Scaling Limiters, Device Implications ‐ Intel’s Response • Post “Traditional‐Scaling” Innovations ‐ Mobility Booster: Uniaxial Strain - Poly Depletion Elimination: Metal Gate - Gate Leakage Reduction: HiK • Future Challenges and Options - Power Limitation - Potential New Transistor Structures and Materials 40+ Years of Moore’s Law at INTEL: From Few to Billions of Transistors 2X transistors every 2 years Transistor Count has Doubled Every Two Years 40+ Years of Moore’s Law at INTEL: From Few to Billions of Transistors 2X transistors every 2 years Traditional Scaling Era END OF TRADITIONAL SCALING ERA ~ 2003 Lasted ~40 YEARS Top “Traditional-Scaling” Enablers R. Dennard et.al. IEEE JSSC, 1974 • Gate Oxide Thickness Scaling - Key enabler for Lgate scaling • Junction Scaling - Another enabler for Lgate scaling - Improved abruptness (REXT reduction) • Vcc Scaling - Reduce XDEP (improve SCE) - However, did not follow const E field 1990’s: Golden Era of Scaling Vcc, Tox & Lg scaling & increasing Idsat Year 2000: INTEL 90nm CMOS Pathfinding End of “Traditional-Scaling” Era Gate oxide running Mobility degrades out of atoms with scaling 1.E+04 Jox limit VLSI Symp. 2000 300 Universal 1.E+03 NA= Mobility 3x1017 ] 1.E+02 SiO 250 2 2 /(V.s) [Lo et. al, EDL97] 2 1.E+01 18 200 1.3x10 [A/cm 130nm 1.E+00 1.8x1018 OX J 1.E-01 18 150 2.5x10 18 1.E-02 Nitrided SiO2 180nm 3.3x10 1.E-03 Mobility (cm 100 0.51.01.52.02.5 0 0.5 1 1.5 TOX Physical [nm] E EFF [MV/cm] • Gate Oxide Leakage • Universal Mobility Model direct tunneling limited • Ionized impurity scattering T.
    [Show full text]
  • Elastic Strain Engineering in Silicon and Silicon-Germanium Nanomembranes
    Elastic Strain Engineering in Silicon and Silicon-Germanium Nanomembranes By Deborah Marie Paskiewicz A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy (Materials Science) at the UNIVERSITY OF WISCONSIN-MADISON 2012 Date of final oral examination: 11/14/12 The dissertation is approved by the following members of the Final Oral Committee: Max G. Lagally, Professor, Materials Science and Engineering Mark A. Eriksson, Professor, Physics Thomas F. Kuech, Professor, Chemical and Biological Engineering Paul G. Evans, Associate Professor, Materials Science and Engineering Irena Knezevic, Associate Professor, Electrical and Computer Engineering ©Copyright by Deborah Marie Paskiewicz 2012 All Rights Reserved i Abstract Elastic Strain Engineering in Silicon and Silicon-Germanium Nanomembranes Deborah M. Paskiewicz Under the supervision of Professor Max G. Lagally At the University of Wisconsin-Madison Strain in crystalline materials alters the atomic symmetry, thereby changing materials properties. Controlling the strain (its magnitude, direction, extent, periodicity, symmetry, and nature) allows tunability of these new properties. Elastic strain engineering in crystalline nanomembranes (NMs) provides ways to induce and relax strain in thin sheets of single- crystalline materials without exposing the material to the formation of extended defects. I use strain engineering in NMs in two ways: (1) elastic strain sharing between multiple layers using the crystalline symmetry of the layers to induce unique strain distributions, and (2) complete elastic relaxation of single-crystalline alloy NMs. In both cases, NM strain engineering methods enable the introduction of unique strain profiles or strain relaxation in ways not compatible with conventional bulk processing, where strain destroys the long-range crystallinity.
    [Show full text]