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Effect of Ge Concentration on the On-Current Boosting of Logic P-Type MOSFET with Sigma-Shaped Source/Drain

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Effect of Ge Concentration on the On-Current Boosting of Logic P-Type MOSFET with Sigma-Shaped Source/Drain coatings Article Effect of Ge Concentration on the On-Current Boosting of Logic P-Type MOSFET with Sigma-Shaped Source/Drain Eunjung Ko 1,2, Juhee Lee 1,2, Seung-Wook Ryu 2, Hyunsu Shin 1, Seran Park 1 and Dae-Hong Ko 1,* 1 Department of Material Science and Engineering, Yonsei University, Seoul 03722, Korea; [email protected] (E.K.); [email protected] (J.L.); [email protected] (H.S.); [email protected] (S.P.) 2 R&D Division, SK Hynix Inc., Icheon-si 17336, Korea; [email protected] * Correspondence: [email protected]; Tel.: +82-2-2123-2853; Fax: +82-2-312-5375 Abstract: Silicon german ium (SiGe) has attracted significant attention for applications in the source/drain (S/D) regions of p-type metal-oxide-semiconductor field-effect transistors (p-MOSFETs). However, in SiGe, as the Ge concentration increases, high-density defects are generated, which limit its applications. Therefore, several techniques have been developed to minimize defects; however, these techniques require relatively thick epitaxial layers and are not suitable for gate-all-around FETs. This study examined the effect of Ge concentration on the embedded SiGe source/drain region of a logic p-MOSFET. The strain was calculated through nano-beam diffraction and predictions through a simulation were compared to understand the effects of stress relaxation on the change in strain applied to the Si channel. When the device performance was evaluated, the drain saturation current was approximately 710 µA/µm at an off current of 100 nA/µm with a drain voltage of 1 V, indicating that the current was enhanced by 58% when the Ge concentration was optimized. Keywords: silicon germanium; p-type metal-oxide-semiconductor field-effect transistors; source/drain Citation: Ko, E.; Lee, J.; Ryu, S.-W.; (S/D) regions; epitaxial growth; thermal annealing Shin, H.; Park, S.; Ko, D.-H. Effect of Ge Concentration on the On-Current Boosting of Logic P-Type MOSFET with Sigma-Shaped Source/Drain. 1. Introduction Coatings 2021, 11, 654. https:// In recent years, silicon germanium (SiGe) has been widely used in the source/drain doi.org/10.3390/coatings11060654 (S/D) regions of p-type metal-oxide-semiconductor field-effect transistors (p-MOSFETs) to induce a uniaxial strain in the channel region. When a 65-nm-transistor-node is used for Academic Editor: Ingrid Milošev three-dimensional structures, such as a fin field-effect transistors (FETs) or gate-all-around FETs, the lateral dimensions, including the junction depth, of these regions becomes more Received: 7 May 2021 significant. Thus, embedded SiGe technology, namely e-SiGe, was adopted to increase Accepted: 27 May 2021 Published: 29 May 2021 the S/D volume. The SiGe epitaxy process has been used in S/D to induce a compressive strain in its channel, thereby increasing hole mobility [1–4]. Since Si and Ge have the same Publisher’s Note: MDPI stays neutral crystallographic structure, both materials can be easily alloyed [5]; the lattice constant of with regard to jurisdictional claims in SiGe increases as the Ge concentration increases. Thus, to increase the transistor current, published maps and institutional affil- several studies have aimed to induce compressive strain in the channel by increasing the iations. Ge concentration [6,7]. SiGe is useful for strain engineering and it also effectively reduces the contact resistance in the S/D regions by reducing the Schottky barrier heights [8–10]. As the transistor size decreases, achieving a low contact resistivity becomes crucial. A contact resistivity of <1 × 10−9 W·cm2 is required in a <7 nm node [11]. E-SiGe is an effective method that can increase the uniaxial compressive strain applied Copyright: © 2021 by the authors. Licensee MDPI, Basel, Switzerland. to the channel, and a selectively epitaxial growth (SEG) of SiGe in the recessed S/D region This article is an open access article is essential for this. SiGe is particularly suitable for the SEG process because it can be distributed under the terms and selectively deposited on the exposed S/D regions and etched at high selectivity for Si and conditions of the Creative Commons SiO2 [12–14]. When performing SEG of SiGe using a chemical vapor deposition (CVD), it Attribution (CC BY) license (https:// is also necessary to consider how many chips of the patterned wafer are adjacent to each creativecommons.org/licenses/by/ other [15]. The strain applied to the channel is affected by the shape of the sigma cavity 4.0/). and concentrations of Ge and B [16–19]. The strain is compensated when the concentration Coatings 2021, 11, 654. https://doi.org/10.3390/coatings11060654 https://www.mdpi.com/journal/coatings Coatings 2021, 11, 654 2 of 9 of B increases to realize a low contact resistance of S/D. Therefore, increasing the Ge concentration remains crucial in a gate-all-around FET. However, as the Ge concentration increases, high-density defects are generated in the grown layers because the difference in the lattice parameter between the Si substrate and the SiGe layer increases [12,13]. Therefore, several techniques have been developed to minimize defects, such as epitaxial lateral overgrowth [12] and thermal cyclic annealing [13]. However, these techniques require relatively thick epitaxial layers and are not suitable for gate-all-around FETs. Herein, we studied the current boosting and defect generation in a nano-sized sigma- shaped SiGe pattern, which was designed to implement the S/D shape in a gate-all-around FET. The strain behavior in the Si channel and the formation of misfit dislocations in SiGe were investigated for various values of concentrations of Ge (CGe). The strain inside the channel was analyzed using nano-beam diffraction (NBD) and simulation. Furthermore, the change in stress owing to an e-SiGe and its effect on the electrical performance of a 28-nm-p-MOSFET were also evaluated. In this study, intrinsic SiGe was grown in one Coatings 2021, 11, x FOR PEER REVIEW 3 of 9 sigma cavity structure, but B-doped SiGe will be grown in various sigma cavities in the future to study changes in device characteristics. Finally, the 2.L3 Materials layer was and made Methods of pure Si fabricated using the epitaxy method, which capped the L2 layer.The TheCGe L3effect layer in acted current as boostinga sacrificial by layer SiGe wasto supply examined the necessary using a p-MOSFET Si for device forming thewith silicide-reduced a planar gate contact structure. resistance A multilayer in the SiGe,S/D region. comprising To supply layer 1hole (L1)/layer carriers 2 (L2)/layer in the S/D region,3 (L3), boron was formed was incorporated using the process in situ at flow doping shown concentrations in Figure1a afterof less a sigmathan 1 cavity was × 1019 and 2created × 1020 atoms/cm to implement3 in L1 the and S/D L2, shape respectively. in a gate-all-around After the FET.native The oxideCGe distributionwas re- in SiGe moved throughwas in confirmed situ dry usingcleaning, a transmission the L1, L2, and electron L3 layers microscopy-energy were epitaxially dispersive grown by X-ray (TEM- remote plasmaEDX, chemical X-MAX vapor 80 TLE deposition detector, Oxford without , Abingdon, a vacuum England) break, as and shown atomic in Figure probe tomography 1d. The SiGe(APT, or Si LEAP5000XR, epitaxial layers CAMECA, of L1, L2, Gennevilliers, and L3 were France). grown Theusing misfit SiCl2 dislocationsH2 (di- in the chlorosilane,sigma-shaped DCS) and GeH cavity4 as ofprecursors, the e-SiGe and S/D the region selectivity were analyzed was determined using high-resolution by co- TEM flowing HCl(HR-TEM, gas [23–25]. JEM2100F, L1, L2, and JEOL, L3 Tokyo, were grown Japan). at The 660, strain 620, inducedand 750 in°C, the respectively. channel was calculated The fabricatedusing MOSFETs a fast Fourier showed transform uniformly image patterned obtained sigma-shaped through the cavities nano-beam in the diffraction S/D (NBD) region with methodcritical dimensions and simulated of approximat using ANSYSely 10, software 30, and (version 30 nm for 19, the ANSYS, top, center, Workbench, and PA, USA). depth of theThe cavity, electrical respectively, properties as shown of the in p-MOSFETs Figure 1e. Both were L1 characterized and L2 were using uniformly a semiconductor grown at differentparameter growth analyzer rates (Agilent,induced by B1500A, the crystal CA, USA).plane of the Si substrate [26]. Figure 1. (a) TheFigure process 1. (a) flow The andprocess schematic flow and structure schematic at eachstructure step. at ( beach) Anisotropic step. (b) Anisotropic Si etch through Si etch dry through etching using HBr, Cl2, He.dry (c) etching The sigma-shaped using HBr, Cl cavity2, He. was(c) The formed sigma-shaped through cavity wet etching. was formed (d) Multilayerthrough wet SiGe etching. epitaxial (d) growth. (e) Cross-sectionalMultilayer TEM image SiGe epitaxial after SiGe growth. growth. (e) Cross-sectional TEM image after SiGe growth. Figure 23. shows Results the and vertical Discussion and longitudinal distributions of CGe in SiGe, as measured using TEM-EDX.Figure The x1-axis shows in Figure the formation 2a,b correspond of sigma cavity to the in red the and transistor blue dots, for inducing respec- a strain in tively, in thethe inset Si of channel. Figure After2a. Ge the was Si not was det anisotropicallyected at vertical patterned positions through 1 and 2, dryindicating etching, as shown that they correspondedin Figure1b, to a the sigma-shaped Si substrate. cavity, At vertical as shown position in Figure 3, CGe1 wasc, was approximately formed at an angle of 22.6 at.%–28.554 ◦at.%,through which the increased anisotropic to approxim etchingately of the 30.2 Si (111)at.%–36.6 plane at.% with at vertical tetramethyl posi- ammonium tion 5.
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