IEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE

Strain for CMOS performance Improvement +Victor chan, +Ken Rim, #Meikei Ieong, +Sam Yang, +Rajeev Malik, ‡Young Way Teh, #Min Yang, #Qiqing (Christine) Ouyang +IBM Systems & Technology Group, #IBM Research Division, T. J. Watson Research Center and ‡Chartered Mfg. Ltd, at IBM Semiconductor Research and Development Center (SRDC) email: [email protected]

Abstract gate gate Device Improvement with strain engineering is considered a way to enhance the carrier mobility. Several Lateral Z stress-transfer techniques (such as etch-stop liner, stress Source Drain transfer technique, e-SiGe) using extra integration process Source Drain into an existing baseline process is demonstrated. In addition, new preparation techniques of strained-Si surface (e.g. biaxial tensile stress) and different substrate orientation to enhance Longitudinal mobility are introduced. The challenges and vitality of each NMOS PMOS method will be discussed and compared. In addition, we will Longitudinal X Tensile Compressive highlight how the stress oriented from the layout geometry Lateral Y Tensile Tensile affects the device electrical behavior. The issues and Si Depth Z Compressive Tensile improvement in the circuit level device modeling will be Fig. 1 Desired stress on CMOS performance discussed. Stress Engineering: Process & Results 1000 Shrinking the n(100) 900 In the coming decade, advances in CMOS fabrication will lead to devices with gate lengths from 45 to 800 below 10 nm. Shrinking size can pack more devices and 700 n(110) improves the logic switching speed. The challenges in reducing device sizes are the feasibility of fabrication, 600 @ Ioff=100nA/um @ Ion (uA/um) 100nA/um @ maintaining performance and reliability, as well as gate oxide nFET Ion (uA/um) 500 ABCDEF thinning. After more than two decades of continual and rapid 700 progress in CMOS devices technology, especially aggressive and significant pace of scaling in the last few years, the 600 scaling will apparently approach the fundamental limits of p(110) scaling, the feasibility of fabrication and device reliability. 500 Besides scaling, several innovative mobility enhancement 400 techniques are suggested to maintain the MOS performance p(100) @ Ioff=100nA/um @ improvement trajectory laid out in the ITRS roadmap. Ion (uA/um) 100nA/um @

pFET IonpFET (uA/um) 300 A B C D E F Strain helps carriers to travel faster Compressive Neutral Tensile Fig. 2 Different longitudinal stress in channel provides Mobility enhancement is an attractive option because different drive current in nominal devices. it can potentially improve device performance beyond any of the benefits from device scaling. Compressive stresses are The two main approaches being pursued are strain introduced by Shallow Trench Isolation (STI) towards engineering (from both substrate- and process-induced) and channels longitudinally and laterally. Mechanical stress orientation effects. breaks crystal symmetry and removes the 2-fold and 6-fold degeneracy of the valence and conduction bands respectively. Substrate-induced strain. One of the most effective This will lead into changes of the band scattering rates and / way to introduce high tensile strain to the channel is to or the carrier effective mass, which in turn affect carrier epitaxially grow strained-silicon on a relaxed SiGe layer (Fig mobility [1, 2]. However, NMOS and PMOS carriers have 3a). Because of the lattice mismatch between Si and SiGe, different interaction on the channel strain in three directions, the lattice of the Si layer is stretched (strained) in the plane of namely longitudinal, lateral and Si depth directions. Fig. 1 the interface. This deformation breaks the symmetry of the illustrates possible directions of uniaxial stresses and their energy band structure and results in band splitting (Fig. 4). effects on N and PMOS. Different mechanical stresses can be The reduced inter-band/inter-valley scattering and effective introduced through the wafer substrate and during the masses result in enhanced carrier transport in the strained fabrication process, which will be discussed below. NMOS silicon layer that is used as the channel of the MOSFET[2]. current is enhanced with tensile stress in channel, and PMOS Enhanced drive currents of 15 to 25% have been one is with compressive stress. 40% difference may be demonstrated on sub-100 nm bulk strained-silicon resulted if the longitudinal stress is applied (Fig 2). (Fig. 5) [2, 3].

0-7803-9023-7/05/$20.00 ©2005 IEEE. 23-3-1 667 1E-6 10001000 Str. Si / Relax SiGe 28% 1000 Str. Si / Relx. SiGe 28% a) Strained Si/SiGe b) SiGe-on-Insulator c) Strained-Si Strain Str. Si/SiGe Si / SiGe (13% (13%[Ge]) Ge) Str. Si Si / Relx. / Relax SiGe SiGe 13% 13% Control Str. Si Si / Str. / Str SiGe SiGe 30% 30% / Relx. / Relax SiGe 13%SiGe 13% on bulk wafer (SGOI) MOSFET Directly On 1E-7100 Control 800800 Insulator (SSDOI) 1E-8 nFET 600600 /um) 10 A m) P 400 (A/ 1E-91 400 off I

Strained Si Strained Si Strained Si Ioff (n 110% 200200 110% 1E-100.1 SiGe SiGe Controlcontrol Universal Mobility Buried oxide Effective Electron (cm/V*sec) Mobility Universal Mobility Buried oxide 00 1E-110.01 0.00 500.0k0.5 1.0 1.0M 1.5M1.5 400.0μ 600.0μ 800.0μ Effective e- Mobility (cm/V-sec) Effective Field, E (V/cm) 400 600 800 Effective Field (Eeff (MV/um)) Si substrate I (A/Pm) eff Si substrate Si substrate Ion on(uA/um) 1E-61000 Fig. 3 Schematic diagram to show three ways of formation pFET of strained Si MOS devices [2,4-5]. 1E-7100

The performance benefit of combining strained m)

P 1E-810

silicon with an SOI has also been demonstrated in a 60 nm (A/ off I gate-length, n-channel MOSFET with ultrathin thermally Ioff (nA/um) 1E-9 mixed /SiGe on insulator substrate (strain-Si 1 Strain StrainS tr. SSi i/S / /SiGe SiGe iG e (28% (28 (28% Ge) % [GGe) e]) on insulator SSOI, SiGe on insulator SGOI) (Fig 3b) [4]. 20- Control ControlControl 1E-100.1 25% device enhancement is demonstrated at short channel 200.0μ200 400.0μ400 600.0μ 600 I (A /P m) length. Ionon (uA/um) Recently, Rim et. al. [5] demonstrated Fig. 5 NMOS and PMOS show benefits with biaxial tensile strained using ultrathin strained silicon directly on insulator (SSDOI) Si of 13 & 28% Ge respectively [2]. structures (Fig 3c) that eliminate the SiGe layer before transistor fabrication, thereby providing higher mobility while SiGe is then selectively removed, and transistors are mitigating the SiGe-induced material and process integration fabricated on the remaining ultra-thin strained Si. Both problems. A SSDOI structure is fabricated by a layer-transfer electron and hole mobility enhancement have been observed or “wafer-bonding” technique. First, an ultra-thin layer of indicating strain is retained after the complete device strained silicon is formed epitaxially on a relaxed silicon processing steps [5]. (SiGe) layer, and an oxide layer is formed on top. The presence of the SiGe layer in strained silicon After hydrogen is implanted into the SiGe layer, the wafer is substrate leads to several materials and integration-related flipped and bonded to a handle substrate. A high-temperature challenges. For example, SiGe strain relaxation layer induces process splits away most of the original wafer, and leave the high density of defects in strained silicon. Dopant diffusion strained Si and SiGe layers on top of the oxide layer. The rate in SiGe is significant different from that in Si. Boron diffusion is retarded while arsenic diffusion is enhanced. Additional efforts in junction engineering to control short- channel effects and to set the MOSFET threshold voltages to the desired values is required. Significant device self-heating is also observed in strained Si/SiGe devices because of the lower thermal conductivity in SiGe [2, 4-5].

Process-induced strain. Besides using substrate to provide stress in channel, strain effects induced during the fabrication process can increase the channel mobility. Both tensile and compressive stresses can be introduced to the channel in any one of the three dimensions by different process techniques [6,7]. 65nm bulk and SOI CMOS technologies with 45nm channel length and 12A gate oxide are used for study. Different stress-transfer techniques, such as contact etch stop liner, Stress Memorization Technique, and embedded SiGe in the source / drain (S/D) will be discussed in the following.

Fig. 4 Biaxial stress effects on the conduction and valence bands of a) Contact end-stop stress liner. strained Si. Biaxial tension splits the 6 fold dengerate conduction Mechanical stress can be transferred to the channel valleys into 2 fold and 4 fold, and lowers 2 fold degnerate valleys so through Si active area and poly gate if a permanent stressed- that electrons preferentially populate these valleys that have lower in- plane transport mass. So increases with tension. liner is deposited on a device. Tensile liner will enhance Biaxial tension also splits the heavy and light hole bands. So in a 2- NMOS and compressive liner will enhance PMOS mobility dimensional hole gas in inversion layer, the tension first negates the respectively. The integration process will be described as band splitting caused by quantum confinement, and further strain begins below. After silicide formation (either cobalt or nickel to split the bands in the opposite polarity from the confinement-induced silicide), a highly stress liner (either tensile or compressive), splitting. So high tensile strain results in significant valence band such as PECVD (Plasma Enhanced Chemical Vapor splitting which leads to hole mobility enhancement [2].

668 23-3-2 Deposition) or RTCVD (Rapid Thermal CVD) nitride), is uniformly deposited over the wafer. The drive current Tensile nit Contact Compr nit dependence on stress is through the change in film thickness and material [8]. The remaining steps follow a conventional N P process flow, including interlayer dielectric and contact formation. Thicker nitride capping layer can increase the ST stress level. However, this will impact the conformity of gap fill itself, subsequent interlayer dielectric (ILD) gap fill, and contact opening process. Fig. 6 shows the drive current improvement for tensile Compr NMOS with tensile stress and PMOS with compressive stress liner [9]. Tensile liner improves NMOS current by 11% (and 17% after self-heating correction) and compressive liner N P improves PMOS current by 20% than that of the non-stressed process. If one single liner is used, one drawback of this Fig.7 SEM cross-section of an SRAM cell features tensile and approach is that the device of the opposite type will be compressive liner in NMOS and PMOS respectively [9]. degraded. One of the possible solutions is to use high dose of Ge implantation to destroy the nitride film and relax its stress nitride liner is deposited, and this film is also selectively [10]. For example, a highly tensile stress nitride film is etched on the NMOS region. This process can be applied in deposited over both N & PMOS, and Ge is selectively the reverse order. Fig. 7 shows the SEM cross-section taken implanted into PMOS region to relax the nitride stress. It is from a SRAM cell with the Dual Stress Liner (DSL) process advised that the subsequent processes to have low thermal [9]. Compared to non-stressed process, DSL process results budget to prevent the stress stability of the liner. ring oscillator delay with 12 - 24%, dependent on the fan-out TM The above method cannot provide both NMOS and loading. IBM PowerPC Fmax vs. power PMOS to their highest performance. In order to achieve improves 7% with DSL compared to single tensile liner. TM ultimate CMOS performance, two types of stress liners should AMD Athlon 64 microprocessor [9] Fmax vs. power be applied to NMOS and PMOS accordingly. For example, a improves 12 % with DSL compared to non-stressed liner. highly tensile nitride liner is deposited first. It is selectively etched on the PMOS regions. Next, a highly compressive b) Stress Memorization Technique. Local strain can be applied to the channel through a Stress Memorization Technique. In the conventional 10-4 a) NMOS fabrication process, Source / Drain Si area and poly gate are amorphized by S/D and extension implantation. In the stress 10-5 memorization process, conventional dopant activation spike

m) anneal is performed after the deposition of a tensile stressor P Un-stress capping layer, such as nitride (Fig 8) [11-13]. The nitride -6 10 layer will subsequently be removed, and the next step is tensile

Ioff (A/ salicidation. The stress effect is transferred from the nitride 10-7 film to the channel during annealing and memorized by the re-crystallization of the S/D and poly gate amorphized layers. After active area and gate re-crystallization, the stress inside 10-8 the channel is memorized. Since the nitride film is disposable, 700 900 1100 1300 Ion (PA/Pm) a very thick capping layer can be used to increase the stress level without any process limitation. 10-5 b) PMOS A 15% of NMOS improvement is demonstrated when this modular stressor element is added on top of a etch- -6 stop liner, as shown in Fig. 9. The amount of drive current 10 Compressive Un-stress improvement is related to the amorphous layer, anneal

m) condition and stress level of the nitride liner. P 10-7 c) Embedded SiGe in S/D

Ioff (A/ Besides the introduction of nitride stressor, a more 10-8 direct way to provide strain to channel is filling S/D with SiGe. One suggestion is, epitaxial-grown strained SiGe (e- 10-9 SiGe) is embedded in the S/D regions [14-16,26] or extension 350 450 550 location [17] (Fig. 10). When the lattice spacing of this SiGe Ion (PA/Pm) material is larger than Si, uniaxial compressive strain is Fig.6 Ion enhancement using stress liner compared to neutral induced to the channel. Extra integration processes are liner (non-stressed process) for a) nMOS and b) PMOS [9]. inserted after spacer formation, such as selective Si recess

23-3-3 669 Amorphous layer AmorphorusBy implant layer by implant N P

n+ n+ p+ p+ STI

Tensile Nit Oxide N P

n+ n+ p+ p+ STI Fig.10 SEM photo of PMOS with e-SiGe structure in S/D [26]

Anneal & nit removal

N P

n+ n+ p+ p+ STI Si is crystallized and stress is memorized

Fig. 8 Integration process of SMT. a) after S/D implantation; b) oxide and tensile nitride deposition; c) S/D and poly dopant activation anneal; d) nitride removal; e) salicidation and subsequent processes.

Fig. 11 PMOS Ion-Ioff for e-SiGe 10001e-05 (Courtesy from , 2004 Fig. 8 of [16]) control discussed in Fig. 2. Device drive current can be effectively 1001e-06 modulated by mechanical built in stresses. Careful selection on process modular enhancer is necessary to prevent enhancement of one type and degradation of another type of 1e-07 Tensile Nit 10 carriers, and the expense of higher process complexity, cost stressor

nFET Ioff (nA/um) and integration yield. A complete stress model on device NMOS Ioff (nA/um) parameters, especially Ion and Vt, is recommended for an 1e-08 1 0.006 0.007 0.008 0.009 0.01 0.011 0.012 0.013 0.014 600 700 800 b 900 (M1FN10 1000 100 08 01100 07M1 I 1200 ) 1300 1400 accurate circuit simulation and verification. NMOSnFET Ion Ion ((uA/um)uA/um) Strained Si begins to be implemented in 65 and Fig. 9 15% NMOS current improvement with Disposable Tensile 90nm technologies. Fig. 12 shows the IonN / IonP ratio in the Stressor. Tensile contact etch-stop liner is used. recent three generations. The enhancement of drive current from strained Si process will influence the rise and fall time etch in the S/D regions, and selective and insitu-doped of circuit logic stages and hence overall performance. epitaxial SiGe growth. NMOS was protected by capping Applying strain enhancement to both N and PMOS can adjust layer to prevent Si recess and SiGe epitaxial growth. This the ratio back to the appropriate levels, such as DSL (Fig. 7). structure creates a large uniaxial compressive stress to the Moreover, Vt shift associated with shift in band PMOS channel, thereby resulting in significant hole mobility edges due to channel strain is seen on both NMOS and PMOS improvement. An apparent drive current improvement from 2.6 Intel published data is shown in Fig. 11. Neutral N, Neutral P The compressive stress is mainly dependent on the e- 2.4 SiGe thickness in the S/D, both below and above (raise S/D) the Si surface, and % Ge content in the SiGe. Too high Ge 2.2 Tens N, Neut P content may cause defects and yield issue. Moreover, the improvement will be also degraded for small S/D overhang 2.0 regions ((distance from poly gate to STI edge), Further Tens N, Compr P 1.8 optimization in process is necessary to reduce the adverse ratio IonP / IonN Neut N, Compr P effect [15]. 1.6

Implications 1.4 20 30 40 50 60 70 80 90 100 110 120 130 140 The electron and hole mobility has different technology (nm) dependence on the type of uni-axial stresses and this has been Fig.12 IonN / IonP ratio in the recent technologies. 670 23-3-4 devices (Fig 13). The uni-axial stress produced by the be degraded. Besides stability margin and write margin, read process transfers the stress through S/D overhang regions and and write performance are also important. Gamma Ratio of poly gate to the channel resulting variation of stress along the I(passgate) / I(pull-up) and Beta Ratio of I(pull-down) / channel. Hence, the Vt shift is dependent on both channel I(passgate) must be adjusted to meet the operation length and active area geometry. Appropriate Vt adjustment requirements. If NMOS current becomes higher, Beta Ratio through channel or halo implant can compensate this. remains the same and Gamma Ratio increases. The WRM is better but ADM will be degraded. On the other hand, if 0.30.30.3 control PMOS current becomes higher, Gamma ratio is reduced. The 0.2 Un-stress 0.20.2 Disposable cell will be written more slowly. ADM will be better and StressorTensile more stable. Thus, Vt and current have to be adjusted when 0.10.10.1 stress engineering is implemented. In addition to 00 n POR conventional Vt-adjustment and halo implantation correction n OP

Vtlin (V) Vtlin -0.1 -0.1-0.1 p POR to modulate the drive and standby current, stress-transfer Vtlin (V) Vtlin(V) Un-stresscontrol p OP modular process is important. For example, the stress level in -0.2-0.2 -0.2 the nitride film during SMT process and etch stop liner in the -0.3-0.3 Tensile -0.3 Disposable Stressor process DSL process can affect both drive current and Vt. Without pMOS selective RIE -0.4-0.4-0.4 The annealing temperature is also critical in the 0.01 0.1 0.010.01 Lpoly 0.1 (um) stress transfer process. It will also affect the device reliability, Lpoly (um) such as hot carrier concern. Moreover, different methods of Fig.13 Vt shift due to tensile stress built along the channel. stressor deposition, such as nitride film, may provide different

When the technology reaches deep submicron 25 W(um) regime and the active area becomes small, the drive current 0.12 n-10x0.045 20 n-0.24x0.045 can be modulated by the mechanical stress from the STI. The n-0.12x0.045 source is mainly from STI corners. Longitudinal stress can be p-10x0.045 15 p-0.24x0.045 modulated by different (e.g. irregular or asymmetrical) S/D 0.24 p-0.12x0.045 overhang regions, whereas different lateral stress can be 10 active size obtained by different channel widths and adjacent active area. PFET Figs. 14-15 investigate the effect of STI proximity to the gate 5 10 edge in device performance [1,18-20]. PMOS exhibits higher 0.12 Ion at constant Ioff with smaller S/D overhang regions i.e. 0 higher compressive stress from STI in longitudinal direction, 0.24

whereas NMOS Ion is decreased. When the channel width is (%) change current drive -5 reduced, NMOS is less sensitive to the stress effect; on the 10 NFET contrary, PMOS becomes more sensitive to it. The stress -10 varies along the channel and hence different channel lengths 0 0.2 0.4 0.6 0.8 1 1.2 1.4 received different stress effects. STI proximity has minimal active size (symmetric) (um) effect on long channel devices (Fig. 14). As the gate length Fig.14 STI mechanical stress effect (different active width) reduces, the STI stress effect becomes significant, but reduces on the NMOS & PMOS drive current changes with when the gate length is nominal and short. This suggests that different device width. All current is relative to the drive current of the nominal devices is controlled by the Wx0.045um with active size = 1.2um [18]. halo dose and carrier scattering. From Figs. 14-15, devices always have STI stress 25 proximity effects, especially in small S/D overhang regions. n-10x0.045 20 n-10x0.24 The effects can be reduced by process material but cannot be n-10x10 fully eliminated. In general, > 50% devices with 2x minimum p-10x0.045 15 p-10x0.24 distance of gate to STI edge in a product [1]. Therefore, p-10x10 10 understanding the phenomenon and fundamental behavior can active size help to build and develop an appropriate circuit level device PFET 5 model, rather than using isolated test structure as baseline model. 0 From the discussion above, stress engineering induced from process integration will affect the Vt and drive -5 current. This will also affect the SRAM design, such as the drive current change (%) -10 NFET cell stability (access disturb margin, ADM) and writability (write margin, WRM). ADM is bigger with weak NMOS and -15 strong PMOS, whereas bigger WRM comes from strong 0 0.2 0.4 0.6 0.8 1 1.2 1.4 NMOS and weak PMOS. SRAM operation margin (ADM & active size (symmetric) (um) WRM) vary inversely with device current tolerance. If the Fig.15 STI mechanical stress effect changes on different device drive current tolerance increases, the operation margins will length. All current is relative to 10xL with active size = 1.2um [18].

23-3-5 671 130 conformity and uniformity; hence affect the stress level in the 120 device channel. Furthermore, many stress-induced processes a) (100) substraten(100) involve lithography and etching. The new processes may 110 violate the minimum design ground-rule, such as lithography 100 overlay margin and etch bias in the cell layout design of the 90 SRAM cells.

Ion change (%) change Ion p(100) As discussed above, stress-induced process can 80 impact device variances. This can translate into impact on 70 A BCDEF circuit performance and yield. Circuit and layout designers 120 should understand the impact of any new stressed-transfer processes and the chance of under-performance devices. 110 b) (110) substrate n(110) Layout of devices in a critical path should be drawn in a less 100 stress-sensitive way, for example, larger S/D overhang regions (Figs. 14-15). 90

The fabrication line should implement appropriate (%) change Ion 80 p(110) methods to monitor the process, such as in-line nitride 70 deposition thickness and film stress, to control the uniformity A BCDEF and repeatability of stress transfer process on large amount of Compressive Neutral Tensile transistors. Devices with different stressor process (such as Fig. 17 Different longitudinal stress in channel provides different tensile liner and neutral liner on two different devices drive current in nominal devices in a) (100) and b) (110) substrate surfaces. correspondingly) are built on same location of a wafer. From the electrical data, stresses under within chip variation, within wafer variation, within lot variation and lot to lot variation can be monitored. Furthermore, devices with different active area (and poly gate) geometries, sizes, and density should be monitored to check the micro-loading effect from film (100) deposition and etching. (110) Mobility improvement beyond stress engineering 110 handle wafer Besides substrate-induced and process-induced stress Fig. 18 Schematic cross-section and SEM of CMOS on a hybrid- engineering, wafer substrate orientation and channel substrate with PMOS on (110) surface orientation and NMOS on (100) surface orientation [24]. orientation can improve mobility. Different surface orientation and direction of applied field for different in-plane Technology (HOT). NMOS is fabricated on the Si substrate stress provide different interaction with carrier transports [21]. with (100) surface orientation and PMOS on (110) surface a) Substrate Orientation orientation [23, 24] (Fig. 18). Two types of hybrid substrates Beside strained Si in the traditional (100) plane, it are shown in Fig. 19: Type A with PMOS on (110) SOI and may be advantageous to change the crystal orientation to NMOS on (100) Si epitaxial layer, and Type B with NMOS optimize CMOS circuit performance. The carrier mobility of on (100) SOI and PMOS on (110) Si epitaxial layer. The inversion layers depends on surface orientation and current hybrid substrate was formed by layer transfer technique flow directions, due to asymmetry of the carrier effective through wafer bonding (Fig. 19). Layer transfer process, masses in the Si crystal lattice [22]. The definition of block-level trench etch and epitaxial re-growth were substrate orientation and carrier direction is described in Fig. performed before the conventional CMOS device process (Fig. 16. For PMOS, hole mobility is 2.5 times as high on (110) 20). surface orientation as on a standard (100) wafer surface, CMOS on the hybrid orientation substrates were depending on the applied effective vertical field. However, fabricated with NMOS on (100) SOI and PMOS on (110) epi- electron mobility is degraded on the (110) substrate. Similar Si (Fig. 18). The drive current of PMOS has 30-40% to devices fabricated on (100) substrate, those on (110) improvement compared to device on (100) substrate (Fig. 21). substrate are sensitive to longitudinal stress and have similar There is no NMOS degradation in HOT and the behavior is stress characteristics (Fig. 17). similar to those on (100) wafers. Other device characteristics To fully realize the advantage of the carrier mobility such as Vt roll-off, junction capacitance and leakage and dependence on surface orientations, new design and extension overlap region are very similar between (110) and integration have been developed for the Hybrid Orientation (100) substrates. These indicates similar dopant diffusion rate in both substrates. With great PMOS current improvement, (100) plane (110) plane ring oscillator delay can be improved up to 21% [24, 25], dependent on channel length, fan-out and circuit components. Further performance gain can be achieved by <011> channel <110> channel integrating HOT technology with strained Si, for example, e- SiGe [26], and DSL [27]. Fig. 22 shows our recent best PMOS performance with (110) and stress engineering. Drive Fig 16 Devices are fabricated on two wafer orientations. Current flow direction relative to wafer flat is indicated. current of 720uA/um at Ioff=100nA/um is observed. 672 23-3-6 Type A Type B H H Oxide Oxide (110)

(100) substrate (100) Step 1: Buried oxide formation and H I/I.

(110) substrate (100) substrate

Oxide Oxide

(100) Si handle (110) Si handle wafer wafer

Step 2: Flip-bond implanted wafer to handle wafer with different orientation. (100)

(110) SOI (100) SOI Oxide Oxide (100) Si handle (110) Si handle wafer wafer

Step 3: Wafer split and SOI thinning.

Fig. 21 Characteristics of HOT CMOS. PMOS on Fig. 19 Process flow of form the hybrid-substrates (type A & type B) [23]. (110) epi-Si and NMOS on (100) SOI [24].

Nitride Nitride Nitride epi-Si 1.E-06 SOI SOI SOI SOI BOX BOX BOX BOX

Si handle wafer Si handle wafer Si handle wafer 1.E-07 (100) Step 1 Thin oxide/nitride Step 2 SOI/BOX stack etching and Step 3 Si epitaxy and CMP. deposition. spacer formation.

PMOS loff (A/um) (110)+strain Si epi-Si epi-Si SOI SOI epi-Si SOI BOX BOX BOX 1.E-08 400 500 600 700 800 Si handle wafer Si handle wafer Si handle wafer PMOS Ion (uA/um) Fig. 22 PMOS on (110) substrate Step 4 Si etch back and Step 5 Shallow trench Step 6 Continue CMOS isolation. performance is further enhanced by stress thin nitride/oxide strip. fabrication. engineering.

Fig. 20 Process flow of fabricating CMOS on hybrid substrates [23]. b) Channel Orientation Design and Stress Control Summary and Trade-offs On a (100) Si substrate wafer, carriers under the poly In the nano-technology era, strained Si will be added gate can flow in different directions (Fig. 23). Holes in the to continue the Moore’s Law. Mobility enhancement <100> channel has less sensitivity on mobility from channel technique is attractive and has been discussed above. Some stress than <110> channel, as shown in Fig. 24 [28, 29]. options can be combined for even higher performance gains. However, electrons mobility have the same sensitivity from the stress in both <100> and <110> channels. This advantage (100) plane (100) plane brings the technology using higher tensile stress (e.g. contact etch-stop liner) to improve NMOS mobility, and PMOS mobility is not degraded even without selective etch or implantation during stress-transfer process. This can reduce the fabrication complexity. No extra substrate preparation is <110> channel, 0 deg notch <100> channel, 45 deg notch required, except that appropriate wafer notch is considered. Fig.23. <110> and <100> channel on (100) plane.

23-3-7 673 p,, PMOS performance cannot be further improved by other 1000 stress transfer method. Carrier direction Ultimate circuit level device model should include <110> all the stress effects, including different channels and widths, 100 S/D overhang regions, distance from adjacent active area in both longitudinal and transverse direction, and their sizes. Carrier direction Combination of different uni-axial stress from different 10 <100> directions will form bi-axial stress effects, leading the model pFET Ioff (nA/um) to be more complicated. The uniaxial channel stress is induced from the sides 1 0.0002 0.0003 0.0004 0.0005 0.0006 of the device. Devices with different channel lengths have 200 300 M1 400 FPRVT1x_08 M1 Io500 n 600 . pFET Ion (uA/um) different stress effects. Many mobility enhancement methods Fig. 24 20% improvement in pMOS current with <100> carrier involve uni-axial stress through the active area, such as S/D direction on (100) substrate when stressed etch stop nitride is used. area. The improvement may reduce from ideal isolated In fact, some of them have been integrated in a modular devices to devices inside a product. fashion into any existing baseline process for integrated circuit manufacturing. Extra process complexity, cost and Acknowledgements yield should be carefully considered (Table 1). In addition, This work is supported by the independent alliance programs extra process steps may involve extra film deposition or etch. for SOI Technology Development (Sony Electronics Inc., Toshiba America Electronic Components, Inc. and , Extra plasma damage and low temperature process may lead Inc.), Bulk CMOS Technology Development (Chartered Semiconductor to reliability issues. Mfg. Ltd, Infineon Technologies AG and Samsung Electronics Co. Ltd) Biaxial tensile strained Si is considered as a and IBM Yorktown Research Division). The authors would like to thank technique in the last decade. However, it has been difficult to Scott Crowder and Lisa Su for their support of this work. implement because of misfit and threading dislocations, Ge out-diffusion, silicide formation difficulty, self-heating effect, References higher As diffusion in the S/D extension region, and cost. [1] C. Diaz et al., CICC Proceeding,, May 2002, pg. 475-478 [2] K. Rim et al., VLSI Symposium, June 2002, pg. 98-99 DSL (contact etch stop layer) provides enhancement [3] H. C. H. Wang et al., IEDM Tech. Dig.,Dec 2003, pg. 61-64 in both NMOS and PMOS. It needs extra steps and ground [4] B. H. Lee et al., IEDM Tech. Dig.,Dec 2002, pg. 946-948 rule in the liner boundary and contact opening may be a [5] K. Rim et al., IEDM Tech. Dig., Dec 2003, pg. 49-52 concern. This has been implemented in IBM PowerPCTM and [6] C. H. Ge et al., IEDM Tech. Dig., Dec 2003, pg. 73-76 TM [7] S. E. Thompson et al., Trans. Elec. Devices, Vol 51, Nov 04, pg. 1790-97 AMD Athlon . [8] S. Ito et al., IEDM Tech. Dig., Dec 2000, pg. 247-250 SMT (Stress Memorization Technique) needs extra [9] H. S. Yang et al., IEDM Tech. Dig., Dec 2004, pg. 1075-78 steps and is easy to be implemented. It does not have any [10] A. Shimizu et al., IEDM Tech. Dig., Dec 2001, pg. 433-436 major process or ground rule limitation. However, it can only [11] K Ota et al., IEDM Tech. Dig., Dec 2002, pg. 27-30 [12] C. H . Chen et al, VLSI Symposium, June 2004, pg. 56-57 improve NMOS performance. [13] R. Khamankar et al., VLSI Symposium, June 2004, pg. 162-163 e-SiGe in S/D structure provides highly compressive [14] T. Ghani et al., IEDM Tech. Dig., Dec 2003, pg. 978-980 strain to the channel, and results in large hole mobility [15] K. Mistry et al., VLSI Symposium, June 2004, pg. 50-51 improvements. Extra complicated integration steps are [16] P. Bai et al., IEDM Tech. Dig., Dec 2004, pg. 657-660 [17] P. R. Chidambaram et al., VLSI Symposium, June 2004, pg. 48-49 necessary; nevertheless, it can provide very good PMOS [18] V. Chan et al., IEDM Tech. Dig., Dec 2003, pg. 77-80 performance. [19] R. A. Bianchi et al., IEDM Tech. Dig., Dec 2002, pg. 117-120 HOT technology ((110) substrate) clearly shows an [20] Y. M. Sheu et al., VLSI Tech, Sys & Appl, 2003, pg. 269-272 attractive option to improve device performance. However, [21] M. V. Fischeitti et al., J. Appl. Phys, June 2003, pg.1079 -1081 [22] Sato et al., Phys Rev. B, Condens. Mat, 1971 Vol.4, pg. 1950-60 the impact on circuit performance of mixing SOI and bulk [23] M. Yang et al., IEDM Tech. Dig., Dec 2003, pg. 453-456 devices on the same chip and circuit design will require more [24] M. Yang et al., VLSI Symposium, June 2004, pg. 160-161 detailed analysis. [25] L. Chang et al., Trans. Elec. Devices, Vol. 51, Oct 2004, pg. 1621-27 Channel orientation (<100> channel, 45 deg notch) [26] C. Ouyang et al., VLSI Symposium, June 2005, accepted [27] C. Sheraw et al., VLSI Symposium, June 2005, accepted is a highly manufacturable technique to reduce integration [28] T. Komoda et al., IEDM Tech. Dig., Dec 2004, pg. 217-220 complexity. It allows NMOS improvement by other stress- [29] K. Uchida et al., IEDM Tech. Dig., Dec 2004, pg. 229-232 transfer process, without any PMOS degradation. However,

NMOS PMOS Disadvantage & limitation Biaxial Tensile Strain ĹĹExtra cost on substrate, difficulty in material, integration, & device design. Contact etch-stop liner (DSL) ĹĹExtra steps in integration, ground rule consideration SMT Ĺ o Extra steps in integration e-SiGe o Ĺ High process complexity, difficulty in epi-growth, yield Substrate Orientation (HOT) o Ĺ Extra Cost on hybrid substrate, extra steps eg. Epi to prepare isolation Channel Orientation (<100>) o Ĺ No further improvement in PMOS current Table 1 Summary of all feasible technologies for mobility enhancement. Extra processes are considered, such as selective etch or implantation to prevent performance degradation.

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