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Stress Mapping in Strain-Engineered Silicon P-Type MOSFET Device: a Comparison Between Process Simulation and Experiments Christophe Krzeminski

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Stress Mapping in Strain-Engineered Silicon P-Type MOSFET Device: a Comparison Between Process Simulation and Experiments Christophe Krzeminski Stress mapping in strain-engineered silicon p-type MOSFET device: A comparison between process simulation and experiments Christophe Krzeminski To cite this version: Christophe Krzeminski. Stress mapping in strain-engineered silicon p-type MOSFET device: A com- parison between process simulation and experiments. Journal of vaccum Science and Technology B, 2012, 30 (2), pp.022203-1. 10.1116/1.3683079. hal-00624131 HAL Id: hal-00624131 https://hal.archives-ouvertes.fr/hal-00624131 Submitted on 13 Feb 2012 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. APS/xxxxx Stress mapping in strain-engineered silicon pMOSFET device using process simulation C. Krzeminski1 Institut d’Electronique de Micro´electronique et de Nanotechnologie (IEMN-UMR CNRS 8520), D´epartement ISEN, Avenue Poincar´e, 59650 Villeneuve d’Ascqa) Strain engineering is the main technological booster used by semiconductor companies for the 65 and 45nm technology nodes to improve the channel mobility and the electrical performance of logic devices. For 32 and 22nm nodes, intense research work focuses on the integration and optimisation of these different techniques by cumulating the effects of different stressors. To estimate the level and the distribution of the stress field generated in the transistor channel by such multiple processing steps is a complex issue. Process simulation has a role to play in order to face the many challenges in term of scalability, yield and design. The objective of this paper is first to evaluate the stress distribution generated by the two most usual processing steps: Contact Etch Stop Liner (CESL) and embedded SiGe Stressors (eSiGe). Next, the final stress field in nanoscale device resulting of these intentionally but also parasitic sources are evaluated. Process simulations have been able to quantify the global trend observed in these stressors in relatively close correlation with experiment. PACS numbers: 82.20.Wt,85.40.Bh, 83.85.St a)Electronic mail: [email protected] 1 I. INTRODUCTION For CMOS devices downscaling, sharp requirements have been defined by the Interna- tional Technology Roadmap for Semiconductors (ITRS) in terms of drive current, off state current, power density, making the geometric scaling a challenging task3. The new vec- tor adopted to extend the Moore’s law is the channel mobility enhancement through the introduction of stress in the channel4. Different method of stress engineering have been in- troduced to boost the electrical performance of the logic devices. Intense research work has been devoted in the last decade to increase the channel mobility by biaxial layer but it has been observed to be difficult to implement for technical and cost issues. Local mechanical stress control5 and uniaxial stress are on the fundamental point of view more favourable on the band structure engineering and the resulting mobility enhancement6 and easier to implement on the technological point of view7. Several technological stress-transfer techniques have been developed in order to intro- duce such uniaxial stress in the channel device. First, embedded SiGe stressors (eSiGe) in the source/drain regions have been proposed to induce a compressive stress in the pMOS channel8–12. The filling of the source/drain by a SiGe material with a lattice spacing larger than silicon leads to a large compressive stress in the channel and drive current improvement13. Next, an another technique is the deposition of a stress material on top of the gate stack after silicide formation. If one single liner is used, the electrical performance of the opposite type of device will be degraded. With the possibility to engineer compressive or tensile stress depending on the process conditions with nitride film14, successful integration of dual Contact Etch Stop Liner (CESL) have been reported15. Uniaxial strain boosters have been widely adopted in order to increase the performance of logic device for the 90nm8 down to 45nm technology nodes16. Some studies focuses on the optimisation of these dif- ferent techniques in order to enhance the stress level generated and also on the integration with the main aim to cumulate the effect of different stressor12. Research activities are also dedicated to enhance the stress level generated by these different uniaxial stress techniques. Despite these large technological progress, many challenges are faced by the uniaxial stress engineering approach for 32nm technology nodes and below in terms of scalability since the stress coupling effect between the gate pitch and the various stressors like eSiGe and CESL is expected to be smaller for decreasing nodes17. Next the yield is also concerned with the 2 integration of multiple sources of local and global stress in such a way that the channel mo- bility is enhanced without exceeding the local critical shear where defects appears. Finally, circuit design is also pitch-and layout-dependent effects must be taken into account as the device geometries shrink and strain distribution should be investigated on a larger scale. Therefore, intense research work have been dedicated the last few years to develop or im- prove ex-situ or in-situ characterisation techniques in order to quantify the strain introduced in nanoelectronics device. MicroRaman Spectroscopy (µ-RS)18 and Coherent Beam Elec- tron Diffraction (CBED)19 analysis are the most often usual characterisation technique20. However with these two techniques, the stress field can only be investigated in a few points of the structure. Significant progress have been achieved with the development of the Ge- ometric Phase Analysis (GPA) technique21 which enable a more complete two dimensional mapping of strain field component in silicon crystalline on relatively large scale ∼ µm with a resolution of a few nanometers. On the other side, a direct confrontation between CBED and GPA analysis using High-Angle Annular-Dark-Field Scanning Transmission Electron Microscopy (HAADF STEM) shows that the difference in absolute strain measured could exceed 300 MPa22. In the present case, the difficulty to define a strain reference relative to the unstress level is probably the main source of discrepancy. An other study also stress the influence of sampling preparations in stress evaluation23. Even if these remarkable ex- perimental achievements clearly improve the understanding on how stress is generated and distributed in the silicon channel of the nanodevice, some limitations are faced. In order to address these challenges associated to downscaling, process simulation and TCAD tools have probably a significant and complementary role to play in order to provide guidelines for process optimisation. In comparison to dopant diffusion modelling24, very few studies have been dedicated to the stress simulation. The modelling of the stress by TCAD tools was introduced in the 90’s in order to estimate the stress generated by silicon oxidation in the case of LOCOS (LOCal Oxidation of Silicon) and next STI (Shallow Trench Isolation) fabrication. The aim was to make predictive simulations in order to provide guidelines for the stress minimisation generated by various process steps such as oxidation, nitride deposi- tion, densification, implantation, silicidation25,26 and also to minimize defects formation. As discussed previously, the philosophy has radically changed as stress engineering is now the principal technology booster to improve electrical device performance for logic nanodevice. 3 This approach impacts largely process simulation tools as it is critical to evaluate layout dependent stress variations and to take into account the influence on the design information flow27. Some recent research work have been undertaken for the simulation of the stress field generated by these technological booster. Different strained-silicon options have been analysed with simple stress simulations28. The amount of stress generated in the channel by eSiGe stressor has been estimated29,30. Eneman et al. also investigate the scalability of eSiGe stressor31,32. Stress transfer has been found to be highly dependent on downscaling and to decrease with the dimension of the active area. However, some questions remain open concerning the predictivity of these results. For example, in the case of the stress field generated by CESL, Loiko et al.33 criticises the method often used for the modelling of the stress introduced by the deposition step. Orain et al.34 perform a complete 3D mechanical simulation study using a pseudo-3D structure in order to investigate the complex mecha- nisms responsible of the stress transfer for CESL. The main objective of this work is first to investigate the stress field generated for several front-end key step and next to evaluate the stress mapping for a stress-engineered pMOSFET. In this study, the paper is organised as follow : in the first section, the stress modelling and the rheological parameters used are briefly presented. The stress distribution for eSiGe and CESL stress booster on simple test structures are simulated and confront to available experimental characterisation.
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