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Challenges and Innovations in Nano‐CMOS Transistor Scaling

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Challenges and Innovations in Nano‐CMOS Transistor Scaling Tahir Ghani Intel Fellow Logic Technology Development October, 2009 Nikkei Presentation 1 Outline • Traditional‐Scaling ‐ Traditional Scaling Limiters, Device Implications ‐ Intel’s Response • Post “Traditional‐Scaling” Innovations ‐ Mobility Booster: Uniaxial Strain - Poly Depletion Elimination: Metal Gate - Gate Leakage Reduction: HiK • Future Challenges and Options - Power Limitation - Potential New Transistor Structures and Materials 40+ Years of Moore’s Law at INTEL: From Few to Billions of Transistors 2X transistors every 2 years Transistor Count has Doubled Every Two Years 40+ Years of Moore’s Law at INTEL: From Few to Billions of Transistors 2X transistors every 2 years Traditional Scaling Era END OF TRADITIONAL SCALING ERA ~ 2003 Lasted ~40 YEARS Top “Traditional-Scaling” Enablers R. Dennard et.al. IEEE JSSC, 1974 • Gate Oxide Thickness Scaling - Key enabler for Lgate scaling • Junction Scaling - Another enabler for Lgate scaling - Improved abruptness (REXT reduction) • Vcc Scaling - Reduce XDEP (improve SCE) - However, did not follow const E field 1990’s: Golden Era of Scaling Vcc, Tox & Lg scaling & increasing Idsat Year 2000: INTEL 90nm CMOS Pathfinding End of “Traditional-Scaling” Era Gate oxide running Mobility degrades out of atoms with scaling 1.E+04 Jox limit VLSI Symp. 2000 300 Universal 1.E+03 NA= Mobility 3x1017 ] 1.E+02 SiO 250 2 2 /(V.s) [Lo et. al, EDL97] 2 1.E+01 18 200 1.3x10 [A/cm 130nm 1.E+00 1.8x1018 OX J 1.E-01 18 150 2.5x10 18 1.E-02 Nitrided SiO2 180nm 3.3x10 1.E-03 Mobility (cm 100 0.51.01.52.02.5 0 0.5 1 1.5 TOX Physical [nm] E EFF [MV/cm] • Gate Oxide Leakage • Universal Mobility Model direct tunneling limited • Ionized impurity scattering T. Ghani et. al. VLSI Symposium 2000 Outline • Traditional‐Scaling ‐ Traditional Scaling Limiters, Device Implications ‐ Intel’s Response • Post “Traditional‐Scaling” Innovations ‐ Mobility Booster: Uniaxial Strain - Poly Depletion Elimination: Metal Gate - Gate Leakage Reduction: HiK • Future Challenges and Options - Power Limitation - Potential New Transistor Structures and Materials Innovations Pioneered by Intel to Overcome “Traditional-Scaling” Limiters • Mobility enhancement through uniaxial strained silicon technology innovation introduced at 90nm node - Epitaxial SiGe S/D - SiN Capping Layers • HiK gate insulator introduced at 45nm CMOS node to reduce gate leakage • Metal Gate introduced at 45nm CMOS node to eliminate poly depletion Uniaxial Strain Silicon Transistors Intel: IEDM 2003 PMOS T. Ghani et. al. IEDM, 2003 NMOS SiN stress layer SiGe SiGe These transistor structures introduced first at Intel’s 90nm CMOS node. These structures have now become industry standard for strain implementation Strained SiGe S/D PMOS Transistor • SiGe film embedded into source/drain • SiGe film deposited by selective epitaxy • Induces large uniaxial compressive strain in SiGe SiGe channel • This strain leads to dramatic hole mobility enhancement How Strain Impacts Mobility? Strain impacts mobility through: • Energy/subband spacing which affects scattering (τ) 1 • Valley repopulation which changes transport mass (meff) 2 • Band warpage which changes transport mass (meff) 3 q τ >< μ = m eff Valence band Compression 1 2 3 (2p/a) y k ΔE channel Tension direction kx (2p/a) M. Stettler, 2006 SINANO Device Modeling School Performance Gains with Uniaxial Strain 2nd Gen PMOS: 65nm 6 Source: Intel Ref: Unstrained Silicon (100)/<110> 5 Channel=Si 2.2x Mobility Idlin PMOS 80 4 45nnm 3 60 Idsat 65nnm 2 90nnm NMOS Enhancement Ratio Enhancement y 40 1 E =1MV/cm 0 EFF Mobilit Drive Gain (%) Drive Drive Gain (%) Drive 20 0 1000 2000 3000 0 Channel Stress (Mpa) Significant headroom left to increase PMOS mobility in future (> 5x) Innovations Pioneered by Intel to Overcome Traditional Scaling Limiters • Mobility enhancement through uniaxial strained silicon technology innovation introduced at 90nm node ‐ Epitaxial SiGe S/D ‐ SiN Capping Layers • HiK gate insulator introduced at 45nm CMOS node to reduce gate leakage • Metal Gate introduced at 45nm CMOS node to eliminate poly depletion Year 2003: INTEL 65nm CMOS Pathfinding Gate Oxide Runs out of steam Gate electrode Gate oxide running out of atoms 1.E+04 Jox limit VLSI Symp. 2000 1.E+03 ] 1.E+02 SiO 2 2 1.1nm SiO2 1.E+01 [Lo et. al, EDL97] [A/cm 1.E+00 130nm OX J 1.E-01 Silicon 1.E-02 Nitrided SiO2 180nm substrate 1.E-03 0.51.01.52.02.5 TOX Physical [nm] Intel 65nm production: 2005 • Gate Oxide Leakage • Gate Oxide only 3-4 atomic layers thick. direct tunneling limited • Gate depletion also a limiter T. Ghani .et. al. VLSI Symp. 2000 High-k + Metal Gate Benefits • High‐k gate dielectric – Reduced gate leakage – TOX(e) scaling • Metal gates – Eliminate polysilicon depletion – Resolves VT pinning and poor mobility for high‐ k dielectrics High-k + Metal Gate Challenges • High‐k gate dielectric – Poor mobility – Poor reliability • Metal gates – Dual band edge work functions – Thermal stability – Integration scheme Transistor Process Flow • Key considerations – Integrate hafnium-based high-k dielectric, dual metal gate electrodes, strained silicon – Thermal stability of metal gate electrodes • High-k First, Metal Gate Last – Metal gate deposition after high temperature anneals – Integrated with strained silicon process 45nm High-k + Metal Gate Transistors 65 nm Transistor 45 nm HK + MG TEM TEM Hafnium-based high-k + metal gate transistors are the biggest advancement in transistor technology since the late 1960s 45 nm High-k + Metal Gate Transistors Benefits compared to 65nm node >25x lower gate oxide leakage >30% lower switching power ~30% higher drive current, or >5x lower source-drain leakage Intel is only company with high-k + metal gate transistors in production, starting in Nov. ‘07 Scaling of Vt Variation 1.1 1 Minimal oxide scale HiK+MG 0.9 0.8 0.7 Tox scaling 0.6 0.5 Normalized to C2 180nm 0.4 180nm 130nm 90nm 65nm 45nm ⎛ 4 4qε3 φ ⎞ T ⎛ 4 N ⎞ 1 ⎛ c ⎞ σV = ⎜ si B⎟⋅ox ⋅⎜ ⎟ = ⎜ 2 ⎟ )1( Tran ⎜ 2 ⎟ ε Leff⎜ ⋅ Zeff⎟ 2Leff⎜ ⋅ Zeff⎟ ⎝ ⎠ ox ⎝ ⎠ ⎝ ⎠ HK+MG reduces random Vt variation Critical to SRAM Vmin Replacement Metal Gate Flow NMOS PMOS Polysilicon Gate (sacrificial) High-k Dielectric (ALD) P+ P+ N+ N+ SiGe SiGe Silicon Substrate Standard transistor process through source-drain formation, but including atomic layer deposition high-k dielectric Replacement Metal Gate Flow NMOS PMOS P+ P+ N+ N+ SiGe SiGe Silicon Substrate Deposit and planarize oxide layer Replacement Metal Gate Flow NMOS PMOS P+ P+ N+ N+ SiGe SiGe Silicon Substrate Etch out sacrificial polysilicon gate Replacement Metal Gate Flow NMOS PMOS P+ P+ N+ N+ SiGe SiGe Silicon Substrate Deposit separate NMOS and PMOS WF metal layers Replacement Metal Gate Flow NMOS PMOS P+ P+ N+ N+ SiGe SiGe Silicon Substrate Deposit Al fill metal, planarize surface RMG PMOS Strain Benefit Before gate removal After gate removal RMG process provides significant additional PMOS performance gain by increasing channel strain 45 nm Microprocessor Products Quad Core Dual Core Single Core 6 Core 8 Core >200 million 45 nm CPUs shipped to date Intel Logic Technology Roadmap 45 nm 32 nm 22 nm Process Name: P1266 P1268 P1270 Products: CPU CPU CPU 1st Production: 2007 2009 2011 Intel 32nm: 2nd generation high-k + metal gate transistors Transistor Density 1000 Pitch Gate Pitch (nm) 0.7x every 65nm 2 years 45nm 32nm 112.5 nm 100 1995 2000 2005 2010 Intel 32 nm transistors provide the tightest gate pitch of any reported 32 nm or 28 nm technology Transistor Performance 2.0 1.0 V, 100 nA IOFF 32nm 1.5 45nm 65nm Drive 90nm Current 1.0 (mA/um) 130nm NMOS 0.5 PMOS 0.0 1000 100 Gate Pitch (nm) Intel 32 nm transistors provide the highest drive currents of any reported 32 nm or 28 nm technology SRAM Cell Size Scaling 10 ) 2 65 nm, 0.570 um2 1 0.5x every Cell Area (um (um Area Cell 2 years 45 nm, 0.346 um2 0.1 1995 2000 2005 2010 32 nm, 0.171 um2 Transistor density continues to double every 2 years 32 nm Defect Density Trend 90 nm 65 nm 45 nm 32 nm Defect Higher Density Yield (log scale) <2 year 2002 2003 2004 2005 2006 2007 2008 2009 2010 Intel’s 32 nm process is certified and CPU wafers are moving through the factory in support of planned Q4 revenue production Outline • Traditional‐Scaling ‐ Traditional Scaling Limiters, Device Implications ‐ Intel’s Response • Post “Traditional‐Scaling” Innovations ‐ Mobility Booster: Uniaxial Strain - Poly Depletion Elimination: Metal Gate - Gate Leakage Reduction: HiK • Future Challenges and Options - Power Limitation - Potential New Transistor Structures and Materials CPU Transistor Count & Power Trend 1.E+10 1.E+10 1000 Itanium® 2 CPU 1.E+09 1.E+09 CPU Power (W) Pentium® 4 CPU 1.E+08 Penryn1.E+08 QC 1.E+07 Pentium® II CPU 1.E+07 100 TM 1.E+06 486 1.E+06 286 1.E+05 2x increase 1.E+05 every 1.E+04 8080 1.E+04 2 years 4004 10 1.E+03 1.E+03 1970 1980 1990 2000 2010 1990 1995 2000 2005 2010 2015 Power Dissipation Limited to ~100W BUT increased transistor count needed in Multi-Core CPU Era !!! Multi‐Core CPU Power Limited Era P = Switching Power + Leakage Power + .. FixedFixed PowerPower CC 1x1xCC 2 ~ (fCgateVCC α) * N Relative V Relative V Constant 1x 1.5x 2x Relative Transistor Count • VCC scaling required for continued increase in transistor count in power limited world Future Transistors will need to continue to achieve Higher Performance while Scaling Power Supply Voltage Possible Future Transistor Options • Advanced Channel Materials - III-V and Ge channel materials • Multi-Gate Fin Transistors - Non planar architecture • Tunnel Transistors - New transport mechanism Each transistor structure has many significant challenges which will have to be successfully addressed if it is to become a serious contender to silicon MOSFET Ultimate Channel Materials: Ballistic Transport Ultimate Ballistic Regime: 1 υ ~ inj m* IDSAT ~ Qinv*υinj t Eco 1.
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    JOURNAL OFNANO- AND ELECTRONICPHYSICS ЖУРНАЛ НАНО- ТА ЕЛЕКТРОННОЇ ФІЗИКИ Vol. 4 No 1, 01003(6pp) (2012) Том 4 № 1, 01003(6cc) (2012) Prospects for the Application of Nanotechnologies to the Computer System Architecture J. Partyka1, M. Mazur2,* 1 Faculty of Electrical Engineering and Information Science, Lublin University of Technology 38а, ul. Nadbystrzycka 2 Wyższa Szkoła Ekonomii i Innowacji w Lublinie ul. Mełgiewska 7-9 (Received 26 September 2011; published online 14 March 2012) Computer system architecture essentially influences the comfort of our everyday living. Developmental transition from electromechanical relays to vacuum tubes, from transistors to integrated circuits has sig- nificantly changed technological standards for the architecture of computer systems. Contemporary infor- mation technologies offer huge potential concerning miniaturization of electronic circuits. Presently, a modern integrated circuit includes over a billion of transistors, each of them smaller than 100 nm . Step- ping beyond the symbolic 100 nm limit means that with the onset of the 21 century we have entered a new scientific area that is an era of nanotechnologies. Along with the reduction of transistor dimensions their operation speed and efficiency grow. However, the hitherto observed developmental path of classical elec- tronics with its focus on the miniaturization of transistors and memory cells seems arriving at the limits of technological possibilities because of technical problems as well as physical limitations related to the ap- pearance of