DOCSLIB.ORG

Challenges and Innovations in Nano‐CMOS Transistor Scaling

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Challenges and Innovations in Nano‐CMOS Transistor Scaling Challenges and Innovations in Nano‐CMOS Transistor Scaling Tahir Ghani Intel Fellow Logic Technology Development October, 2009 Nikkei Presentation 1 Outline • Traditional‐Scaling ‐ Traditional Scaling Limiters, Device Implications ‐ Intel’s Response • Post “Traditional‐Scaling” Innovations ‐ Mobility Booster: Uniaxial Strain - Poly Depletion Elimination: Metal Gate - Gate Leakage Reduction: HiK • Future Challenges and Options - Power Limitation - Potential New Transistor Structures and Materials 40+ Years of Moore’s Law at INTEL: From Few to Billions of Transistors 2X transistors every 2 years Transistor Count has Doubled Every Two Years 40+ Years of Moore’s Law at INTEL: From Few to Billions of Transistors 2X transistors every 2 years Traditional Scaling Era END OF TRADITIONAL SCALING ERA ~ 2003 Lasted ~40 YEARS Top “Traditional-Scaling” Enablers R. Dennard et.al. IEEE JSSC, 1974 • Gate Oxide Thickness Scaling - Key enabler for Lgate scaling • Junction Scaling - Another enabler for Lgate scaling - Improved abruptness (REXT reduction) • Vcc Scaling - Reduce XDEP (improve SCE) - However, did not follow const E field 1990’s: Golden Era of Scaling Vcc, Tox & Lg scaling & increasing Idsat Year 2000: INTEL 90nm CMOS Pathfinding End of “Traditional-Scaling” Era Gate oxide running Mobility degrades out of atoms with scaling 1.E+04 Jox limit VLSI Symp. 2000 300 Universal 1.E+03 NA= Mobility 3x1017 ] 1.E+02 SiO 250 2 2 /(V.s) [Lo et. al, EDL97] 2 1.E+01 18 200 1.3x10 [A/cm 130nm 1.E+00 1.8x1018 OX J 1.E-01 18 150 2.5x10 18 1.E-02 Nitrided SiO2 180nm 3.3x10 1.E-03 Mobility (cm 100 0.51.01.52.02.5 0 0.5 1 1.5 TOX Physical [nm] E EFF [MV/cm] • Gate Oxide Leakage • Universal Mobility Model direct tunneling limited • Ionized impurity scattering T. Ghani et. al. VLSI Symposium 2000 Outline • Traditional‐Scaling ‐ Traditional Scaling Limiters, Device Implications ‐ Intel’s Response • Post “Traditional‐Scaling” Innovations ‐ Mobility Booster: Uniaxial Strain - Poly Depletion Elimination: Metal Gate - Gate Leakage Reduction: HiK • Future Challenges and Options - Power Limitation - Potential New Transistor Structures and Materials Innovations Pioneered by Intel to Overcome “Traditional-Scaling” Limiters • Mobility enhancement through uniaxial strained silicon technology innovation introduced at 90nm node - Epitaxial SiGe S/D - SiN Capping Layers • HiK gate insulator introduced at 45nm CMOS node to reduce gate leakage • Metal Gate introduced at 45nm CMOS node to eliminate poly depletion Uniaxial Strain Silicon Transistors Intel: IEDM 2003 PMOS T. Ghani et. al. IEDM, 2003 NMOS SiN stress layer SiGe SiGe These transistor structures introduced first at Intel’s 90nm CMOS node. These structures have now become industry standard for strain implementation Strained SiGe S/D PMOS Transistor • SiGe film embedded into source/drain • SiGe film deposited by selective epitaxy • Induces large uniaxial compressive strain in SiGe SiGe channel • This strain leads to dramatic hole mobility enhancement How Strain Impacts Mobility? Strain impacts mobility through: • Energy/subband spacing which affects scattering (τ) 1 • Valley repopulation which changes transport mass (meff) 2 • Band warpage which changes transport mass (meff) 3 q τ >< μ = m eff Valence band Compression 1 2 3 (2p/a) y k ΔE channel Tension direction kx (2p/a) M. Stettler, 2006 SINANO Device Modeling School Performance Gains with Uniaxial Strain 2nd Gen PMOS: 65nm 6 Source: Intel Ref: Unstrained Silicon (100)/<110> 5 Channel=Si 2.2x Mobility Idlin PMOS 80 4 45nnm 3 60 Idsat 65nnm 2 90nnm NMOS Enhancement Ratio Enhancement y 40 1 E =1MV/cm 0 EFF Mobilit Drive Gain (%) Drive Drive Gain (%) Drive 20 0 1000 2000 3000 0 Channel Stress (Mpa) Significant headroom left to increase PMOS mobility in future (> 5x) Innovations Pioneered by Intel to Overcome Traditional Scaling Limiters • Mobility enhancement through uniaxial strained silicon technology innovation introduced at 90nm node ‐ Epitaxial SiGe S/D ‐ SiN Capping Layers • HiK gate insulator introduced at 45nm CMOS node to reduce gate leakage • Metal Gate introduced at 45nm CMOS node to eliminate poly depletion Year 2003: INTEL 65nm CMOS Pathfinding Gate Oxide Runs out of steam Gate electrode Gate oxide running out of atoms 1.E+04 Jox limit VLSI Symp. 2000 1.E+03 ] 1.E+02 SiO 2 2 1.1nm SiO2 1.E+01 [Lo et. al, EDL97] [A/cm 1.E+00 130nm OX J 1.E-01 Silicon 1.E-02 Nitrided SiO2 180nm substrate 1.E-03 0.51.01.52.02.5 TOX Physical [nm] Intel 65nm production: 2005 • Gate Oxide Leakage • Gate Oxide only 3-4 atomic layers thick. direct tunneling limited • Gate depletion also a limiter T. Ghani .et. al. VLSI Symp. 2000 High-k + Metal Gate Benefits • High‐k gate dielectric – Reduced gate leakage – TOX(e) scaling • Metal gates – Eliminate polysilicon depletion – Resolves VT pinning and poor mobility for high‐ k dielectrics High-k + Metal Gate Challenges • High‐k gate dielectric – Poor mobility – Poor reliability • Metal gates – Dual band edge work functions – Thermal stability – Integration scheme Transistor Process Flow • Key considerations – Integrate hafnium-based high-k dielectric, dual metal gate electrodes, strained silicon – Thermal stability of metal gate electrodes • High-k First, Metal Gate Last – Metal gate deposition after high temperature anneals – Integrated with strained silicon process 45nm High-k + Metal Gate Transistors 65 nm Transistor 45 nm HK + MG TEM TEM Hafnium-based high-k + metal gate transistors are the biggest advancement in transistor technology since the late 1960s 45 nm High-k + Metal Gate Transistors Benefits compared to 65nm node >25x lower gate oxide leakage >30% lower switching power ~30% higher drive current, or >5x lower source-drain leakage Intel is only company with high-k + metal gate transistors in production, starting in Nov. ‘07 Scaling of Vt Variation 1.1 1 Minimal oxide scale HiK+MG 0.9 0.8 0.7 Tox scaling 0.6 0.5 Normalized to C2 180nm 0.4 180nm 130nm 90nm 65nm 45nm ⎛ 4 4qε3 φ ⎞ T ⎛ 4 N ⎞ 1 ⎛ c ⎞ σV = ⎜ si B⎟⋅ox ⋅⎜ ⎟ = ⎜ 2 ⎟ )1( Tran ⎜ 2 ⎟ ε Leff⎜ ⋅ Zeff⎟ 2Leff⎜ ⋅ Zeff⎟ ⎝ ⎠ ox ⎝ ⎠ ⎝ ⎠ HK+MG reduces random Vt variation Critical to SRAM Vmin Replacement Metal Gate Flow NMOS PMOS Polysilicon Gate (sacrificial) High-k Dielectric (ALD) P+ P+ N+ N+ SiGe SiGe Silicon Substrate Standard transistor process through source-drain formation, but including atomic layer deposition high-k dielectric Replacement Metal Gate Flow NMOS PMOS P+ P+ N+ N+ SiGe SiGe Silicon Substrate Deposit and planarize oxide layer Replacement Metal Gate Flow NMOS PMOS P+ P+ N+ N+ SiGe SiGe Silicon Substrate Etch out sacrificial polysilicon gate Replacement Metal Gate Flow NMOS PMOS P+ P+ N+ N+ SiGe SiGe Silicon Substrate Deposit separate NMOS and PMOS WF metal layers Replacement Metal Gate Flow NMOS PMOS P+ P+ N+ N+ SiGe SiGe Silicon Substrate Deposit Al fill metal, planarize surface RMG PMOS Strain Benefit Before gate removal After gate removal RMG process provides significant additional PMOS performance gain by increasing channel strain 45 nm Microprocessor Products Quad Core Dual Core Single Core 6 Core 8 Core >200 million 45 nm CPUs shipped to date Intel Logic Technology Roadmap 45 nm 32 nm 22 nm Process Name: P1266 P1268 P1270 Products: CPU CPU CPU 1st Production: 2007 2009 2011 Intel 32nm: 2nd generation high-k + metal gate transistors Transistor Density 1000 Pitch Gate Pitch (nm) 0.7x every 65nm 2 years 45nm 32nm 112.5 nm 100 1995 2000 2005 2010 Intel 32 nm transistors provide the tightest gate pitch of any reported 32 nm or 28 nm technology Transistor Performance 2.0 1.0 V, 100 nA IOFF 32nm 1.5 45nm 65nm Drive 90nm Current 1.0 (mA/um) 130nm NMOS 0.5 PMOS 0.0 1000 100 Gate Pitch (nm) Intel 32 nm transistors provide the highest drive currents of any reported 32 nm or 28 nm technology SRAM Cell Size Scaling 10 ) 2 65 nm, 0.570 um2 1 0.5x every Cell Area (um (um Area Cell 2 years 45 nm, 0.346 um2 0.1 1995 2000 2005 2010 32 nm, 0.171 um2 Transistor density continues to double every 2 years 32 nm Defect Density Trend 90 nm 65 nm 45 nm 32 nm Defect Higher Density Yield (log scale) <2 year 2002 2003 2004 2005 2006 2007 2008 2009 2010 Intel’s 32 nm process is certified and CPU wafers are moving through the factory in support of planned Q4 revenue production Outline • Traditional‐Scaling ‐ Traditional Scaling Limiters, Device Implications ‐ Intel’s Response • Post “Traditional‐Scaling” Innovations ‐ Mobility Booster: Uniaxial Strain - Poly Depletion Elimination: Metal Gate - Gate Leakage Reduction: HiK • Future Challenges and Options - Power Limitation - Potential New Transistor Structures and Materials CPU Transistor Count & Power Trend 1.E+10 1.E+10 1000 Itanium® 2 CPU 1.E+09 1.E+09 CPU Power (W) Pentium® 4 CPU 1.E+08 Penryn1.E+08 QC 1.E+07 Pentium® II CPU 1.E+07 100 TM 1.E+06 486 1.E+06 286 1.E+05 2x increase 1.E+05 every 1.E+04 8080 1.E+04 2 years 4004 10 1.E+03 1.E+03 1970 1980 1990 2000 2010 1990 1995 2000 2005 2010 2015 Power Dissipation Limited to ~100W BUT increased transistor count needed in Multi-Core CPU Era !!! Multi‐Core CPU Power Limited Era P = Switching Power + Leakage Power + .. FixedFixed PowerPower CC 1x1xCC 2 ~ (fCgateVCC α) * N Relative V Relative V Constant 1x 1.5x 2x Relative Transistor Count • VCC scaling required for continued increase in transistor count in power limited world Future Transistors will need to continue to achieve Higher Performance while Scaling Power Supply Voltage Possible Future Transistor Options • Advanced Channel Materials - III-V and Ge channel materials • Multi-Gate Fin Transistors - Non planar architecture • Tunnel Transistors - New transport mechanism Each transistor structure has many significant challenges which will have to be successfully addressed if it is to become a serious contender to silicon MOSFET Ultimate Channel Materials: Ballistic Transport Ultimate Ballistic Regime: 1 υ ~ inj m* IDSAT ~ Qinv*υinj t Eco 1.
Load more

Recommended publications
  • Strained Silicon Devices M. Reiche , O. Moutanabbir , J. Hoentschel , U
    Solid State Phenomena Vols. 156-158 (2010) pp 61-68 Online available since 2009/Oct/28 at www.scientific.net © (2010) Trans Tech Publications, Switzerland doi:10.4028/www.scientific.net/SSP.156-158.61 Strained Silicon Devices M. Reiche 1a , O. Moutanabbir 1b, J. Hoentschel 2c , U. Gösele 1d, S. Flachowsky 2e and M. Horstmann 2f 1 Max Planck Institute of Microstructure Physics, Weinberg 2, D – 06120 Halle, Germany 2 GLOBALFOUNDRIES Fab 1, Wilschdorfer Landstraße 101, D – 01109 Dresden, Germany a [email protected], b [email protected], c [email protected], d [email protected], e stefan.flachowsky@ globalfoundries.com, f [email protected] Keywords: strained silicon, mobility enhancement, process-induced strain, global strain, SSOI. Abstract. Strained silicon channels are one of the most important Technology Boosters for further Si CMOS developments. The mobility enhancement obtained by applying appropriate strain provides higher carrier velocity in MOS channels, resulting in higher current drive under a fixed supply voltage and gate oxide thickness. The physical mechanism of mobility enhancement, methods of strain generation and their application for advanced VLSI devices is reviewed. Introduction The ordinary device scaling was the most important principle of performance enhancement in Si CMOS for more than 30 years. However, starting with 90 nm technologies the performance enhancements of CMOS started to diminish through standard device scaling such as shrinking the gate length and thinning the gate oxide due to several physical limitations in miniaturization of MOSFETs. For example, thinning the gate oxide requires a reduction of the supply voltage and an increase of the gate tunneling current occurs.
    [Show full text]
  • China's Progress in Semiconductor Manufacturing Equipment
    MARCH 2021 China’s Progress in Semiconductor Manufacturing Equipment Accelerants and Policy Implications CSET Policy Brief AUTHORS Will Hunt Saif M. Khan Dahlia Peterson Executive Summary China has a chip problem. It depends entirely on the United States and U.S. allies for access to advanced commercial semiconductors, which underpin all modern technologies, from smartphones to fighter jets to artificial intelligence. China’s current chip dependence allows the United States and its allies to control the export of advanced chips to Chinese state and private actors whose activities threaten human rights and international security. Chip dependence is also expensive: China currently depends on imports for most of the chips it consumes. China has therefore prioritized indigenizing advanced semiconductor manufacturing equipment (SME), which chip factories require to make leading-edge chips. But indigenizing advanced SME will be hard since Chinese firms have serious weaknesses in almost all SME sub-sectors, especially photolithography, metrology, and inspection. Meanwhile, the top global SME firms—based in the United States, Japan, and the Netherlands—enjoy wide moats of intellectual property and world- class teams of engineers, making it exceptionally difficult for newcomers to the SME industry to catch up to the leading edge. But for a country with China’s resources and political will, catching up in SME is not impossible. Whether China manages to close this gap will depend on its access to five technological accelerants: 1. Equipment components. Building advanced SME often requires access to a range of complex components, which SME firms often buy from third party suppliers and then assemble into finished SME.
    [Show full text]
  • Technology Roadmap for 22Nm CMOS and Beyond
    Technology Roadmap for 22nm CMOS and beyond June 1, 2009 IEDST 2009@IIT-Bombay Hiroshi Iwai Tokyo Institute of Technology 1 Outline 1. Scaling 2. ITRS Roadmap 3. Voltage Scaling/ Low Power and Leakage 4. SRAM Cell Scaling 5.Roadmap for further future as a personal view 2 1. Scaling 3 Scaling Method: by R. Dennard in 1974 1 Wdep: Space Charge Region (or Depletion Region) Width 1 1 SDWdep has to be suppressed 1 Otherwise, large leakage Wdep between S and D I Leakage current Potential in space charge region is high, and thus, electrons in source are 0 attracted to the space charge region. 0 V 1 K=0.7 X , Y, Z :K, V :K, Na : 1/K for By the scaling, Wdep is suppressed in proportion, example and thus, leakage can be suppressed. K Good scaled I-V characteristics K K Wdep V/Na K Wdep I I : K : K 0 0K V 4 Downscaling merit: Beautiful! Geometry & L , W g g K Scaling K : K=0.7 for example Supply voltage Tox, Vdd Id = vsatWgCo (Vg‐Vth) Co: gate C per unit area Drive current I d K –1 ‐1 ‐1 in saturation Wg (tox )(Vg‐Vth)= Wgtox (Vg‐Vth)= KK K=K Id per unit Wg Id/µm 1 Id per unit Wg = Id / Wg= 1 Gate capacitance Cg K Cg = εoεoxLgWg/tox KK/K = K Switching speed τ K τ= CgVdd/Id KK/K= K Clock frequency f 1/K f = 1/τ = 1/K Chip area Achip α α: Scaling factor In the past, α>1 for most cases Integration (# of Tr) N α/K2 N α/K2 = 1/K2 , when α=1 Power per chip P α fNCV2/2 K‐1(αK‐2)K (K1 )2= α = 1, when α=1 5 k= 0.7 and α =1 k= 0.72 =0.5 and α =1 Single MOFET Vdd 0.7 Vdd 0.5 Lg 0.7 Lg 0.5 Id 0.7 Id 0.5 Cg 0.7 Cg 0.5 P (Power)/Clock P (Power)/Clock 0.73 = 0.34 0.53 = 0.125 τ (Switching time) 0.7 τ (Switching time) 0.5 Chip N (# of Tr) 1/0.72 = 2 N (# of Tr) 1/0.52 = 4 f (Clock) 1/0.7 = 1.4 f (Clock) 1/0.5 = 2 P (Power) 1 P (Power) 1 6 - The concerns for limits of down-scaling have been announced for every generation.
    [Show full text]
  • Moore's Law: the Future of Si Microelectronics
    Moore’s law: the future of Si microelectronics Soon after Bardeen, Brattain, and Shockley invented a solid-state device in 19471 to replace electron vacuum tubes, the microelectronics industry and a revolution started. Since its birth, the industry has experienced four decades of unprecedented explosive growth driven by two factors: Noyce and Kilby inventing the planar integrated circuit2,3 and the advantageous characteristics that result from scaling (shrinking) solid-state devices. Scott E. Thompson and Srivatsan Parthasarathy SWAMP Center, Department of Electrical and Computer Engineering, University of Florida, Gainsville, FL 32611-6130 USA E-mail:[email protected], [email protected] Scaling solid-state devices has the peculiar property of improving approaches under investigation are: (1) nonclassical CMOS, which cost, performance, and power, which has historically given any consists of new channel materials and/or multigate fully depleted company with the latest technology a large competitive device structures; and (2) alternatives to CMOS, such as spintronics, advantage in the market. As a result, the microelectronics single electron devices, and molecular computing8,9. While some of industry has driven transistor feature size scaling from 10 µm to these non-Si research areas are important and will be successful in ~30 nm4-6 during the past 40 years. During most of this time, new applications and markets10, it seems unlikely any of the non-Si scaling simply consisted of reducing the feature size. However, options can replace the Si transistor for the $300 billion during certain periods, there were major changes as with the microelectronics industry in the foreseeable future (perhaps as long industry move from Si bipolar to p-channel metal-oxide- as 30 years).
    [Show full text]
  • Multiprocessing Contents
    Multiprocessing Contents 1 Multiprocessing 1 1.1 Pre-history .............................................. 1 1.2 Key topics ............................................... 1 1.2.1 Processor symmetry ...................................... 1 1.2.2 Instruction and data streams ................................. 1 1.2.3 Processor coupling ...................................... 2 1.2.4 Multiprocessor Communication Architecture ......................... 2 1.3 Flynn’s taxonomy ........................................... 2 1.3.1 SISD multiprocessing ..................................... 2 1.3.2 SIMD multiprocessing .................................... 2 1.3.3 MISD multiprocessing .................................... 3 1.3.4 MIMD multiprocessing .................................... 3 1.4 See also ................................................ 3 1.5 References ............................................... 3 2 Computer multitasking 5 2.1 Multiprogramming .......................................... 5 2.2 Cooperative multitasking ....................................... 6 2.3 Preemptive multitasking ....................................... 6 2.4 Real time ............................................... 7 2.5 Multithreading ............................................ 7 2.6 Memory protection .......................................... 7 2.7 Memory swapping .......................................... 7 2.8 Programming ............................................. 7 2.9 See also ................................................ 8 2.10 References .............................................
    [Show full text]
  • Strained Silicon Layer in CMOS Technology
    ELECTRONICS, VOL. 18, NO. 2, DECEMBER 2014 63 Strained Silicon Layer in CMOS Technology Tatjana Pešić-Brđanin, Branko L. Dokić However, the other demands of designing integrated circuits Abstract— Semiconductor industry is currently facing with the with ultra large scale of integration, such as, for example, the fact that conventional submicron CMOS technology is increase in density on the chip and reducing the size of the approaching the end of their capabilities, at least when it comes to chip, have led to the scaling of other transistor dimensions. scaling the dimensions of the components. Therefore, much attention is paid to device technology that use new technological Fig. 1 shows the trend of reducing the gate length that has led structures and new channel materials. Modern technological to the emergence of new technologies [1]. Reducing the gate processes, which mainly include ultra high vacuum chemical length caused a simultaneous scaling of other technological vapor deposition, molecular beam epitaxy and metal-organic parameters, in order to meet the required performances of molecular vapor deposition, enable the obtaining of ultrathin, integrated circuits regarding high speed and low power crystallographically almost perfect, strained layers of high purity. consumption, or the desired degree of integration. However, In this review paper we analyze the role that such layers have in modern CMOS technologies. It’s given an overview of the with recent CMOS technologies, in which the gate length is characteristics of both strain techniques, global and local, with less than 90 nm, this performance improvement becomes more special emphasis on performance of NMOS biaxial strain and difficult due to physical limitations in miniaturization of MOS PMOS uniaxial strain.
    [Show full text]
  • Optimization of Monte Carlo Neutron Transport Simulations with Emerging Architectures Yunsong Wang
    Optimization of Monte Carlo Neutron Transport Simulations with Emerging Architectures Yunsong Wang To cite this version: Yunsong Wang. Optimization of Monte Carlo Neutron Transport Simulations with Emerging Archi- tectures. Distributed, Parallel, and Cluster Computing [cs.DC]. Université Paris Saclay (COmUE), 2017. English. NNT : 2017SACLX090. tel-01687913 HAL Id: tel-01687913 https://pastel.archives-ouvertes.fr/tel-01687913 Submitted on 18 Jan 2018 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. NNT : 2017SACLX090 THESE` DE DOCTORAT DE L’UNIVERSITE´ PARIS-SACLAY PREPAR´ E´ A` L’ECOLE´ POLYTECHNIQUE ECOLE´ DOCTORALE No 573 INTERFACES : APPROCHES INTERDISCIPLINAIRES / FONDEMENTS, APPLICATIONS ET INNOVATION Sp´ecialit´ede doctorat: Informatique par M. Yunsong Wang Optimization of Monte Carlo Neutron Transport Simulations by Using Emerging Architectures Th`ese pr´esent´ee et soutenue `a Gif-sur-Yvette, le 14 d´ecembre 2017 : Composition de jury : M. Marc Verderi Directeur de Recherche, CNRS/IN2P3/LLR Pr´esident du jury M. Andrew Siegel Expert Senior, Argonne National Laboratory Rapporteur M. Raymond Namyst Professeur, Universit´ede Bordeaux/LABRI Rapporteur M. David Chamont Charg´ede Recherche, CNRS/IN2P3/LAL Examinateur M. David Riz Ing´enieur,CEA/DAM Examinateur M.
    [Show full text]
  • Design and Analysis of a New Carbon Nanotube Full Adder Cell
    Hindawi Publishing Corporation Journal of Nanomaterials Volume 2011, Article ID 906237, 6 pages doi:10.1155/2011/906237 Research Article Design and Analysis of a New Carbon Nanotube Full Adder Cell M. H. Ghadiry,1 Asrulnizam Abd Manaf,1 M. T. Ahmadi,2 Hatef Sadeghi,2 and M. Nadi Senejani3 1 School of Electrical and Electronic Engineering, Universiti Sains Malaysia, Engineering Campus, 11800 Penang, Malaysia 2 Faculty of Electrical Engineering, Universiti Teknologi Malaysia, 81310 Skudai, Malaysia 3 Department of Computer Engineering, Islamic Azad University, Ashtian Branch, 39618-13347 Ashtian, Iran Correspondence should be addressed to M. H. Ghadiry, [email protected] Received 10 January 2011; Accepted 27 February 2011 Academic Editor: Theodorian Borca-Tasciuc Copyright © 2011 M. H. Ghadiry et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. A novel full adder circuit is presented. The main aim is to reduce power delay product (PDP) in the presented full adder cell. A new method is used in order to design a full-swing full adder cell with low number of transistors. The proposed full adder is implemented in MOSFET-like carbon nanotube technology and the layout is provided based on standard 32 nm technology from MOSIS. The simulation results using HSPICE show that there are substantial improvements in both power and performance of the proposed circuit compared to the latest designs. In addition, the proposed circuit has been implemented in conventional 32 nm process to compare the benefits of using MOSFET-like carbon nanotubes in arithmetic circuits over conventional CMOS technology.
    [Show full text]
  • Electron Effective Mobility in Strained Si/Si1-Xgex MOS Devices Using Monte Carlo Simulation
    Electron effective mobility in strained Si/Si1-xGex MOS devices using Monte Carlo simulation V. Aubry-Fortuna, P. Dollfus, S. Galdin-Retailleau Institut d'Electronique Fondamentale, CNRS UMR 8622, Bât. 220, Université Paris-Sud, 91405 Orsay cedex, France. E-mail : [email protected] Abstract Based on Monte Carlo simulation, we report the study of the inversion layer mobility in n-channel strained Si/ Si1-xGex MOS structures. The influence of the strain in the Si layer and of the doping level is studied. Universal mobility curves µeff as a function of the effective vertical field Eeff are obtained for various state of strain, as well as a fall-off of the mobility in weak inversion regime, which reproduces correctly the experimental trends. We also observe a mobility enhancement up to 120 % for strained Si/ Si0.70Ge0.30, in accordance with best experimental data. The effect of the strained Si channel thickness is also investigated: when decreasing the thickness, a mobility degradation is observed under low effective field only. The role of the different scattering mechanisms involved in the strained Si/ Si1-xGex MOS structures is explained. In addition, comparison with experimental results is discussed in terms of SiO2/ Si interface roughness, as well as surface roughness of the SiGe substrate on which strained Si is grown. Keywords strained Si, effective mobility, Monte Carlo simulation, MOSFET PACS codes 72.20.Dp, 72.20.Fr, 85.30.Tv -1- 1. Introduction The use of strained-Si channel pseudomorphically grown on a SiGe virtual substrate is becoming a promising way to accelerate the improvement of CMOS performance.
    [Show full text]
  • Sige CVD, Fundamentals and Device Applications
    SiGeSiGe CVD,CVD, fundamentalsfundamentals andand devicedevice applicationsapplications DrDr DerekDerek HoughtonHoughton AixtronAixtron IncInc ICPS,ICPS, FlagstaffFlagstaff JulyJuly 20042004 . OVERVIEW 1.1. Introduction Introduction 2.2. SiGe SiGe Market Market SurveySurvey 3.3. Fundamentals Fundamentals ofof SiGeSiGe CVDCVD 4.4. CVD CVD EquipmentEquipment forfor SiGeSiGe 5.5. Device Device aplicationsaplications andand commercializationcommercialization 6.6. SiGe SiGe materialsmaterials engineering,engineering, metrologymetrology 7.7. Summary Summary and and DiscussionDiscussion SiGe’s Market Opportunity... Si CMOS/BJTs SiGe HBTs/CMOS? III-V FETs/HBTs Automotive Road Collision Pricing Avoidance Navigation/Areospace GPS x-band Radar Communications GSM DCS ISM DECT FRA WLAN DTH WLAN OC-48 DBS FRA G-Ethernet OC-192 LMDS 0.1 0.2 0.5 1 2 5 10 20 50 100 Frequency (GHz) SiGe HBT device structure and process description KeyKey figures figures of of SiGe SiGe HBT HBT process process •• SiGe SiGe BiCMOSBiCMOS uses uses SiGeSiGe HBT HBT ++ SiSi CMOSCMOS •• SiGe SiGe HBT HBT showsshows samesame processprocess asas SiSi BT BT withwith exceptionexception ofof 30-8030-80 nmnm thinthin SiGeSiGe base base layerlayer (Ge(Ge <25%) <25%) •• Growth Growth ratesrates usedused areare aboutabout 3030 nm/minnm/min (~(~ 22 minmin forfor basebase layer)layer) •• Typically, Typically, samesame LPCVDLPCVD growthgrowth chamberschambers cancan depositedeposite both both SiSi and and SiGeSiGe layers layers Only difference: Base SiGe replaces Silicon •• Depending Depending
    [Show full text]
  • Elastic Strain Engineering in Silicon and Silicon-Germanium Nanomembranes
    Elastic Strain Engineering in Silicon and Silicon-Germanium Nanomembranes By Deborah Marie Paskiewicz A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy (Materials Science) at the UNIVERSITY OF WISCONSIN-MADISON 2012 Date of final oral examination: 11/14/12 The dissertation is approved by the following members of the Final Oral Committee: Max G. Lagally, Professor, Materials Science and Engineering Mark A. Eriksson, Professor, Physics Thomas F. Kuech, Professor, Chemical and Biological Engineering Paul G. Evans, Associate Professor, Materials Science and Engineering Irena Knezevic, Associate Professor, Electrical and Computer Engineering ©Copyright by Deborah Marie Paskiewicz 2012 All Rights Reserved i Abstract Elastic Strain Engineering in Silicon and Silicon-Germanium Nanomembranes Deborah M. Paskiewicz Under the supervision of Professor Max G. Lagally At the University of Wisconsin-Madison Strain in crystalline materials alters the atomic symmetry, thereby changing materials properties. Controlling the strain (its magnitude, direction, extent, periodicity, symmetry, and nature) allows tunability of these new properties. Elastic strain engineering in crystalline nanomembranes (NMs) provides ways to induce and relax strain in thin sheets of single- crystalline materials without exposing the material to the formation of extended defects. I use strain engineering in NMs in two ways: (1) elastic strain sharing between multiple layers using the crystalline symmetry of the layers to induce unique strain distributions, and (2) complete elastic relaxation of single-crystalline alloy NMs. In both cases, NM strain engineering methods enable the introduction of unique strain profiles or strain relaxation in ways not compatible with conventional bulk processing, where strain destroys the long-range crystallinity.
    [Show full text]
  • Prospects for the Application of Nanotechnologies to the Computer System Architecture
    JOURNAL OFNANO- AND ELECTRONICPHYSICS ЖУРНАЛ НАНО- ТА ЕЛЕКТРОННОЇ ФІЗИКИ Vol. 4 No 1, 01003(6pp) (2012) Том 4 № 1, 01003(6cc) (2012) Prospects for the Application of Nanotechnologies to the Computer System Architecture J. Partyka1, M. Mazur2,* 1 Faculty of Electrical Engineering and Information Science, Lublin University of Technology 38а, ul. Nadbystrzycka 2 Wyższa Szkoła Ekonomii i Innowacji w Lublinie ul. Mełgiewska 7-9 (Received 26 September 2011; published online 14 March 2012) Computer system architecture essentially influences the comfort of our everyday living. Developmental transition from electromechanical relays to vacuum tubes, from transistors to integrated circuits has sig- nificantly changed technological standards for the architecture of computer systems. Contemporary infor- mation technologies offer huge potential concerning miniaturization of electronic circuits. Presently, a modern integrated circuit includes over a billion of transistors, each of them smaller than 100 nm . Step- ping beyond the symbolic 100 nm limit means that with the onset of the 21 century we have entered a new scientific area that is an era of nanotechnologies. Along with the reduction of transistor dimensions their operation speed and efficiency grow. However, the hitherto observed developmental path of classical elec- tronics with its focus on the miniaturization of transistors and memory cells seems arriving at the limits of technological possibilities because of technical problems as well as physical limitations related to the ap- pearance of
    [Show full text]