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Roadmap for 22Nm Logic CMOS and Beyond

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Roadmap for 22Nm Logic CMOS and Beyond Roadmap for 22nm Logic CMOS and Beyond March 9, 2009 @Heritage Institute of Technology Hiroshi Iwai, Tokyo Institute of Technology 1 • There were many inventions in the 20th century: Airplane, Nuclear Power generation, Computer, Space aircraft, etc • However, everything has to be controlled by electronics • Electronics Most important invention in the 20th century • What is Electronics: To use electrons, Electronic Circuits Electronic Circuits started by the invention of vacuum tube (Triode) in 1906 Thermal electrons from cathode controlled by grid bias Lee De Forest Cathode Anode (heated) Grid (Positive bias) Same mechanism as that of transistor 4 wives of Lee De Forest 1906 Lucille Sheardown 1907 Nora Blatch 1912 Mary Mayo, singer 1930 Marie Mosquini, silent film actress Mary Marie 4 First Computer Eniac: made of huge number of vacuum tubes 1946 Big size, huge power, short life time filament Æ dreamed of replacing vacuum tube with solid‐state device Today's pocket PC made of semiconductor has much higher performance with extremely low power consumption 5 History of Semiconductor devices 1947, 1st Point Contact Bipolar Transistor: Ge Semiconductor, Bardeen, Brattin Æ Nobel Prize 1948, 1st Junction Bipolar Transistor, Ge Semiconductor, Schokley Æ Nobel Prize 1958, 1st Integrated Circuits, Ge Semiconductor, J.Kilby Æ Nobel Prize 1959, 1st Planar Integrated Circuits, R.Noice 1960, 1st MOS Transistor, Kahng, Si Semiconductor 1963, 1st CMOS Circuits, C.T. Sah and F. Wanlass 6 J. E. LILIENFELD DEVICES FOR CONTROLLED ELECTRIC CURRENT Filed March 28, 1928 J.E.LILIENFELD 7 Capacitor structure with notch Negative bias Gate Electrode Gate Insulator Semiconductor Electron No current Positive bias Electric field Current flows 8 G Surface Gate electrode Gate Oxd Channel Drain Source SD Electron flow 0 bias for gate Positive bias for gate Surface Potential (Negative direction) Negative 0V 0V N+-Si P-Si N+-Si P-Si 1V 1V N-Si N-Si Source Channel Drain Source Channel Drain 9 However, no one could realize MOSFET operation for more than 30 years. Because of very bad interface property between the semiconductor and gate insulator Even Shockley! 10 Very bad interface property between the semiconductor and gate insulator Interfacial Charges GeO Electric Shielding Carrier Ge e Scattering Drain Current was several orders of magnitude smaller than expected Even Shockley! 11 However, they found amplification phenomenon when investigating Ge surface when putting needles. This is the 1st Transistor: Not Field Effect Transistor, But Bipolar Transistor (another mechanism) 1947: 1st transistor J. Bardeen W. Bratten, W. Shockley Bipolar using Ge 12 1958: 1st Integrated Circuit Jack S. Kilby Connect 2 bipolar transistors in the Same substrate by bonding wire. 13 1960: First MOSFET by D. Kahng and M. Atalla Top View 断面 e i at S G ce Al ur So Al SiO2 n ai Si Dr Si Si/SiO2 Interface is extraordinarily good 14 1970,71: 1st generation of LSIs DRAM Intel 1103 MPU Intel 4004 15 MOS LSI experienced continuous progress for many years Name of Integrated Circuits Number of Transistors 1960s IC (Integrated Circuits) ~ 10 1970s LSI (Large Scale Integrated Circuit) ~1,000 1980s VLSI (Very Large Scale IC) ~10,000 1990s ULSI (Ultra Large Scale IC) ~1,000,000 2000s ?LSI (? Large Scale IC) ~1000,000,00016 Gate Electrode Gate Insulator Substrate Poly Si SiO2 Si Use Gate Field Effect for switching Gate Electrode Gate Insulator Poly Si SiO2 Source e e Drain Si Channel N‐MOS (N‐type MOSFET) Substrate17 N‐MOS Gate (N‐type MOSFET) Source Drain Electron flow Current flow P‐MOS Gate (P‐type MOSFET) Source Drain Hole flow Current flow 18 OFF Gate ON Gate 0 V Source 1 V Drain Source Drain 0 V 1 V 0 V 1 V 1 V 1 V Electron flow High Potential Electrons Region 19 Current Positive Gate bias Negative voltage OFF Threshold voltage O N N Threshold O voltage Drain Current OFF Drain Current Current Negative Positive voltage Gate bias 20 CMOS Inverter PMOS Complimentary MOS NMOS When NMOS is ON, PMOS is OFF When PMOS is ON, NMOS is OFF 21 CMOS： Low Power: No DC current from Power supply to the ground VD VD Q Charge Q Discharge C C 1 cycle Clock frequency f 1 1 P = CV 2 2 D P = fCVD 2 2 22 2 input NAND Circuit １Ｖ １Ｖ Input 1 Input 2 AND Input １ １１００ Input ２ １０１０ Output Output １０００ Input 1 Input 2 NAND= NOT・AND Input１ １１００ Input２ １０１０ Output ０１１１ 23 Needless to say, but…. CMOS Technology: Indispensible for our human society Al the human activities are controlled by CMOS living, production, financing, telecommunication, transportation, medical care, education, entertainment, etc. Without CMOS: There is no computer in banks, and world economical activities immediately stop. Cellarer phone dose not exists 24 Downsizing of the components has been the driving force for circuit evolution 1900 1950 1960 1970 2000 Vacuum Transistor IC LSI ULSI Tube 10 cm cm mm 10 µm 100 nm -3 -5 10-7m 10-1m 10-2m 10 m 10 m In 100 years, the size reduced by one million times. There have been many devices from stone age. We have never experienced such a tremendous reduction of devices in human history. 25 Downsizing 1. Reduce Capacitance Reduce switching time of MOSFETs Increase clock frequency Increase circuit operation speed 2. Increase number of Transistors Parallel processing Increase circuit operation speed Downsizing contribute to the performance increase in double ways Thus, downsizing of Si devices is the most important and critical issue.26 Scaling Method: by R. Dennard in 1974 1 Wdep: Space Charge Region (or Depletion Region) Width 1 1 SDWdep has to be suppressed 1 Otherwise, large leakage Wdep between S and D I Leakage current Potential in space charge region is high, and thus, electrons in source are 0 attracted to the space charge region. 0 V 1 K=0.7 X , Y, Z :K, V :K, Na : 1/K for By the scaling, Wdep is suppressed in proportion, example and thus, leakage can be suppressed. K Good scaled I-V characteristics K K Wdep V/Na K Wdep I I : K : K 0 0K 27 V 27 Downscaling merit: Beautiful! Geometry & L , W g g K Scaling K : K=0.7 for example Supply voltage Tox, Vdd Id = vsatWgCo (Vg‐Vth) Co: gate C per unit area Drive current I d K –1 ‐1 ‐1 in saturation Wg (tox )(Vg‐Vth)= Wgtox (Vg‐Vth)= KK K=K Id per unit Wg Id/µm 1 Id per unit Wg = Id / Wg= 1 Gate capacitance Cg K Cg = εoεoxLgWg/tox KK/K = K Switching speed τ K τ= CgVdd/Id KK/K= K Clock frequency f 1/K f = 1/τ = 1/K Chip area Achip α α: Scaling factor In the past, α>1 for most cases Integration (# of Tr) N α/K2 N α/K2 = 1/K2 , when α=1 Power per chip P α fNCV2/2 K‐1(αK‐2)K (K1 )2= α = 1, when α=1 28 28 k= 0.7 and α =1 k= 0.72 =0.5 and α =1 Single MOFET Vdd 0.7 Vdd 0.5 Lg 0.7 Lg 0.5 Id 0.7 Id 0.5 Cg 0.7 Cg 0.5 P (Power)/Clock P (Power)/Clock 0.73 = 0.34 0.53 = 0.125 τ (Switching time) 0.7 τ (Switching time) 0.5 Chip N (# of Tr) 1/0.72 = 2 N (# of Tr) 1/0.52 = 4 f (Clock) 1/0.7 = 1.4 f (Clock) 1/0.5 = 2 P (Power) 1 P (Power) 1 29 29 Actual past downscaling trend until year 2000 10 2 Past 30 years scaling Minimum logic Vdd (V) 10 3 10 1 Merit: N, f increase M 2 ） z) PU （mm H L ize (M X g (µm ip s cy 10 0 j (µm ) ch uen Demerit: P increase ) 10 1 req Id/µm k f (mA/µm) loc ) c S (W s -1 IP r or 10 t M ist ox (µm owe ns ) -1 p ra V scaling insufficient 10 f t dd -2 r o 10 be m Nu 10 -3 10 -3 Additional significant 1970 1980 1990 2000 1970 1980 1990 2000 increase in Source. Iwai and S. Ohmi, Microelectronics Reliability 42 (2002), pp.1251-1268 I , f, P Change in 30 years d Ideal Real Ideal Real Ideal Real scaling Change scaling Change scaling Change ‐2 Lg K 10 –2 ‐1 –2 ‐2 Id K (10 ) 10 f 1/K(10 2) 103 tox K(10 ) 10 –2 10‐1 I /µm 1 101 Vdd K(10 ) d P α(10 1) 105 2 5 4 2 Achip α 101 N α/K (10 ) 10 = fαNCV Vd scaling insufficient, α increased 30 N, Id, f, P increased significantly 30 Many people wanted to say about the limit. Past predictions were not correct!! Period Expected Cause limit(size) Late 1970’s 1µm: SCE Early 1980’s 0.5µm: S/D resistance Early 1980’s 0.25µm: Direct‐tunneling of gate SiO2 Late 1980’s 0.1µm: ‘0.1µm brick wall’(various) 2000 50nm: ‘Red brick wall’ (various) 2000 10nm: Fundamental? 31 Historically, many predictions of the limit of downsizing. VLSI text book written 1979 predict that 0.25 micro‐ meter would be the limit because of direct‐ tunneling current through the very thin‐gate oxide. C. Mead L. Conway 33 VLSI textbook Finally, there appears to be a fundamental limit 10 of approximately quarter micron channel length, where certain physical effects such as the tunneling through the gate oxide ....
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