Nanoelectronics the Original Positronic Brain?
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Resonance-Enhanced Waveguide-Coupled Silicon-Germanium Detector L
Resonance-enhanced waveguide-coupled silicon-germanium detector L. Alloatti and R. J. Ram Citation: Applied Physics Letters 108, 071105 (2016); doi: 10.1063/1.4941995 View online: http://dx.doi.org/10.1063/1.4941995 View Table of Contents: http://scitation.aip.org/content/aip/journal/apl/108/7?ver=pdfcov Published by the AIP Publishing Articles you may be interested in Waveguide-coupled detector in zero-change complementary metal–oxide–semiconductor Appl. Phys. Lett. 107, 041104 (2015); 10.1063/1.4927393 Efficient evanescent wave coupling conditions for waveguide-integrated thin-film Si/Ge photodetectors on silicon- on-insulator/germanium-on-insulator substrates J. Appl. Phys. 110, 083115 (2011); 10.1063/1.3642943 Metal-semiconductor-metal Ge photodetectors integrated in silicon waveguides Appl. Phys. Lett. 92, 151114 (2008); 10.1063/1.2909590 Guided-wave near-infrared detector in polycrystalline germanium on silicon Appl. Phys. Lett. 87, 203507 (2005); 10.1063/1.2131175 Back-side-illuminated high-speed Ge photodetector fabricated on Si substrate using thin SiGe buffer layers Appl. Phys. Lett. 85, 3286 (2004); 10.1063/1.1805706 Reuse of AIP Publishing content is subject to the terms at: https://publishing.aip.org/authors/rights-and-permissions. IP: 18.62.22.131 On: Mon, 07 Mar 2016 17:12:57 APPLIED PHYSICS LETTERS 108, 071105 (2016) Resonance-enhanced waveguide-coupled silicon-germanium detector L. Alloattia),b) and R. J. Ram Massachusetts Institute of Technology, Cambridge, Massachusetts 02139, USA (Received 5 January 2016; accepted 3 February 2016; published online 16 February 2016) A photodiode with 0.55 6 0.1 A/W responsivity at a wavelength of 1176.9 nm has been fabricated in a 45 nm microelectronics silicon-on-insulator foundry process. -
Which Is the Best Dual-Port SRAM in 45-Nm Process Technology? – 8T, 10T Single End, and 10T Differential –
Which is the Best Dual-Port SRAM in 45-nm Process Technology? – 8T, 10T Single End, and 10T Differential – Hiroki Noguchi†, Shunsuke Okumura†, Yusuke Iguchi†, Hidehiro Fujiwara†, Yasuhiro Morita†, Koji Nii†,††, Hiroshi Kawaguchi†, and Masahiko Yoshimoto† † Kobe University, Kobe, 657-8501 Japan. †† Renesas Technology Corporation, Itami, 664-0005 Japan. Phone: +81-78-803-6234, E-mail: [email protected] read ports. The next section describes their cell topologies. Abstract— This paper compares readout powers and operating frequencies among dual-port SRAMs: an 8T SRAM, 10T II. CELL TOPOLOGIES single-end SRAM, and 10T differential SRAM. The conventional 8T SRAM has the least transistor count, and is the most area A. 8T SRAM efficient. However, the readout power becomes large and the (a) cycle time increases due to peripheral circuits. The 10T Precharge Precharge circuit single-end SRAM is our proposed SRAM, in which a dedicated signal MC inverter and transmission gate are appended as a single-end read Bitline leakage port. The readout power of the 10T single-end SRAM is reduced by 75% and the operating frequency is increased by 95%, over the 8T SRAM. On the other hand the 10T differential SRAM can MC Memory cell (MC) operate fastest, because its small differential voltage of 50 mV RWL achieves the high-speed operation. In terms of the power WWL Readout current efficiency, however, the sense amplifier and precharge circuits lead to the power overhead. As a result, the 10T single-end P1 P2 Bitline keeper SRAM always consumes lowest readout power compared to the 8T and the 10T differential SRAM. -
Technology Roadmap for 22Nm CMOS and Beyond
Technology Roadmap for 22nm CMOS and beyond June 1, 2009 IEDST 2009@IIT-Bombay Hiroshi Iwai Tokyo Institute of Technology 1 Outline 1. Scaling 2. ITRS Roadmap 3. Voltage Scaling/ Low Power and Leakage 4. SRAM Cell Scaling 5.Roadmap for further future as a personal view 2 1. Scaling 3 Scaling Method: by R. Dennard in 1974 1 Wdep: Space Charge Region (or Depletion Region) Width 1 1 SDWdep has to be suppressed 1 Otherwise, large leakage Wdep between S and D I Leakage current Potential in space charge region is high, and thus, electrons in source are 0 attracted to the space charge region. 0 V 1 K=0.7 X , Y, Z :K, V :K, Na : 1/K for By the scaling, Wdep is suppressed in proportion, example and thus, leakage can be suppressed. K Good scaled I-V characteristics K K Wdep V/Na K Wdep I I : K : K 0 0K V 4 Downscaling merit: Beautiful! Geometry & L , W g g K Scaling K : K=0.7 for example Supply voltage Tox, Vdd Id = vsatWgCo (Vg‐Vth) Co: gate C per unit area Drive current I d K –1 ‐1 ‐1 in saturation Wg (tox )(Vg‐Vth)= Wgtox (Vg‐Vth)= KK K=K Id per unit Wg Id/µm 1 Id per unit Wg = Id / Wg= 1 Gate capacitance Cg K Cg = εoεoxLgWg/tox KK/K = K Switching speed τ K τ= CgVdd/Id KK/K= K Clock frequency f 1/K f = 1/τ = 1/K Chip area Achip α α: Scaling factor In the past, α>1 for most cases Integration (# of Tr) N α/K2 N α/K2 = 1/K2 , when α=1 Power per chip P α fNCV2/2 K‐1(αK‐2)K (K1 )2= α = 1, when α=1 5 k= 0.7 and α =1 k= 0.72 =0.5 and α =1 Single MOFET Vdd 0.7 Vdd 0.5 Lg 0.7 Lg 0.5 Id 0.7 Id 0.5 Cg 0.7 Cg 0.5 P (Power)/Clock P (Power)/Clock 0.73 = 0.34 0.53 = 0.125 τ (Switching time) 0.7 τ (Switching time) 0.5 Chip N (# of Tr) 1/0.72 = 2 N (# of Tr) 1/0.52 = 4 f (Clock) 1/0.7 = 1.4 f (Clock) 1/0.5 = 2 P (Power) 1 P (Power) 1 6 - The concerns for limits of down-scaling have been announced for every generation. -
A Study of the Foundry Industry Dynamics
A Study of the Foundry Industry Dynamics by Sang Jin Oh B.S. Industrial Engineering Seoul National University, 2003 SUBMITTED TO THE MIT SLOAN SCHOOL OF MANAGEMENT IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF MASTER OF SCIENCE IN MANAGEMENT STUDIES AT THE MASSACHUSETTS INSTITUTE OF TECHNOLOGY ARCHVES JUNE 2010 MASSACHUSETTS INSTiUTE OF TECHNOLOGY © 2010 Sang Jin Oh. All Rights Reserved. The author hereby grants MIT permission to reproduce JUN 082010 and to distribute publicly paper and electronic LIBRARIES copies of this thesis document in whole or in part in any medium now known and hereafter created. Signature of Author Sang Jin Oh Master of Science in Management Studies May 7, 2010 Certified by (7 Michael A. Cusumano SMR Distinguished Professor of Management Thesis Supervisor Accepted by (I Michael A. Cusumano Faculty Director, M.S. in Management Studies Program MIT Sloan School of Management A Study of the Foundry Industry Dynamics By Sang Jin Oh Submitted to the MIT Sloan School of Management On May 7, 2010 In Partial Fulfillment of the Requirements for the Degree of Master of Science in Management Studies Abstract In the process of industrial evolution, it is a general tendency that companies which specialize in a specific value chain have emerged. These companies should construct a business eco-system based on their own platform to compete successfully with vertically integrated companies and other specialized companies. They continue to sustain their competitive advantage only when they share their ability to create value with other eco-system partners. The thesis analyzes the dynamics of the foundry industry. -
AN-Introducing 45Nm Technology in Microwind
Introducing 45 nm technology in Microwind3 MICROWIND APPLICATION NOTE Introducing 45 nm technology in Microwind3 Etienne SICARD Syed Mahfuzul Aziz Professor School of Electrical & Information Engineering INSA-Dgei, 135 Av de Rangueil University of South Australia 31077 Toulouse – France Mawson Lakes, SA 5095, Australia www.microwind.org www.unisa.edu.au email: [email protected] email: [email protected] This paper describes the improvements related to the CMOS 45 nm technology and the implementation of this technology in Microwind3. The main novelties related to the 45 nm technology such as the high-k gate oxide, metal- gate and very low-K interconnect dielectric is described. The performances of a ring oscillator layout and a 6- transistor RAM memory layout are also analyzed. 1. Recent trends in CMOS technology Firstly, we give an overview of the evolution of important parameters such as the integrated circuit (IC) complexity, gate length, switching delay and supply voltage with a prospective vision down to the 22 nm CMOS technology. The trend of CMOS technology improvement continues to be driven by the need to integrate more functions within a given silicon area. Table 1 gives an overview of the key parameters for technological nodes from 180 nm, introduced in 1999, down to 22 nm, which is supposed to be in production around 2011. Demonstration chips using 45-nm technology have been reported starting in 2004. Mass market manufacturing with this technology is scheduled for late 2007. Technology node 130 nm 90 nm 65 nm 45 nm 32 nm 22 nm First production 2001 2003 2005 2007 2009 2011 Effective gate 70 nm 50 nm 35 nm 25 nm 17 nm 12 nm length Gate material Poly Poly Poly Metal Metal Metal Gate dielectric SiO2 SiO2 SiON High K High K High K Kgates/mm2 240 480 900 1500 2800 4500 Memory point (2) 2.4 1.3 0.6 0.3 0.15 0.08 Table 1: Technological evolution and forecast up to 2011 The gate material has long been polysilicon, with silicon dioxide (SiO2) as the insulator between the gate and the channel (Fig. -
The New Era of Scaling in an Soc World
2009 ISSCC The New Era of Scaling in an SoC World Mark Bohr Intel Senior Fellow Logic Technology Development 1 The End of Scaling is Near? “Optical lithography will reach its limits in the range of 0.75-0.50 microns” “Minimum geometries will saturate in the range of 0.3 to 0.5 microns” “X-ray lithography will be needed below 1 micron” “Minimum gate oxide thickness is limited to ~2 nm” “Copper interconnects will never work” “Scaling will end in ~10 years” Perceived barriers are meant to be surmounted, circumvented or tunneled through 2 Outline • Transistor Scaling • Microprocessor Evolution • Vision of the Future 3 Scaling Trends 10 CPU Transistor Count 10 9 2x every 2 years 1 10 7 Microns 0.1 10 5 3 0.01 10 1970 1980 1990 2000 2010 2020 Transistor dimensions scale to improve performance, reduce power and reduce cost per transistor 4 Scaling Trends 10 CPU Transistor Count 10 9 2x every 2 years 1 10 7 Microns 0.1 65nm 10 5 45nm Feature Size 32nm 0.7x every 2 years 3 0.01 10 1970 1980 1990 2000 2010 2020 Transistor dimensions scale to improve performance, reduce power and reduce cost per transistor 5 MOSFET Scaling Device or Circuit Parameter Scaling Factor Device dimension tox, L, W 1/ κ Doping concentration Na κ Voltage V 1/ κ Current I 1/ κ Capacitance εA/t 1/ κ Delay time/circuit VC/I 1/ κ Power dissipation/circuit VI 1/ κ2 Power density VI/A 1 R. Dennard, IEEE JSSC, 1974 Classical MOSFET scaling was first described in 1974 6 30 Years of MOSFET Scaling Dennard 1974 Intel 2005 1 µm Gate Length: 1.0 µm 35 nm Gate Oxide Thickness: 35 nm -
Brains, Minds, and Computers in Literary and Science Fiction Neuronarratives
BRAINS, MINDS, AND COMPUTERS IN LITERARY AND SCIENCE FICTION NEURONARRATIVES A dissertation submitted to Kent State University in partial fulfillment of the requirements for the degree of Doctor of Philosophy. by Jason W. Ellis August 2012 Dissertation written by Jason W. Ellis B.S., Georgia Institute of Technology, 2006 M.A., University of Liverpool, 2007 Ph.D., Kent State University, 2012 Approved by Donald M. Hassler Chair, Doctoral Dissertation Committee Tammy Clewell Member, Doctoral Dissertation Committee Kevin Floyd Member, Doctoral Dissertation Committee Eric M. Mintz Member, Doctoral Dissertation Committee Arvind Bansal Member, Doctoral Dissertation Committee Accepted by Robert W. Trogdon Chair, Department of English John R.D. Stalvey Dean, College of Arts and Sciences ii TABLE OF CONTENTS Acknowledgements ........................................................................................................ iv Chapter 1: On Imagination, Science Fiction, and the Brain ........................................... 1 Chapter 2: A Cognitive Approach to Science Fiction .................................................. 13 Chapter 3: Isaac Asimov’s Robots as Cybernetic Models of the Human Brain ........... 48 Chapter 4: Philip K. Dick’s Reality Generator: the Human Brain ............................. 117 Chapter 5: William Gibson’s Cyberspace Exists within the Human Brain ................ 214 Chapter 6: Beyond Science Fiction: Metaphors as Future Prep ................................. 278 Works Cited ............................................................................................................... -
Liable Machines 7 CHAPTER 7
Liable Machines 7 CHAPTER 7 After lighting a cigarette, Alfred Lanning, declared, “It reads minds all right.”1 Lanning was a recurrent character in Isaac Asimov’s science fiction. In this particular story, the director of a plant of U.S. Robots and Mechanical Men was talking about Her- bie, a robot with “a positronic brain of supposedly ordinary vintage.” Herbie had the ability to “tune in on thought waves,” leaving Lanning and his colleagues baffled by his ability to read minds. Herbie was “the most important advance in robotics in decades.” But neither Lanning nor his team knew how it happened. Lanning’s team included Peter Bogert, a mathematician and second-in-command to Lanning; Milton Ashe, a young officer at U.S. Robots and Mechanical Men; and Dr. Susan Calvin, a robopsychologist (who happened to be in love with Ashe). Lanning asked Dr. Calvin to study Herbie first. She sat down with the robot, who had recently finished reading a pile of science books. “It’s your fiction that interests me,” said Herbie. “Your studies of the interplay of human motives and emotions.” As Dr. Calvin listened, she begun to think about Milton Ashe. “He loves you,”—the robot whispered. 150 | LIABLE MACHINES “For a full minute, Dr. Calvin did not speak. She merely stared.” “You are mistaken! You must be. Why should he?” “But he does. A thing like that cannot be hidden, not from me.” Then he supported his statement with irresistible rationality: “He looks deeper than the skin and admires intellect in others. Milton Ashe is not the type to marry a head of hair and a pair of eyes.” She was convinced. -
45 Nm Process
INTEL FIRST TO DEMONSTRATE WORKING 45 nm CHIPS New Technology Will Improve Energy Efficiency and Boost Capabilities of Future Intel Platforms Mark Bohr Intel Senior Fellow Director of Process Architecture & Integration January 2006 1 65 nm Status • Announced shipping 65nm for revenue in Oct. 2005 • Two 65nm/300mm fabs shipping in volume (D1D and Fab 12); with two more coming in 2006 • Intel has shipped more than a million dual- core processors made on 65nm process technology • CPU shipment cross-over from 90nm to 65nm projected for Q3/06 2 What are We Announcing Today? • Intel is first to reach an important milestone in the development of 45 nm logic technology • Fully functional 153 Mbit SRAM chips have been made with >1 billion transistors each • The memory cell size on these SRAM chips is 0.346 μm2, almost half the size of the 65 nm cell • This milestone demonstrates that Intel is on track for delivery of its 45 nm logic technology in 2H 2007 3 45 nm Technology Benefits Compared to today’s 65 nm technology, the 45 nm technology will provide the following product benefits: ~2x improvement in transistor density, for either smaller chip size or increased transistor count >20% improvement in transistor switching speed or >5x reduction in leakage power >30% reduction in transistor switching power This process technology will provide the foundation to deliver improved performance/Watt that will enhance the user experience 4 Intel's Logic Technology Evolution Process Name P1262 P1264 P1266 P1268 Lithography 90 nm 65 nm 45 nm 32 nm 1st Production -
Logan Brooks Journal Prompt #4: Technical Communication and Science Fiction
Logan Brooks Journal Prompt #4: Technical Communication and Science Fiction I cannot call myself an avid reader, but I am a fan of the science fiction genre. To me, science fiction is a story or idea that assimilates popular and contemporary culture in a way that is magnificent and stunning to its audience at the time. In addition, science fiction tries to portray possible future technologies off of already existing technologies. There are numerous examples of this throughout literature and film. Take for example Isaac Asimov's I, Robot. The robots have “positronic brains”, devices that give them their “pre-natal education.” The positron was first discovered around the time Asimov wrote I, Robot. He took an already existing idea or technology and portrayed it in a way that sounded futuristic and interesting to his readers. Looking back, a positronic brain doesn't sound as interesting as it likely did in the 1950's. Positrons are part of quantum mechanics, so a positronic brain isn't that far- fetched I suppose. Star Trek is still popular to this day. It has retained its popularity not only through brilliant portrayals of futuristic technology, but also through memorable dialogue. “Live Long and Prosper” will likely invoke subconscious memories of Star Trek even by people who have never actually watched an episode. In addition, it took present day technologies (1960's) and portrayed them in a retro-futuristic way. The communicator was based off of land-line telephones, but portrayed a cell phone like quality, even down to the flip display. Also, Star Trek was very adamant on using their superior technology ethically and safely. -
Si MOSFET Roadmap for 22Nm and Beyond
Si MOSFET Roadmap for 22nm and beyond December 16, 2009 Jadavpur University @ Kolkata, India Hiroshi Iwai Tokyo Institute of Technology 1 Outline 1. Scaling 2. ITRS Roadmap 3. Voltage Scaling/ Low Power and Leakage 4. SRAM Cell Scaling 5.Roadmap for further future 2 1. Scaling 3 Scaling Method: by R. Dennard in 1974 1 Wdep: Space Charge Region (or Depletion Region) Width 1 1 SDWdep has to be suppressed 1 Otherwise, large leakage Wdep between S and D I Leakage current Potential in space charge region is high, and thus, electrons in source are 0 attracted to the space charge region. 0 V 1 K=0.7 X , Y, Z :K, V :K, Na : 1/K for By the scaling, Wdep is suppressed in proportion, example and thus, leakage can be suppressed. K Good scaled I-V characteristics K K Wdep V/Na K Wdep I I : K : K 0 0K V 4 Downscaling merit: Beautiful! Geometry & L , W g g K Scaling K : K=0.7 for example Supply voltage Tox, Vdd Id = vsatWgCo (Vg‐Vth) Co: gate C per unit area Drive current I d K –1 ‐1 ‐1 in saturation Wg (tox )(Vg‐Vth)= Wgtox (Vg‐Vth)= KK K=K Id per unit Wg Id/µm 1 Id per unit Wg = Id / Wg= 1 Gate capacitance Cg K Cg = εoεoxLgWg/tox KK/K = K Switching speed τ K τ= CgVdd/Id KK/K= K Clock frequency f 1/K f = 1/τ = 1/K Chip area Achip α α: Scaling factor In the past, α>1 for most cases Integration (# of Tr) N α/K2 N α/K2 = 1/K2 , when α=1 Power per chip P α fNCV2/2 K‐1(αK‐2)K (K1 )2= α = 1, when α=1 5 2 Generations k= 0.72 =0.5 and α =1 Single MOFET Vdd 0.5 Lg 0.5 Id 0.5 Cg 0.5 P (Power)/Clock 0.53 = 0.125 τ (Switching time) 0.5 Chip N (# of Tr) 1/0.52 = 4 f (Clock) 1/0.5 = 2 P (Power) 1 6 - The concerns for limits of down-scaling have been announced for every generation. -
I-Robot Points for Understanding Answer
Pre-intermediate Level Points for Understanding Answer Key I, Robot Isaac Asimov 1 a Harm: to injure, damage or have a bad effect on someone or something. This is important within the first law because robots are superior to humans and very powerful. If this rule did not exist, robots would be very dangerous. b Conflict: if different statements or suggestions conflict, they cannot all be right or they cannot all happen. This is important within the second and third laws because it makes sure robots obey c Protect: to keep someone or something safe. The process of keeping someone or something safe is called protection. This is important because a robot has to keep itself safe. 2 She’s a robot-psychologist. She is intelligent and has a plain face. She behaves coldly toward people and things around her, but robots excite her. 3 The reporter is interviewing Susan Calvin because he’s writing an article for The Interplanetary Press. He wants information about her involvement with robots. 2 a Gloria thinks Robbie is her friend because they play games together and she tells him stories. She is very upset when he is taken away. b Grace Weston is frightened of Robbie because she thinks he might hurt Gloria and she doesn’t want a machine looking after her daughter. c George Weston thinks Robbie is Gloria’s nanny and is unable to hurt Gloria he was made to be gentle and nice. 2 Mr Weston arranges for the family to go to New York because Gloria becomes very unhappy.