Intel's Atom Lines 1. Introduction to Intel's Atom Lines 3. Atom-Based Platforms Targeting Entry Level Desktops and Notebook
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Wind River Vxworks Platforms 3.8
Wind River VxWorks Platforms 3.8 The market for secure, intelligent, Table of Contents Build System ................................ 24 connected devices is constantly expand- Command-Line Project Platforms Available in ing. Embedded devices are becoming and Build System .......................... 24 VxWorks Edition .................................2 more complex to meet market demands. Workbench Debugger .................. 24 New in VxWorks Platforms 3.8 ............2 Internet connectivity allows new levels of VxWorks Simulator ....................... 24 remote management but also calls for VxWorks Platforms Features ...............3 Workbench VxWorks Source increased levels of security. VxWorks Real-Time Operating Build Configuration ...................... 25 System ...........................................3 More powerful processors are being VxWorks 6.x Kernel Compatibility .............................3 considered to drive intelligence and Configurator ................................. 25 higher functionality into devices. Because State-of-the-Art Memory Host Shell ..................................... 25 Protection ..................................3 real-time and performance requirements Kernel Shell .................................. 25 are nonnegotiable, manufacturers are VxBus Framework ......................4 Run-Time Analysis Tools ............... 26 cautious about incorporating new Core Dump File Generation technologies into proven systems. To and Analysis ...............................4 System Viewer ........................ -
Intel® Architecture Instruction Set Extensions and Future Features Programming Reference
Intel® Architecture Instruction Set Extensions and Future Features Programming Reference 319433-037 MAY 2019 Intel technologies features and benefits depend on system configuration and may require enabled hardware, software, or service activation. Learn more at intel.com, or from the OEM or retailer. No computer system can be absolutely secure. Intel does not assume any liability for lost or stolen data or systems or any damages resulting from such losses. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifica- tions. Current characterized errata are available on request. This document contains information on products, services and/or processes in development. All information provided here is subject to change without notice. Intel does not guarantee the availability of these interfaces in any future product. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1- 800-548-4725, or by visiting http://www.intel.com/design/literature.htm. Intel, the Intel logo, Intel Deep Learning Boost, Intel DL Boost, Intel Atom, Intel Core, Intel SpeedStep, MMX, Pentium, VTune, and Xeon are trademarks of Intel Corporation in the U.S. -
1 in the United States District Court
Case 6:20-cv-00779 Document 1 Filed 08/25/20 Page 1 of 33 IN THE UNITED STATES DISTRICT COURT WESTERN DISTRICT OF TEXAS AUSTIN DIVISION AURIGA INNOVATIONS, INC. C.A. No. 6:20-cv-779 Plaintiff, v. JURY TRIAL DEMANDED INTEL CORPORATION, HP INC., and HEWLETT PACKARD ENTERPRISE COMPANY, Defendants COMPLAINT Plaintiff Auriga Innovations, Inc. (“Auriga” or “Plaintiff”) files this complaint for patent infringeMent against Defendants Intel Corporation (“Intel”), HP Inc. (“HPI”), and Hewlett Packard Enterprise Company (“HPE”) (collectively, “Defendants”) under 35 U.S.C. § 217 et seq. as a result of Defendants’ unauthorized use of Auriga’s patents and alleges as follows: THE PARTIES 1. Auriga is a corporation organized and existing under the laws of the state of Delaware with its principal place of business at 1891 Robertson Road, Suite 100, Ottawa, ON K2H 5B7 Canada. 2. On information and belief, Intel is a Delaware corporation with a place of business at 2200 Mission College Boulevard, Santa Clara, California 95054. 3. On information and belief, since April 1989, Intel has been registered to do business in the State of Texas under Texas Taxpayer Number 19416727436 and has places of business at 1 Case 6:20-cv-00779 Document 1 Filed 08/25/20 Page 2 of 33 1300 S Mopac Expressway, Austin, Texas 78746; 6500 River Place Blvd, Bldg 7, Austin, Texas 78730; and 5113 Southwest Parkway, Austin, Texas 78735 (collectively, “Intel Austin Offices”). https://www.intel.com/content/www/us/en/location/usa.htMl. 4. On information and belief, HPI is a Delaware corporation with a principal place of business at 1501 Page Mill Road, Palo Alto, CA 94304. -
Resonance-Enhanced Waveguide-Coupled Silicon-Germanium Detector L
Resonance-enhanced waveguide-coupled silicon-germanium detector L. Alloatti and R. J. Ram Citation: Applied Physics Letters 108, 071105 (2016); doi: 10.1063/1.4941995 View online: http://dx.doi.org/10.1063/1.4941995 View Table of Contents: http://scitation.aip.org/content/aip/journal/apl/108/7?ver=pdfcov Published by the AIP Publishing Articles you may be interested in Waveguide-coupled detector in zero-change complementary metal–oxide–semiconductor Appl. Phys. Lett. 107, 041104 (2015); 10.1063/1.4927393 Efficient evanescent wave coupling conditions for waveguide-integrated thin-film Si/Ge photodetectors on silicon- on-insulator/germanium-on-insulator substrates J. Appl. Phys. 110, 083115 (2011); 10.1063/1.3642943 Metal-semiconductor-metal Ge photodetectors integrated in silicon waveguides Appl. Phys. Lett. 92, 151114 (2008); 10.1063/1.2909590 Guided-wave near-infrared detector in polycrystalline germanium on silicon Appl. Phys. Lett. 87, 203507 (2005); 10.1063/1.2131175 Back-side-illuminated high-speed Ge photodetector fabricated on Si substrate using thin SiGe buffer layers Appl. Phys. Lett. 85, 3286 (2004); 10.1063/1.1805706 Reuse of AIP Publishing content is subject to the terms at: https://publishing.aip.org/authors/rights-and-permissions. IP: 18.62.22.131 On: Mon, 07 Mar 2016 17:12:57 APPLIED PHYSICS LETTERS 108, 071105 (2016) Resonance-enhanced waveguide-coupled silicon-germanium detector L. Alloattia),b) and R. J. Ram Massachusetts Institute of Technology, Cambridge, Massachusetts 02139, USA (Received 5 January 2016; accepted 3 February 2016; published online 16 February 2016) A photodiode with 0.55 6 0.1 A/W responsivity at a wavelength of 1176.9 nm has been fabricated in a 45 nm microelectronics silicon-on-insulator foundry process. -
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1 2 Speed, speed, speed $1000 TCR hashing competition D. J. Bernstein Crowley: “I have a problem where I need to make some University of Illinois at Chicago; cryptography faster, and I’m Ruhr University Bochum setting up a $1000 competition funded from my own pocket for Reporting some recent work towards the solution.” symmetric-speed discussions, Not fast enough: Signing H(M), especially from RWC 2020. where M is a long message. Not included in this talk: “[On a] 900MHz Cortex-A7 NISTLWC. • [SHA-256] takes 28.86 cpb ::: Short inputs. • BLAKE2b is nearly twice as FHE/MPC ciphers. • fast ::: However, this is still a lot slower than I’m happy with.” 1 2 3 Speed, speed, speed $1000 TCR hashing competition Instead choose random R and sign (R; H(R; M)). D. J. Bernstein Crowley: “I have a problem where I need to make some Note that H needs only “TCR”, University of Illinois at Chicago; cryptography faster, and I’m not full collision resistance. Ruhr University Bochum setting up a $1000 competition Does this allow faster H design? funded from my own pocket for TCR breaks how many rounds? Reporting some recent work towards the solution.” symmetric-speed discussions, Not fast enough: Signing H(M), especially from RWC 2020. where M is a long message. Not included in this talk: “[On a] 900MHz Cortex-A7 NISTLWC. • [SHA-256] takes 28.86 cpb ::: Short inputs. • BLAKE2b is nearly twice as FHE/MPC ciphers. • fast ::: However, this is still a lot slower than I’m happy with.” 1 2 3 Speed, speed, speed $1000 TCR hashing competition Instead choose random R and sign (R; H(R; M)). -
Microcode Revision Guidance August 31, 2019 MCU Recommendations
microcode revision guidance August 31, 2019 MCU Recommendations Section 1 – Planned microcode updates • Provides details on Intel microcode updates currently planned or available and corresponding to Intel-SA-00233 published June 18, 2019. • Changes from prior revision(s) will be highlighted in yellow. Section 2 – No planned microcode updates • Products for which Intel does not plan to release microcode updates. This includes products previously identified as such. LEGEND: Production Status: • Planned – Intel is planning on releasing a MCU at a future date. • Beta – Intel has released this production signed MCU under NDA for all customers to validate. • Production – Intel has completed all validation and is authorizing customers to use this MCU in a production environment. -
Nanoelectronics the Original Positronic Brain?
Nanoelectronics the Original Positronic Brain? Dan Hammerstrom Department of Electrical and Computer Engineering Portland State University Maseeh College of Engineering 12/13/08 1 and Computer Science Wikipedia: “A positronic brain is a fictional technological device, originally conceived by science fiction writer Isaac Asimov “Its role is to serve as a central computer for a robot, and, in some unspecified way, to provide it with a form of consciousness recognizable to humans” How close are we? You can judge the algorithms, in this talk I will focus on hardware and what the future might hold Maseeh College of Engineering 12/13/08 Hammerstrom 2 and Computer Science Moore’s Law: The number of transistors doubles every 18-24 months No discussion of computing is complete without addressing Moore’s law The semiconductor industry has been following it for almost 30 years It is not really a physical law, but one of faith The fruits of a hyper-competitive $300 billion global industry Then there is Moore’s lesser known 2nd law st The 1 law requires exponentially increasing investment And what I call Moore’s 3rd law st The 1 law results in exponentially increasing design errata Maseeh College of Engineering 12/13/08 Hammerstrom 3 and Computer Science Intel is now manufacturing in their new, innovative 45 nm process Effective gate lengths of 37 nm (HkMG) And they recently announced a 32 nm scaling of the 45 nm process Transistors of this size are no longer acting like ideal switches And there are other problems … 45 nm Transistor -
Intel® Atom™ Processor E6x5c Series-Based Platform for Embedded Computing
PlAtfOrm brief Intel® Atom™ Processor E6x5C Series Embedded Computing Intel® Atom™ Processor E6x5C Series-Based Platform for Embedded Computing Platform Overview Available with industrial and commercial The Intel® Atom™ processor E6x5C series temperature ranges, this processor series delivers, in a single package, the benefits of provides embedded lifecycle support and the Intel® Atom™ processor E6xx combined is supported by the broad Intel® archi- with a Field-Programmable Gate Array tecture ecosystem as well as standard (FPGA) from Altera. This series offers Altera development tools. Additionally, a exceptional flexibility to incorporate a compatible, dedicated Power Management wide range of standard and user-defined Integrated Circuit (PMIC) solution may be I/O interfaces, high-speed connectivity, obtained from leading PMIC suppliers to memory interfaces, and process accelera- help minimize platform part count and tion to meet the requirements of a variety reduce bill of material costs and design of embedded applications in industrial, medi- complexity. Options include separate PMIC cal, communication, vision systems, voice and clock generator chips (available from over Internet protocol (VoIP), military, high- ROHM Co., Ltd.) or a single-chip solution performance programmable logic control- that integrates the voltage regulator and lers (PLCs) and embedded computers. clock generator (available from Dialog Semiconductor). The Intel Atom processor E6x5C series is a multi-chip, single-package device that Product Highlights reduces board footprint, lowers compo- • Single-package: A compact 37.5 x nent count, and simplifies inventory 37.5 mm, 0.8 mm ball pitch, multi-chip control and manufacturing. This compact device internally connects the Intel Atom design offers single-vendor support while processor E6xx with a user-programma- providing Intel Atom processors for ble FPGA. -
Intel Atom® Processor C2000 Product Family for Microservers
Intel® Atom™ Processor C2000 Product Family for Microservers PRODUCT BRIEF Maximize Efficiency for Your Lightweight Scale-Out Workloads Extreme Density and Energy-Efficiency for Low-End, Scale-Out Workloads With a need to rapidly deliver new services, cope with massive data growth, and contain costs, cloud service providers and hosters seek increasingly efficient ways to handle the demands on their infrastructure. Today’s servers based on Intel® Xeon® processors provide leadership performance and performance per watt with the flexibility to handle a wide range of workloads and peak demands. 2nd generation 64-bit However, certain lightweight, scale-out workloads—such as basic dedicated hosting, low-end static Intel® Atom™ Processor web serving, and simple content delivery can sometimes be hosted more efficiently on larger C2000 Product Family numbers of smaller servers built for extreme power efficiency. for microservers To address this need, Intel worked with a broad giving you the flexibility to right-size your infra- • Up to 7x higher7 perfor- ecosystem of leading server manufacturers to structure without limiting software mobility and mance, up to 6x better8 develop and deliver a variety of extreme low-power interoperability as your applications evolve. systems to support an emerging server category— performance/watt Optimized Platform Support microservers. With up to a 1,000 nodes1 per Intel provides complete microserver platform 9 rack and shared power, cooling, and networking • 6-20 watt TDP solutions that simplify implementation, improve resources, microservers can help you improve data overall efficiency and enable higher node density. • Up to 1000+ server center efficiency by right-sizing infrastructure for New innovations include: 10 relatively light processing requirements. -
Which Is the Best Dual-Port SRAM in 45-Nm Process Technology? – 8T, 10T Single End, and 10T Differential –
Which is the Best Dual-Port SRAM in 45-nm Process Technology? – 8T, 10T Single End, and 10T Differential – Hiroki Noguchi†, Shunsuke Okumura†, Yusuke Iguchi†, Hidehiro Fujiwara†, Yasuhiro Morita†, Koji Nii†,††, Hiroshi Kawaguchi†, and Masahiko Yoshimoto† † Kobe University, Kobe, 657-8501 Japan. †† Renesas Technology Corporation, Itami, 664-0005 Japan. Phone: +81-78-803-6234, E-mail: [email protected] read ports. The next section describes their cell topologies. Abstract— This paper compares readout powers and operating frequencies among dual-port SRAMs: an 8T SRAM, 10T II. CELL TOPOLOGIES single-end SRAM, and 10T differential SRAM. The conventional 8T SRAM has the least transistor count, and is the most area A. 8T SRAM efficient. However, the readout power becomes large and the (a) cycle time increases due to peripheral circuits. The 10T Precharge Precharge circuit single-end SRAM is our proposed SRAM, in which a dedicated signal MC inverter and transmission gate are appended as a single-end read Bitline leakage port. The readout power of the 10T single-end SRAM is reduced by 75% and the operating frequency is increased by 95%, over the 8T SRAM. On the other hand the 10T differential SRAM can MC Memory cell (MC) operate fastest, because its small differential voltage of 50 mV RWL achieves the high-speed operation. In terms of the power WWL Readout current efficiency, however, the sense amplifier and precharge circuits lead to the power overhead. As a result, the 10T single-end P1 P2 Bitline keeper SRAM always consumes lowest readout power compared to the 8T and the 10T differential SRAM. -
H1 2015-2016 Results
H1 2015-2016 Results November 2015 Safe Harbour Statement This presentation contains forward-looking statements made pursuant to the safe harbour provisions of the Private Securities litigation reform Act of 1995. By nature, forward looking statement represent the judgment regarding future events and are based on currently available information. Although the Company cannot guarantee their accuracy, actual results may differ materially from those the company anticipated due to a number of uncertainties, many of which the Company is not aware. For additional information concerning these and other important factors that may cause the Company’s actual results to differ materially from expectations and underlying assumptions, please refer to the reports filed by the Company with the Autorité des Marchés Financiers (AMF). Soitec – H1 2015-2016 Results – November 2015 2 Agenda 1 Highlights 2 H1 2015-2016 Financial results 3 Outlook 4 Q&A Appendix: Electronics core business Soitec – H1 2015-2016 Results – November 2015 3 H1 2015-2016 - Core Business highlights Communication and Power – Demand remains robust for RF-SOI products in mobile applications; SOI content continues to grow within smartphones due to increased complexity (number of bands and performance) – Bernin 200mm-diameter wafer capacity is almost sold out for CY 2016 – Simgui (Chinese foundry) produced its first 200mm wafers in October 2015 and is now starting customers qualifications – Customers developing successfully 300mm wafers for RF - at least one major fabless and one foundry -
Intel® Industrial Iot Workshop Security for Industrial Platforms
Intel® Industrial IoT workshop Security for industrial platforms Gopi K. Agrawal Security Architect IOTG Technical Sales & Marketing Intel Corporation Legal © 2018 Intel Corporation No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. This document contains information on products, services and/or processes in development. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps. Intel technologies' features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. No computer system can be absolutely secure. Check with your system manufacturer or retailer or learn more at www.intel.com. Intel, the Intel logo, are trademarks of Intel Corporation in the U.S. and/or other countries. *Other names and brands may be claimed as the property of others. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. No computer system can be absolutely secure.