Technology Roadmap for 22Nm CMOS and Beyond

Technology Roadmap for 22nm CMOS and beyond

June 1, 2009

IEDST 2009@IIT-Bombay

Hiroshi Iwai

Tokyo Institute of Technology

1 Outline

1. Scaling

2. ITRS Roadmap

3. Voltage Scaling/ Low Power and Leakage

4. SRAM Cell Scaling

5.Roadmap for further future as a personal view

2 1. Scaling

3 Scaling Method: by R. Dennard in 1974 1 Wdep: Space Charge Region (or Depletion Region) Width 1 1 SDWdep has to be suppressed 1 Otherwise, large leakage Wdep between S and D I

Leakage current Potential in space charge region is high, and thus, electrons in source are 0 attracted to the space charge region. 0 V 1 K=0.7 X , Y, Z :K, V :K, Na : 1/K for By the scaling, Wdep is suppressed in proportion, example and thus, leakage can be suppressed. K Good scaled I-V characteristics K K Wdep V/Na K Wdep I I : K : K 0 0K V 4 Downscaling merit: Beautiful!

Geometry & L , W g g K Scaling K : K=0.7 for example Supply voltage Tox, Vdd

Id = vsatWgCo (Vg‐Vth) Co: gate C per unit area Drive current I d K –1 ‐1 ‐1 in saturation Wg (tox )(Vg‐Vth)= Wgtox (Vg‐Vth)= KK K=K

Id per unit Wg Id/µm 1 Id per unit Wg = Id / Wg= 1

Gate capacitance Cg K Cg = εoεoxLgWg/tox KK/K = K

Switching speed τ K τ= CgVdd/Id KK/K= K

Clock frequency f 1/K f = 1/τ = 1/K

Chip area Achip α α: Scaling factor In the past, α>1 for most cases

Integration (# of Tr) N α/K2 N α/K2 = 1/K2 , when α=1

Power per chip P α fNCV2/2 K‐1(αK‐2)K (K1 )2= α = 1, when α=1 5 k= 0.7 and α =1 k= 0.72 =0.5 and α =1 Single MOFET Vdd 0.7 Vdd 0.5 Lg 0.7 Lg 0.5 Id 0.7 Id 0.5 Cg 0.7 Cg 0.5 P (Power)/Clock P (Power)/Clock 0.73 = 0.34 0.53 = 0.125 τ (Switching time) 0.7 τ (Switching time) 0.5 Chip N (# of Tr) 1/0.72 = 2 N (# of Tr) 1/0.52 = 4 f (Clock) 1/0.7 = 1.4 f (Clock) 1/0.5 = 2 P (Power) 1 P (Power) 1

6 - The concerns for limits of down-scaling have been announced for every generation.

- However, down-scaling of CMOS is still the ‘royal road’* for high performance and low power.

- Effort for the down-scaling has to be continued by all means.

*Euclid of Alexandria (325BC?-265BC?) ‘There is no royal road to Geometry’ Mencius (Meng-zi), China (372BC?-289BC?) (Rule of right vs. Rule of military) 7 Actual past downscaling trend until year 2000 10 2 Past 30 years scaling

Minimum logic Vdd (V) 10 3 10 1 Merit: N, f increase M 2 ） z) PU （mm H L ize (M X g (µm ip s cy 10 0 j (µm ) ch uen Demerit: P increase ) 10 1 req Id/µm k f (mA/µm) loc ) c S (W s -1 IP r or 10 t M ist ox (µm owe ns ) -1 p ra V scaling insufficient 10 f t dd -2 r o 10 be m Nu 10 -3 10 -3 Additional significant 1970 1980 1990 2000 1970 1980 1990 2000 increase in Source. Iwai and S. Ohmi, Microelectronics Reliability 42 (2002), pp.1251-1268 I , f, P Change in 30 years d Ideal Real Ideal Real Ideal Real scaling Change scaling Change scaling Change

‐2 Lg K 10 –2 ‐1 –2 ‐2 Id K (10 ) 10 f 1/K(10 2) 103 tox K(10 ) 10 –2 10‐1 I /µm 1 101 Vdd K(10 ) d P α(10 1) 105 2 5 4 2 Achip α 101 N α/K (10 ) 10 = fαNCV

Vd scaling insufficient, α increased N, Id, f, P increased significantly 8 - Now, power and/or heat generation are the limiting factors of the down-scaling

- Supply voltage reduction is becoming difficult, because Vth cannot be decreased any more, as described later.

- Growth rate in clock frequency and chip area becomes smaller.

9 2. ITRS Roadmap (for 22 nm CMOS logic)

10 What is a roadmap? What is ITRS? Roadmap: Prediction of future technologies ITRS: International Technology Roadmap for Semiconductors made by SIA (Semiconductor Industry Association with Collaboration with Japan, Europe, Korea and Taiwan)

100 1000 Gateゲート長 Gateゲート絶縁膜厚 length oxide 1992 1994 10 thickness 100 2001 1992 40nm 2003 1997 1994 1999 1999

EOTEOT [nm] [nm] 1.5nm 2001 1997 10 1 2003 2005 2005 Physical Gate Length [nm] [nm] Length Length Gate Gate Physical Physical

1 0.1 1995 2005 2015 1995 2005 2015 11 1992 -1997:NTRS (National Technology Roadmap) 1998 - : ITRS (International Technology Roadmap)

2008 ITRS update 2007 ITRS 2006 ITRS update ITRS Roadmap does change every year! 2007 Edition 2003 Edition 2006 Update 2002 Update 2005 Edition 2001 Edition 2004 Update 2000 Update

http://www.itrs.net/reports.html

13 HP, LOP, LSTP for Logic CMOS 100 e)

1 Operation Frequency (a.u.) Operation

Subthreshold Leakage (A/µm) Source: 2007 ITRS Winter Public Conf. 14 What does ‘45 nm’ mean in 45 nm CMOS Logic?

‘XX nm CMOS Technology ITRS (Likely in 2008 Update) Commercial Logic CMOS products for High Performance Logic Physical Technology Starting Year Half Pitch st Gate Length name Year (1 Metal) 45 nm 2007 2007 68 nm 32 nm 2008 59 nm 29 nm 32 nm 2009?2009 52 nm 27 nm 2010 45 nm 24 nm

‘XX nm’ CMOS Logic Technology: - In general, there is no common corresponding parameter with ‘XX nm’ in ITRS table, which stands for ‘XX nm’ CMOS.

15 What does ‘45 nm’ mean in 45 nm CMOS Logic? 8µm Æ 6µm Æ 4µm Æ 3µm Æ 2µm Æ 1.2µm Æ 0.8µm Æ 0.5µm - Originally, ‘XX’ means lithography resolution. - Thus, ‘XX’ was the gate length, and half pitch of lines - ‘XX’ had shrunk 0.7 in 3 years in average (0.5 in 6 years) those days.

Logic 1st Metal Half Pitch

16 What does ‘45 nm’ mean in 45 nm CMOS Logic?

Æ 350nm Æ 250nm Æ 180nm Æ 130nm Æ 90nm Æ 65nm Æ 45nm -‘XX’ values were established by NTRS* and ITRS with the term of ‘Technology Node**’ and ‘Cycle***’ using typical ‘half pitch value’.

- The gate length of logic CMOS became smaller with one or two generations from the half pitch, and ‘XX’ names ahead of generations have been used for logic CMOS. Resist Ashing

Resist

- Memory still keeps the half pitch as the value of ‘XX’

17 For example, Typical Half Pitches at ITRS 2007

Resist Ashing

Resist Source: 2008 ITRS Summer Public Conf. 18 Physical gate length in past ITRS was too aggressive. The dissociation from commercial product prediction will be adjusted. Physical gate length of High-Performance logic will shift by 3-5 yrs.

Correspond to 45nm 32nm 22nm Logic CMOS

X0.71 IT / 3 Y RS 2 ear 32nm 007 P 27nm rint L 22nm g 25 nm 2008 20n Updat m e Print 16nm Lg X0.71 / 3 Year 2008 Upda te Ph ys. Lg ITR X0.71 / 3.8 Year S 200 7 Phy 3 year shift s. Lg X0.71 / 3 Year

Source: 2008 ITRS Summer Public Conf. 19 EOT and Xj shift backward, corresponding to Lg shift

EOT: 0.55 nm Æ 0.88 nm, Xj: 8 nm Æ 11 nm @ 22nm CMOS

Likely in 2008 Update Correspond to 22nm Source: 2008/ ITRS Summer Public Conf.

Likely in 2008 Update

non-steady trend filled in for metal gate EOT for 2009/10 corrected based on latest conference presentations 20 What does ‘22 nm’ mean in 22 nm CMOS Logic?

Source: 2008 ITRS Summer Public Conf. From ITRS2008 Update, maybe XX nm stands for the physical Gate length

21 Clock frequency does not increase aggressively anymore. Even decreased! Advantage in SISC Era for ‘out of order’

Multi Core Advantage in RISC Clock ≠ Simple configuration Performance

Source: Mitsuo Saito, Toshiba 22 d? ue ITRS2007 tin on C ck lo y e C nc r ue Co eq Fr Chip ency Frequ Cell Broadband Engine 6GHz capability for SRAM

Source: IBM, Toshiba, Sony ISSCC2008 and 08

Source: 2007 ITRS Winter Public Conf. 23 Clock frequency Change in the past ITRS 01 (Max on chip frequency or ‘Core clock’) 20 S R IT 03 20 RS 5 IT 00 S2 R ar IT Ye %/ 15 ear 8%/Y

2007 ITRS

22 nm: Source: 2008 ITRS Summer Public Conf. 6 GHz? 24 Structure and technology innovation (ITRS 2007)

Source: 2008 ITRS Summer Public Conf. 25 Timing of CMOS innovations shifts backward. Bulk CMOS has longer life now!

Correspond to 22nm Logic CMOS

Bulk extends 4 years!

Multi G delays 4 years!

Source: 2008 ITRS Summer Public Conf.

26 Wafer size (ITRS 2007) Correspond to 22nm

Source: ITRS 2007 ?? Maybe delay??

27 ITRS2008 Low-k Roadmap Update

Correspond to 22nm Logic

ITRS 2007

Update 2008 ITRS 2007 Update 2007

Source: 2008 ITRS Summer Public Conf. k value increases by 0.1 ~ 0.3

28 Historical Transition of ITRS Low-k Roadmap

ITRS2003

ITRS2005 ITRS2007,8

ITRS2001

ITRS1999

Source: 2008 ITRS Summer Public Conf. 29 Roadmap towards 22nm technology and beyond

- Physical gate length downsizing rate will be less aggressive.

- Corresponding to the above, performance increase would slow down – Clock frequency, etc.

- Introduction of innovative structures – UTB SOI and DG delayed, and bulk CMOS has longer life than predicted by previous ITRS roadmaps.

30 3. Voltage Scaling / Low Power and Leakage

31 Difficulty in Down-scaling of Supply Voltage: Vdd

Because, Vth cannot V be down-scaled anymore, d d Vdd down-scaling is difficult.

Vdd –Vth determines the performance (High Id) and cannot be too small.

Volt V th

∆Vth: Vth variation

> ∆Vth Subthreshold leakage current limit Margin for Vth variation Year is necessary 32 Subtheshold leakage current of MOSFET

Id Subthreshold Current Ion Is OK at Single Tr. level

OFF ON But not OK For Billions of Trs. Subthreshould Leakage Current Ioff Vg Vg=0V Subthreshold Vth region (Threshold Voltage) 33 Vth cannot be decreased anymore Log scale Id plot

-3

Ion m) 10 A µ 10-4A significant Ioff increase 10-5A Vdd Ioff 10-6A down-scaling Vth: 300mV Æ 100mV 10-7A Ioff increases Vdd=0.5V with 3.3 decades 10-8A Vdd=1.5V (300 – 100)mV/(60mv/dec) Vth 10-9A = 3.3 dec Ioff down-scaling -10

Log Id per unit gate width (= 1 10 A Vth = 300mV Vg (V) Subthreshold slope (SS) Vth = (Ln10)(kT/q)(Cox+CD+Cit)/Cox = 100mV > ~ 60 mV/decade at RT Vg = 0V SS value: Constant and does not become small with down-scaling 34 ITRS for HP logic Ion/Ioff ratio

1.0E+9 2008up (bulk) 2008up (UTB) 2008up (DG) 2007 (bulk) 1.0E+8 2007 (UTB) 1999 2007 (DG) 2005 (bulk) 2005 (UTB) 1.0E+7 2005 (DG) 2003 2001 1999 1.0E+6 2 0 0 1.0E+5 1 2005 DG Others Ion/Ioff ratio 1.0E+4 2003-2008

1.0E+3 2004 2007 2010 2013 2016 2019 2022

Source: ITRS and 2008 Values are from ITRS Public Conf. 2008 ITRS Summer Public Conf. Year and still under discussion 35 ITRS for HP logic Vth-sat will be Vdd will stay higher Saturated Vdd around 0.1V in 2008 update Vth 2008up (bulk) 2008up (UTB) 2008up (DG) 2008 2007 (bulk) 2007 (UTB) 20 2007 (DG) 1.2 0 3 0.4 2005 (bulk) 1 , 2 9 00 2005 (UTB) 9 5 2005 (DG) 1 9 , 0.35 20 3 07 200 G 2003 (bulk) 0.3 2005 D 0.8 2008up (bulk) 20 2008up (UTB) 0.25 01 2008up (DG) 2005 UTB 0.6 2007 (bulk) 0.2 Vdd (V) 2007 (UTB) (V) Vth 0.4 2007 (DG) 0.15 2005 (bulk) 2 2005 (UTB) 0.1 00 5 B 0.2 2005 (DG) lk 2007, 2008 2003 0.05 2001 0 1999 0 2004 2007 2010 2013 2016 20192004 2022 2007 2010 2013 2016 2019 2022 2008 Values are from ITRS Public Conf. Year Source: ITRS and Year and still under discussion 2008 ITRS Summer Public Conf. 36 ITRS for HP logic 2008 Values are from ITRS Public Conf. and still under discussion Vth-sat / Vdd

0.4 2008up (bulk) 2008up (UTB) 2008up (DG) 0.35 2007 (bulk) 2003 2007 (UTB) 0.3 2007 (DG) 2005 (bulk) 0.25 2005 (UTB) 2005 (DG) 2005 2003 (bulk) 2007 0.2

0.15 Vth/Vdd 0.1 2008 0.05

0 2004 2007 2010 2013 2016 2019 2022 Year

Source: ITRS and 2008 ITRS Summer Public Conf. 37 Improper down-scaling Metal gate Interfacial C (Quantum eff) High-k oxd Could we squeeze technologies Inversion C for ultimate CMOS scaling? Si (Quantum eff) Saturation of EOT thinning is a serious Interfacial C roadblock to proper down-scaling. @Metal gate and 1.2 2008up (bulk) 2008up (UTB) Gate oxd. 2008up (DG) (EOT=0.2~0.3nm?) 2007 (bulk) 2007 (UTB) C 1 2007 (DG) 1 2005 (bulk) Gate Oxd C 2005 (UTB) 2005 (DG) C2 2003 (bulk) 0.8 2001 1999 C3 Inversion C

EOT (nm) (EOT=0.3~0.5nm?) for HP Logic 0.6

EOT(C1) + EOT(C3) > 0.5nm Small effect to decrease 0.4 2004 2007 2010 2013 2016 2019 2022 EOT(C2) beyond 0.5nm? Year Delay Is 0.5nm real limit? Saturation 38 EOT<0.5nm with Gain in Drive Current is Possible

La2O3 gate insulator (a) EOT=0.37nm**(b) EOT=0.43nm ** (c) EOT=0.48nm 3.5 Vth=-0.04V Vth=-0.03V Vth=-0.02V 3 W/L=2.5/50µm PMA 300oC (30min) 4%up 14%up

Drain current (mA) current Drain 0 insufficient compensation region* 00.20.40.6 0.8 1 00.20.40.6 0.8 1 000.20.4 0.2 0.4 0.60.6 0.8 0.8 1 1 0 0.2Drain 0.4 voltage 0.6 0.8 (V) 1 0 0.2Drain 0.4 voltage 0.6 0.8 (V) 1 Drain voltage (V) 0.3 34%up EOT scaling below 0.5nm EOT=0.37nm EOT=0.43nm 0.2 Still useful for larger drain current Source: K. Kakushima, K. Okamoto, K. Tachi, P. Ahmet, K. Tsutsui, N.i Sugii, 0.1 T. Hattori, and H. Iwai, IWDTF 2008, Tokyo, November, 2008 EOT=0.48nm Because Lg is very large (2.5µm), gate leakage is large in case (a). The gate leakage Drain current (mA) Vd=50mV * component was subtracted from measured data for case (a). However, if we make small 0.0 gate length, the gate leakage current should become sufficiently small to be ignored -0.4 0 0.4 0.8 1.2 compared with Id as we verified with SiO2 gate before (Momose et al.,IEDM 1994). The gate leakage could be suppressed by modifying material and process in future. Gate voltage (V) ** Estimated by Id value 39 Thus, in future, maybe continuous development of new techniques could make more proper down- scaling possible. It is difficult to say, but EOT and Vdd may become smaller than expected today.

40 Random Variability Reduction Scenario in ITRS 2007 Vth σ Normalized Normalized

Source: 2007 ITRS Winter Public Conf. 41 4. SRAM cell scaling

42 Intel’s SRAM test chip trend SRAM down-scaling trend Source: B. Krzanich, S. Natrajan, Intel Developer’s Forum 2007 has been kept until 32nm http://download.intel.com/pressroom/kits/events/idffall_2007/Briefing Silicon&TechManufacturing.pdf and probably so to 22nm 10 Process Lithography 1st production 180nm name 0 ))) .

222 5 130nm X mmm e

P1264 65nm 2005 µµµ ve ry 90nm 2 P1266 45nm 2007 1 ye a 65nm rs P1268 32nm 2009 45nm Cell area Cell area Cell area ((( P1270 22nm 2011 32nm 0.1 Only schedule has been published 1995 2000 2005 2010 Year

Technology 90 nm Process 65 nm Process 45 nm Process 32 nm Process Cell size 1.0 µm2cell 0.57 µm2cell 0.346 µm2cell 0.182 µm2cell Capacity 50 Mbit 70 Mbit 153 Mbit 291 Mbit Chip area 109 mm2 110 mm2 119 mm2 118 mm2 Functional Si February ‘02 April ‘04 January ‘06 September ‘07 43 22 nm technology 6T SRAM Cell: Size = 0.1µm Source: http://www-03.ibm.com/press/us/en/ pressrelease/24942.wss Static noise margin Announced on Aug 18, 2008 of 220 mV at 0.9 V Consortium: IBM (NYSE) , AMD, Freescale, STMicroelectronics, Toshiba and the College of Nanoscale Science and Engineering (CNSE) 0.1µm cell size is almost on the down-scaling trend New technologies introduced - High-NA immersion lithography - High-K metal gate stacks - 25 nm gate lengths - Thin composite oxide-nitride spacers - Advanced activation techniques - Extremely thin silicide - Damascene copper contacts Source: IEDM2008 Pre-conference Publicity http://www.btbmarketing.com/iedm/ 44 Cell size reduction trends Intel 1/2 or 2/3 per cycle? Functional Si 65nm Apr.2004 1 45nm Jan.2006 ) 2 0.57µm2 32nm Sep.2007 m

µ 2 TSMC 0.5 I 0.35µm nt el Conference (IEDM) 45nm Dec.2007 2 0.24µm 0.18µm2 32nm Dec.2007

Cell area ( Cell area 1 T 0.2 /2 S p M 2 IBM Alliance e 2 C 0.15µm r /3 I c p BM (Consortium) y e A c r c ll 0.1µm2 0.1 le y ian Conference (IEDM) cle ce 32nm Dec.2007 65nm 45nm 32nm 22nm Press release 22nm Aug.2008 45 NMOS Mismatch Coefficient (C2) improvement with technology scaling

Normalized to 180nm 2

Source: K.J.Kuhn IEDM 2007 46 Mismatch improvement “tall” design by layout (Intel) 90nm :1.0 µm2

“wide” design 65nm : 0.57 µm2

Source: K. J. Kuhn IEDM2007 Tech. Dig. pp.471

“wide” design (Square endcaps) 45nm 0.346 µm2 47 Double patterning for square endcap Cell evolution is similar

TSMC 32nm TSMC 45nm IEDM 2007 IEDM 2007

IBM Alliance 32nm Source: M. Bohr, ICSICT2008 IEDM 2004 IBM Alliance 22nmIEDM 2008

TSMC 32nm TSMC 45nm IBM Gr. 32nm 48 Most Difficult part of SRAM down-scaling is Vdd down-scaling

Density of on-chip cache SRAM memory is high and thus, Vth cannot be down-scaled too much because of large Isd-leak

Also, under low Vdd, read- and write margin degrades, data retention degrade.

Thus, Vdd down-scaling is more severe in SRAM than logic part of the circuits

49 Intel® Xeon® 7400 Series (Dunnington)

45 nm high-k6 cores 16MB shared L3 cache

Source: Intel Developer Forum 2008 Cache occupies huge area Æ Cell size of SRAM should be minimized Æ Isd-leak should be minimized Æ Vth are often designed to be higher than Min. logic Vth Æ Lg are often designed to be larger than Min. logic Lg

50 Nehalem(Intel) 2,4 or 8 Cores Voltage/Frequency Partitioning DDR Vcc Core Vcc Chip Uncore Vcc Dynamic Power Management

8T SRAMCell 32kB L1 I -cache 32kB L1 D-cache Core 256kB L2 -cache 6T SRAMCell 8 MB L3 cache Source: Intel Developer Forum 2008 51 6T and 8T Cell

6T Cell Cell size is small For high density use

Add separate read function 8T Cell Cell size increase 30% For low voltage use Source: Morita et. al, Symp. on VLSI Circ. 2007

52 5. Roadmap for further future as a Personal View

53 -There will be still 4~6 cycles (or technology generations) left until we reach 11 ~ 5.5 nm technologies, at which we will reach down- scaling limit, in some year between 2020-30 (H. Iwai, IWJT2008). -Even After reaching the down-scaling limit, we could still continue R & D, seeking sufficiently higher Id-sat under low Vdd. -Two candidates have emerged for R & D 1. Nanowire/tube MOSFETs 2. Alternative channel MOSFETs (III-V, Ge) - Other Beyond CMOS devices are still in the cloud.

5.5nm?*

3 important innovations ITRS figure edited by Iwai

Source: 2008 ITRS Summer Public Conf. *5.5nm? was added by Iwai 54 Si nanowire FET with Semi-1D Ballistic Transport Merit of Si-nanowire 0 Reduction in Ioff (Isd-leak) Source: Y. Lee., T. Nagata., K. Kakushima., Good control of K. Shiraishi, and H. Iwai, IWDTF 2008, Tokyo, November, 2008 Isd-leak by Trade off surrounding gate Carrier scattering probability Small Large Increase in Ion (Id-sat) # of quantum channel Small Large

High Conduction (1D) Go=77.8µS/wire Multiple quantum channel High-density lateral (QC) used for conduction and vertical integration Source: T. Ohno, K. Shiraishi, and T. Ogawa, Phys. Rev. Lett. ,1992 55 Our roadmap for R &D Current Issues Source: H. Iwai, IWJT 2008 Si Nanowire Control of wire surface property Source Drain contact Optimization of wire diameter Compact I-V model III-V & Ge Nanowire High-k gate insulator Wire formation technique CNT: Growth and integration of CNT Width and Chirality control Chirality determines conduction types: metal or semiconductor Graphene: Graphene formation technique Suppression of off-current Very small bandgap or no bandgap (semi-metal) Control of ribbon edge structure which affects bandgap 56 Long term roadmap for developmentWe do know system and Source: H. Iwai, IPFA 2006 algorithms are important!

New Materials, New Process, New Structure（Logic,But Memory) do not know how it can

Hybrid integration of different functional Chipbe by us for use of bio?

(Gate length etc） length (Gate Increase of SOC functionality

3D integration of memory cell

Size 3D integration of logic devices

Miniaturization of Interconnects on ＰＣＢ (Printed Circuit Board)

Low cost for LSI process Revolution for ＣＲ，Equipment, Wafer

Introduction of algorithm of bio-system Brain of insects, human

5 nm? Saturation of Downsizing

We do not know how?

After 2050? Some time in 2020 - 2030 57 Acknowledgement I would like to express deep appreciation to the following people for the useful advice and support for material preparation. Special thanks to ITRS committee for the permission to refer roadmap and Public conference. ITRS Committee: Hidemi Ishiuchi (Toshiba), Paolo Gargini (Intel)

Toshiba Corporation: Mitsuo Saito, Yukihiro Urakawa, Tomoaki Yabe

Tsukuba University: Kenji Shiraishi, Kenji Natori

Intel Corporation: Mark Bohr

IBM Alliance : B.S. Haran et al,

Tokyo Institute of Technology: Kuniyuki Kaukshima, Parhat Ahmet, Takamasa Kawanago, Yeonghun Lee 58 Thank you for your attention!