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(12) United States Patent (10) Patent N0.: US 7,326,969 B1 Horch (45) Date of Patent: Feb US007326969B1 (12) United States Patent (10) Patent N0.: US 7,326,969 B1 Horch (45) Date of Patent: Feb. 5, 2008 (54) SEMICONDUCTOR DEVICE Tomohisa MiZuno, et a1; Novel SOI p-Channel MoSFETs With INCORPORATING THYRISTOR-BASED Higher Strain in Si Channel Using Double SiGe Heterostructures; MEMORY AND STRAINED SILICON IEEE Trans. on Electron Dev., vol. 49, No. 1, Jan. 2002. J. Welser, et a1, NMOS and PMOS Transistors Fabricated in (75) Inventor: Andrew E. Horch, Seattle, WA (US) Strained Silicon/Relaxed Silicon-Germanium Structures; IEDM 92; pp. 1000-1002. (73) Assignee: T-RAM Semiconductor, Inc., Milpitas, S. Nakamura, et a1; Giga-bit DRAM cells With low capacitance and low resistance bit-lines on buried MOSFET’s and . ; IEEE 1995, CA (US) IEDM 95, pp. 889-892. T. MiZuno, et al; Electron and Hole Mobility Enhancement in ( * ) Notice: Subject to any disclaimer, the term of this Strained-Si MOSFET’s on . ; IEEE Electron Device Letters, vol. patent is extended or adjusted under 35 21, No. 5, May 2000; pp. 230-232. U.S.C. 154(b) by 235 days. Kern (Ken) Rim, et al; Fabrication and Analysis of Deep Submicron Strained-Si N-MOSFET’s; IEEE Transactions on Electron Devices, (21) Appl. No.: 11/004,712 vol. 47, No. 7, Jul. 2000; pp. 1406-1415. (22) Filed: Dec. 2, 2004 (Continued) Primary ExamineriMattheW E. Warren (51) Int. Cl. (74) Attorney, Agent, or F irmiFields IP, PS H01L 29/423 (2006.01) (52) US. Cl. .................... .. 257/133; 257/140; 257/146; (57) ABSTRACT 257/616; 257/E27.079; 257/E27.193 (58) Field of Classi?cation Search .............. .. 257/133, A semiconductor memory device may comprise a thyristor 257/140, 146, 616, E27.079, E27.193 See application ?le for complete search history. based memory having some portions formed in strained silicon, and other portions formed in relaxed silicon. In a (56) References Cited further embodiment, a thyristor in the thyristor-based memory may be formed in a region of relaxed silicon U.S. PATENT DOCUMENTS germanium, While an access device to the thyristor-based 6,229,161 B1 5/2001 Nemati et al. memory may have a body region incorporating a portion of 6,812,504 B2* 11/2004 Bhattacharyya ........... .. 257/133 a layer of strained silicon. In yet a further embodiment, 6,960,781 B2 * 11/2005 Currie et al. ............... .. 257/19 different regions of the thyristor may be formed in vertical aligned relationship relative to an upper surface of the OTHER PUBLICATIONS relaxed silicon germanium. For this embodiment, the thy U.S.App1. No. 10/671,201. ristor may be formed substantially Within the depth of the Yun-Gi Kim, et a1; Chip Level Reliability on SOI Embedded relaxed silicon germanium layer. In a method of forming the Memory; Proceedings 1998 IEEE International SOI Conference, semiconductor device, relaxed silicon may be deposited Oct. 1998; pp. 135 and 136. over exposed regions of a silicon substrate, and a thin layer Thomas A. Langdo, Strained silicon on SOI substrates adds up; EE of strained silicon formed over a portion of the substrate Times, Nov. 14, 2002; 3 pages. having silicon germanium. IBM, IBM’s Strained Silicon Breakthrough; Image Page, http:// wwwresearch.ibm.com/resources/press/strainedsilicon/; Announcement Jun. 8, 2001; 3 pages. 19 Claims, 32 Drawing Sheets / 200 237 229 235 235 227 $237 38 233 ' 235 ' 235 ~ r r l —._l r‘ -— 233 238 233 231 N £5. E & E 253 251 225 | 221 | | US 7,326,969 B1 Page 2 OTHER PUBLICATIONS Chien-Hao Chen, et al; Stress MemoriZation Technique (SMT) by Selectively Strained-Nitride . Device Application; 2004 Sympo Scott E. Thompson, et al, A 90-nm Logic Technology Featuring sium on VLSI Tech. Digest . ; 2004 IEEE; 2 pages. Strained-Silicon, IEEE Transactions on Electron Devices, vol. 51, A. ShimiZu, et al.; Local Mechanical-Stress Control (LMC): ANeW No. 11, Nov. 2004; pp. 1790-1797. Technique for CMOS-Performance Enhancement; 2001 IEEE; 4 Fu-Liang Yang, et al., A 65nm Node Strained SOI Technology With pages. Slim Spacer, 2003 IEEE, 4 pages. Y.M. Sheu, Impact of STI Mechanical Stress in Highly Scaled K. Rim, et al.; Fabrication and Mobility Characteristics of Ultra-thin MOSFETs; 2003 IEEE; 4 pages. Strained Si Directly on Insulator (SSDOI) MOSFETs; 2003 IEEE; David Lammers; Materials transitions stalk CMOS scaling; EE 4 pages. Times, Jun. 17, 2002; WWW.commsdesign.com; 4 pages. T. Ghani, et al.; A 90 nm High Volume Manufacturing Logic Peter Weiss; Straining for Speed; In search of faster electronics, chip Technology Featuring Novel 45 nm Gate Length strained . makers contort silicon crystals; Science NeWs Online; vol. 165, No. Transistors; IEDM 2003; pp. l-l8 (PoWerPoint presentation). 9; Wk. of Feb. 28, 2004; 8 pages. T. Ghani, et al.; A 90 nm High Volume Manufacturing Logic HoWard Huff; A perspective on enhancing mobilities; Solid State Technology Featuring Novel 45 nm Gate Length Strained Silicon Technology; Jan. 2004; 4 pages. CMOS Transistors; 2003 IEEE; 3 pages. David Lammers; Intel, TI ‘straining’ to improve 90-nm silicon; EE Celeste Biever, Secret of ‘strained silicon’ chips revealed; WWW. Times; Oct. 24, 2003; 2 pages. neWscientist.com; Dec. 20, 2003; 2 pages. Shin-Ichi Takagi; Strained Silicon Technology; short course at K. Ota, et al.; Novel Locally Strained Channel Technique for High International Electron Devices Meeting (IEDM) on Dec. 7, 2003; 74 Performance 55nm CMOS; 2002 IEEE; 4 pages. pages. C.-H. Ge, et al.; Process-Strained Si (PSS) CMOS Technology Featuring 3D Strain Engineering; 2003 IEEE; 4 pages. * cited by examiner U.S. Patent Feb. 5, 2008 Sheet 1 0f 32 US 7,326,969 B1 101A FIG. 1A U.S. Patent Feb. 5, 2008 Sheet 2 0f 32 US 7,326,969 B1 117 FIG. 1B U.S. Patent Feb. 5, 2008 Sheet 3 0f 32 US 7,326,969 B1 200 239 235227 J38 ' '235 251 253 FIG.2 229 253' U.S. Patent Feb. 5, 2008 Sheet 4 0f 32 US 7,326,969 B1 13 2m189m mdlm.QMxl‘mmlw Pmw/< mL % %Emu a .5 ?nk \.l U.S. Patent Feb. 5, 2008 Sheet 7 0f 32 US 7,326,969 B1 F 600 231 — (‘V650 .221 FIG. 6A f‘ 600 679 w \_/~\ /_~/ 677 gal 221 FIG. 6B U.S. Patent Feb. 5, 2008 Sheet 8 0f 32 US 7,326,969 B1 K- 600 679 V; 683 / ' /-\./ 677 git m FIG. 6C [- 600 679 V, 621 P" 683 12.1. FIG. 6D U.S. Patent Feb. 5, 2008 Sheet 9 0f 32 US 7,326,969 B1 K- 600 683 679 ) \f K ’ Q1 677 2__1_ 221 FIG. 6E K- 600 683 K g 231 FIG. 6F U.S. Patent Feb. 5, 2008 Sheet 10 0f 32 US 7,326,969 B1 r 600 691 693 A A f \ f “ 683) r~J233 ( @ 2_3_1 221 FIG. 66 f 700 673“ 677/“ Q Q FIG. 7A U.S. Patent Feb. 5, 2008 Sheet 11 0f 32 US 7,326,969 B1 s79\g _/679 677/ m _ "\677 Lil ‘ 7 u .221 FIG. 7B 679 \ ) N w INN ._L FIG. 7C U.S. Patent Feb. 5, 2008 Sheet 13 0f 32 US 7,326,969 B1 —l_ 231 m izl @ FIG. 7F '/ 700 233 I1 |._ 231 E 6A A FIG. 76 U.S. Patent Feb. 5, 2008 Sheet 14 0f 32 US 7,326,969 B1 F 800 683 3 .621 a 7 A FIG. 8A F 800 $3 2 1' i 721A FIG. 8B U.S. Patent Feb. 5, 2008 Sheet 16 6f 32 US 7,326,969 B1 ‘ 683A f 800E 683B _31 Q1 } 886 22; 885 721 B FIG. 8E K- 800F 893 \‘ K- 891 233 I/ 6838 531 B 621 B } 886 a 885 721 B FIG. 8F U.S. Patent Feb. 5, 2008 Sheet 18 0f 32 US 7,326,969 B1 mam ll-Il' \ 8w 9E / cow 9%gm \v\l|| / 6w RNSNFL < {My?/j.@?m/<;\\§A“ININ. NJ\W/A \f>0% mlw. nowEN /,JH. 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