Strained Silicon Technology
Tejas Krishnamohan ([email protected]) Prof. Krishna Saraswat ([email protected])
Department of Electrical Engineering Stanford University, Stanford CA 94305 What is strain? - Types of loading
Tensile Compressive Shear Torsion For tensile and compressive strain Stress and strain: Positive for tensile loads Negative for compressive loads What is strain? – Hooke’s Law
E Elastic strain is reversible Plastic strain is irreversible What is strain? – Poisson’s Ratio
Elastic constants Young’s Poisson’s Material Modulus Ratio (GPa) Si [100] 130 0.28 Ge[100] 103 0.26 C 1000 0.1 SiC 748 0.18 GaAs 86 0.31 InAs 51.4 0.35 SiO2 94 Al 64
Typically, Cu 124 High Young’s modulus Low Poisson’s ratio W 406 Strained Silicon - Introduction
Transistor scaling: Mobility MOSFET Source Injection
Source-Barrier 1000 -0.3 11 E to x =35 Å eff r to x =70 Å 500 ≈ k T/q Electron B )
s 300 - V /
2 200 -0.3 m E c
eff
( -2
E
eff f
f
e 100 Hole µ Drive Current & Gate Delay: -1 50 Eeff 1− r 1 µm CMOS 0.1 µm CMOS = − 30 I D /W Cox (VG VT )vT 0.1 0.2 0.3 0.5 1 2 3 1+ r E e f f (MV/cm) L ×V CLOADVDD = gate DD ( − )× Mobility degrades with transistor scaling I D VDD VT vinj - Universal mobility model ν - Ionized impurity scattering Lower transport mass Higher inj , µ Lundstrom, IEEE EDL, June 2001 pp.293 Strained Silicon - Introduction
Strain enhanced mobility • Effective mass desired – Small mass in the transport direction (high mobility) – Large mass in the transverse direction (large density of states) • Population of sub-bands is an important consideration – Quantum confinement (high field, ultra-thin channel) may cause carriers to populate sub- bands with different effective mass Biaxial strain – Strain changes band structure and band splitting • Fermi velocity, injection velocity
Source: Intel Corp.
S. Takagi, “Re-examination of subband structure engineering in ultra-short channel MOSFETs under ballistic carrier transport,” Symp. VLSI Tech., pp. 115 – 116 (2003). Strained Silicon – Biaxial strain Si and SiGe crystal structures
Source: J. Hoyt, MIT Strained Silicon – Biaxial strain Effect of biaxial strain on Si energy bands
Source: J. Hoyt, MIT Strained Silicon – Biaxial strain Device structures ¤ ¤ § § ¤ ¤ ¤ ¤ § § ¤ ¤ ¤ ¤ § § ¤ ¤ ¤ ¤ § § ¤ ¤ ¤ ¤ § § ¤ ¤ ¤ ¤ § § ¤ ¤ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¢£ ¢£ ¥¦ ¥¦ ¢£ ¢£ ¥¦ ¥¦ ¢£ ¢£ ¥¦ ¥¦ ¢£ ¢£ ¥¦ ¥¦ ¢£ ¢£ ¥¦ ¥¦ ¢£ ¢£ ¥¦ ¥¦ © © § § ¤ ¤ © © § § ¤ ¤ ¨ ¨ ¨ ¨ ¦ ¦ £ £ ¦ ¦ ¦ ¦ ¦ ¦ £ £ ¦ ¦ ¦ ¦ ¤ ¤ § § ¤ ¤ § § © © § § ¤ ¤ ¤ ¤ § § ¤ ¤ § § © © § § ¤ ¤ ¨ ¨ ¨ ¨ ¢ ¢ ¦ ¦ ¦ ¦ ¦ ¦ £ £ ¦ ¦ ¦ ¦ ¢ ¢ ¦ ¦ ¦ ¦ ¦ ¦ £ £ ¦ ¦ ¦ ¦ ¤ ¤ § § ¤ ¤ § § ¤ ¤ § § ¤ ¤ § § ¢ ¢ ¦ ¦ ¦ ¦ ¢ ¢ ¦ ¦ ¦ ¦ ( + 2 - - 4 ) 5 6 ' 7 + 4 8 ' 4 1 0 + 9 - , : ) 5 ' 0
CoSi2 on RSD Strained ! # " % silicon $ 60nm + , / - , - ) 1 ' 0 3 ( 2 ) 1 1 ' SiGe ( + & , -. ' ) ' ' * Buried oxide K. Rim et al., Symp. VLSI Tech., p. 59, 2001. K. Rim et al., Symp. VLSI Tech., p. 98, 2002. B. Lee et al., IEDM 2002 K. Rim et al., IEDM, 2003. Enabling technology – grow strained Si on relaxed SiGe Strained Silicon – Biaxial strain Strain-dependence of mobility
Strain = (aStr.Si-aSi)/aSi (%) 0.0 0.5 1.0 1.5 2.0 2.5 -2 rrrr N = 1e13 cm oooo inv tttt -3 cccc
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0 10 20 30 40 50 Equivalent [Ge] in Fully Relaxed SiGe (%)
Mobility enhancements consistent with amount of strain even for strained silicon on insulator
K. Rim et al., IEDM, 2003. Strained Silicon – Why Uniaxial? Studied extensively but…two key problems
1) Integration difficulties - Dislocations - Ge up-diffusion - Fast diffusion of extensions 2) Poor hole mobility gain - Cost - At high Eeff LH-HH separation is reduced - Hole mobility gain is lost Source: Intel Corp. Strained Silicon – Uniaxial strain Why uniaxial? Piezoresistance calculations
Biaxial strain C. S. Smith, Phys. Rev. 1954
High hole mobility at high Eeff - Effective mass reduction (band warping) - Increased band splitting - Band separation is not reduced at high
Eeff (high quantization effective mass for light holes) Source: Intel Corp. S. E. Thompson, IEDM Tech. Dig., 2004. Strained Silicon – Uniaxial strain
Choosing the right strain orientation
Traditional PMOS NMOS
C.-H Ge, IEDM December 2003 Strained Silicon – Uniaxial strain Device Technology Traditional Approach Intel’s Technology
Processed induced strain Source: Intel Corp. Strained Silicon – Uniaxial strain Stress distribution
PMOS stress distribution NMOS stress distribution - SiGe S-D compresses channel - Tensile nitride cap stretches the - Average channel stress along channel the channel (~500MPa) - Two components of stress
- SiGe also improves Rext induced by the nitride cap
Source: Intel Corp. Strained Silicon – Uniaxial strain Stress scaling
PMOS stress increases as NMOS stress increases as SiGe % is increased and as the capping layer thickness channel length decreases is increased
Source: Intel Corp. Strained Silicon – Uniaxial strain Transistor performance
PMOS NMOS - Drive current of 0.72mA/micron is - Drive current of 1.26mA/micron obtained is obtained - 30% gain from strain enhanced - 10% gain from tensile strain mobility - At 1.2V and 40nA/micron off- - At 1.2V and 40nA/micron off- state leakage state leakage
Source: Intel Corp. Strained Silicon – Process induced strain Stressor films and liners
Dual stress liner for SOI
H. S. Yang et al., IEDM Tech. Dig., 2004. Strained Silicon – Process induced strain Stress scaling in stressor films and liners
PMOSFET
• Strain/stress increases with shorter gate length • Current drive improvement decreases at short gate lengths – attributed to increased halo doping
H. S. Yang et al., IEDM Tech. Dig., 2004. Strained Silicon – Process induced strain Gate induced stress
• Built-in stress in FUSI gates, metal gates, and metal oxides. • Implants in the gate create large built-in stress that can be kept depending
on annealing process (N2 ~ -150MPa, P ~ - 450MPa, Ge ~ - 500MPa). Gate stress for Extremely Thin-SOI Source: AMD Corp. Strained Silicon – Process induced strain Which is best?
Source: Synopsys, AMD Corp.