Rochester Institute of Technology RIT Scholar Works
Theses
2007
Design and simulation of strained-Si/strained-SiGe dual channel hetero-structure MOSFETs
Puneet Goyal
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Recommended Citation Goyal, Puneet, "Design and simulation of strained-Si/strained-SiGe dual channel hetero-structure MOSFETs" (2007). Thesis. Rochester Institute of Technology. Accessed from
This Thesis is brought to you for free and open access by RIT Scholar Works. It has been accepted for inclusion in Theses by an authorized administrator of RIT Scholar Works. For more information, please contact [email protected]. Design and Simulation of Strained-Si/Strained-SiGe Dual Channel Hetero-structure MOSFETs By
Puneet Goyal
A Thesis Submitted
in Partial Fulfillment
of the Requirements for the Degree of
Master of Science
in Electrical Engineering
Approved by:
Professor Dr. James E. Moon (Thesis Advisor) Professor Dr. P.R. Mukund (Thesis Committee Member) Professor Dr. Santosh K. Kurinec (Thesis Committee Member)
Professor Dr. Vincent Amuso (Department Chair)
DEPARTMENT OF ELECTRICAL ENGINEERING
COLLEGE OF ENGINEERING
ROCHESTER INSTITUTE OF TECHNOLOGY
ROCHESTER, NEW YORK
OCTOBER, 2007
Copyright by Puneet Goyal, 2007
All Rights Reserved
ii Thesis/Dissertation Author Permission Statement Form
Title of thesis or dissertation : Design and Simulation of Strained Si/Strained SiGe Dual Channel Heterostructure MOSFETs______Name of author: Puneet Goyal______Degree: Master of Science______Program: Electrical Engineering______ College: Kate Gleason College of Engineering______ I understand that I must submit a print copy of my thesis or dissertation to the RIT Archives, per current RIT guidelines for the completion of my degree. I hereby grant to the Rochester Institute of Technology and its agents the non exclusive license to archive and make accessible my thesis or dissertation in whole or in part in all forms of media in perpetuity. I retain all other ownership rights to the copyright of the thesis or dissertation. I also retain the right to use in future works (such as articles or books) all or part of this thesis or dissertation.
Print Reproduction Permission Granted: I, Puneet Goyal , hereby grant permission to the Rochester Institute Technology to reproduce my print thesis or dissertation in whole or in part. Any reproduction will not be for commercial use or profit. Signature of Author: ______ Date: ______
Inclusion in the RIT Digital Media Library Electronic Thesis & Dissertation (ETD) Archive I, Puneet Goyal , additionally grant to the Rochester Institute of Technology Digital Media Library (RIT DML) the non exclusive license to archive and provide electronic access to my thesis or dissertation in whole or in part in all forms of media in perpetuity. I understand that my work, in addition to its bibliographic record and abstract, will be available to the world wide community of scholars and researchers through the RIT DML. I retain all other ownership rights to the copyright of the thesis or dissertation. I also retain the right to use in future works (such as articles or books) all or part of this thesis or dissertation. I am aware that the Rochester Institute of Technology does not require registration of copyright for ETDs. I hereby certify that, if appropriate, I have obtained and attached written permission statements from the owners of each third party copyrighted matter to be included in my thesis or dissertation. I certify that the version I submitted is the same as that approved by my committee. Signature of Author: ______ Date: ______
iii Acknowledgement It is my extreme pleasure to thank my thesis and academic advisor Dr. James Moon for his able guidance, enthusiastic supervision, inspiring support and having faith in my work during all the stages of research and thesis work. It was in his class of Advance Field Effect Device, that I learned the basics of CMOS device theory which became the foundation stone of this research work.
Same thing is true for Dr. Santosh Kurinec. It was in her class of Nanoscale Devices , where for first time I learnt about the state of the art strained silicon technology and exploratory devices in CMOS transistor technology. It was her continuum effort and motivation which inspired me to conduct research on strained silicon devices.
I would also like to thank my committee member, Dr. P.R. Mukund for his precious time in reviewing this manuscript and providing me a valuable feedback.
This research work was also possible due to generous support of Advanced Micro Devices, Austin Texas , where I interned as a process development engineer for strained Si devices. I would like to specially thank my managers Dr. Edward Ehrichs, Belinda Hannon, Amado Ramirez, and Vassil Papageorgiouv, and my mentor Karol Finfando and Ashwin Chincoli all of process development team at AMD for their excellent guidance and series of meaningful discussion which enriched and added meaning to my thesis work . I would also like to thank Dr. Syed Islam for his expert support and guidance in learning and developing skills with advance modeling and simulation techniques and especially using advanced simulation tools which is the backbone of this work.
A special thanks to Dr. Amitava Das Gupta of IIT Madras , India for providing us the details about the compact models used in this work for validation.
This work was a team effort and success of this work would not have been possible without help from Shrinivas Pandharpure, Gaurav Thareja (PhD. Student Stanford University ), Kunal
iv Rohilla, Sankha Mukherjee, Michael Latham. I really cannot imagine my research without their support, valuable discussion during each stage of the research work. I am also thankful to all my friends, my roommates for providing me a joyful and learning environment at both graduate office and back at home and for the support during the stage of this project.
I am also grateful to Electrical Engineering Staff members: Mr Ken Snyder, Patti Vicari, and James Stefano for providing me excellent technical support for this work.
A special thanks to Intel’s reliability team at Hillsboro, Oregon and Dr. Joe Watts and Dr. Scott Springer all of IBM Semiconductor Research and Development Center (SRDC) Burlington VT for providing me a valuable feedback and suggestions for this work during the series of interview presentations. In addition, I would like to acknowledge Dr. Zhiyuan (Charles) Cheng of AmberWave Systems Corporation for initiating strained silicon activities at RIT.
I would like to thank my parents, my brother for having faith in me and above all the almighty GOD who has been always with me at every stage of life.
I would like to express my appreciation to Silavco/Simucad Corporation for donating TCAD and EDA Omni licenses to Professor Sean Rommel for the Department of Microelectronic Engineering that provided me the necessary support and software required for this work.
This project was partially funded by the National Science Foundation through grant no. # EEC 0530575.
v Dedication
Dedicated to my parents, brother,
&
Above all
The Almighty GOD.
vi
ABSTRACT With a unified physics based model linking MOSFET performance to carrier mobility and drive current, it is shown that nearly continuous carrier mobility increase has been achieved by introduction of process induced and global induced strain, which has been responsible for increase in device performance commensurately with scaling. Strained silicon germanium technology is a hot research area, explored by many different research groups for present and future CMOS technology, due to its high hole mobility and easy process integration with silicon. Several heterostructure architectures for strained Si/SiGe have been shown in the literature.
A dual channel heterostructure consisting of strained Si/Si 1 xGe x on a relaxed SiGe buffer provides a platform for fabricating MOS transistors with high drive currents, resulting from high carrier mobility and carrier velocity, due to presence of compressively strained silicon germanium layer. This works reports the design, modeling and simulation of NMOS and PMOS transistors with a tensile strained Si channel layer and compressively strained SiGe channel layer for a 65 nm logic technology node. Since most of the recent work on development of strained Si/SiGe has been experimental in nature, developments of compact models are necessary to predict the device behavior. A unified modeling approach consisting of different physics based models has been formulated in this work and their ability to predict the device behavior has been investigated. In addition to this, quantum mechanical simulations were performed in order to investigate and model the device behavior. High p/n channel drive currents of 0.43 and 0.98 mA/ m, respectively, are reported in this work. However with improved performance, ~ 10% electrostatic degradation was observed in PMOS due to buried channel device.
vii
Table of Contents Acknowledgement ...... iv
ABSTRACT ...... vii
List of tables ...... xi
List of figures ...... xi
List of Acronyms and Symbols ...... xiv
Chapter 1: Introduction ...... 1
1. Scaling theory and path forwards ...... 1
1.1. Strained Si as a performance adder ...... 2
1.2. Statement of Problem and Thesis contribution ...... 6
1.3. Thesis Organization. ...... 8
Chapter 1: References ...... 9
Chapter 2: Strained Si/SiGe Theory and Architecture ...... 10
2. Introduction ...... 10
2.1. Strained Silicon Formation ...... 12
2.1.1. Uniaxial stress Generation ...... 13
2.1.2. Biaxial Stress Formation ...... 15
2.2. Strained Silicon Physics ...... 21
Chapter 2: References ...... 32
Chapter 3: Process Modeling Analysis, Simulation and Device Design ...... 35
3. Introduction ...... 35
3.1. Dual Channel Substrate Stack Formation...... 37
3.2. STI and Gate Stack Formation ...... 39
3.3. Source and Drain Formation ...... 41
viii
3.4. Silicidation ...... 45
3.5. Thermal Effects on Dopant Diffusion. ...... 46
3.5.1. Arsenic Diffusion Profile ...... 46
3.5.2. Phosphorous diffusion profiles ...... 47
Chapter 3 References ...... 49
Chapter 4: Device Modeling Analysis and Quantum Mechanical Modeling ...... 50
4. Introduction ...... 50
4.1. Device Simulation ...... 50
4.1.1. Numerical Solution Techniques...... 50
4.1.2. Models ...... 51
4.2. Operation of Strained Si/strained SiGe MOS...... 54
4.3. Quantum Mechanical Effects in Strained SiGe PMOS. ...... 57
Chapter 4: Reference ...... 60
Chapter 5: Electrical Characterization: Performance Analysis of DCH MOS ...... 61
5. Introduction ...... 61
5.1. Drain Current Characteristics (I D VD, V GS ) ...... 61
5.2. Threshold Voltage ...... 66
5.3. Short Channel Effects ...... 68
5.3.1. Sub threshold Conduction ...... 69
5.3.2. DIBL ...... 71
5.3.3. Leakage ...... 73
5.4. Mobility Extraction ...... 75
5.5. Capacitance Voltage Curve Analysis. ...... 81
Chapter 5: References ...... 89
ix
Chapter 6: Conclusion and Future Work. ...... 91
6.1 Summary ...... 91
6.2 Recommendations for Future Work ...... 94
APPENDIX A: SIMULATION CODES ...... 97
Process Simulation ...... 97
Device Simulations ...... 102
APPENDIX B: Material Parameters Used in Simulation ...... 105
x
List of tables Number Page Table 1.1: Material properties...... 3
Table 3.2 Key process parameter and process recipe ...... 36
Table B1 : Band Parameters for Silicon and Polysilicon ...... 105
Table B2 : Static dielectric constant for silicon and polysilicon ...... 105
Table B3: Lattice mobility model (Low Field Mobility) for Si and polysilicon ...... 105
Table B4 : Band Gap Narrowing Parameters ...... 105
Table B5: Material Parameter for SiGe ( x=0.3 ...... 106
List of figures Number Page Figure 1.1.0 Schematic of Strain Silicon Heterostructure[1] ...... 6 Figure 1.1.1 Comparison of hole effective mobility in various Si channel ...... 6 and Strained Si/SiGe channel [1] Figure 2.1.0 Different Methods of Straining Si Lattice [8] ...... 13 Figure 2.1.1 Stress Line configuration and schematic of a dual stress liner [13] [14] ...... 15 Figure 2.1.2 TEM Image of e SiGe Transistor [14]...... 16 Figure 2.1.3 Band modification of tensile strained Si and compressively strained SiGe. Adapted from [18]………………………………………………………………………………………….17 Figure 2.1.4 Schematic Illustration of Matthew and Blakeslee model of critical thickness. A pre existing threading dislocation at (a) critical interface and (b) incoherent interface. Critical thickness hC is determined by force exerted in dislocation line by misfit stress FE and tension in dislocation line FL. Adapted from [18]……….………………………………………………..19 Figure 2.1.6 Schematic Illustration of nucleation and growth of dislocation half loop. Adapted from (Top) [18] (Bottom) [19]……………………………………………………………………20 Figure 2.1.7 Threading dislocation as a function of Ge composition in a LPCVD grown buffer layer. Adapted from [23]………………………………………………………………………….22 Figure 2.1.8 (a) Growth dependence of surface roughness and relaxation ration in SiGe buffer layer. (b) Ge content dependence of surface roughness and threading dislocation in SiGe buffer. Adapted from [18]………………………………………………………………………………..22
xi
Figure 2.1.9 Band diagram of biaxial tensile strained Si based on six k.p method. Adapted from [28]………………………………………………………………………………………………..25 Figure 2.2.0 CB and VB shifting of biaxial tensile strained Si as a function of germanium content calculated from 30 k.p method grown on a [001] buffer. The value 0 indicates the VB level. Adapted from [34]………………………………………………………………………………...26 Figure 2.2.1 Band diagram of biaxial tensile strained Si based on six k.p method. Adapted from [3]………………………………………………………………………………………………... 27 Figure 2.2.2 CB of uniaxial tensile strained Si showing sub band quantization and band splitting. Adapted from [1]………………………………………………………………………………… 27 Figure 2.2.3 Effective mass in strained Silicon grown on [001] SiGe buffer as a function of germanium content. Adapted from [31]………………………………………………………… 29 Figure 2.2.4 DOS effective mass computed from six k. p method in a biaxial tensile strained Si as a function of germanium content. Adapted from [28]……………………………………………30 Figure 2.2.5 Valence band mixing and splitting in case of biaxial compressive strained SiGe. Adapted from [15]………………………………………………………………………………. 32 Figure 3.1.0 Schematic of dual channel strained wafer..………………………………………..39 Figure 3.1.1 Simulated wafer structure (001) buffer SiGe for (A) PMOS (B) NMOS…………..40 Figure 3.1.2 simulated (A) PMOS (B) NMOS after gate stack pattern with feature size………..42 Figure 3.1.3 Source/Drain concentration for PMOS (a) after Implant I (b) after Implant II. The region marked are in order as (left to right) Strained Si, Strained SiGe, Relaxed and Graded SiGe………………………………………………………………………………………44 Figure 3.1.4 Source/Drain concentration for NMOS (a) after Implant I (b) after Implant II. The region marked are in order as (left to right) Strained Si, Strained SiGe, Relaxed and Graded SiGe. ……………………………………………………………………………………………………44 Figure 3.1.5 Source/Drain concentration after RTA (900C, 15 Sec) (Top) PMOS (bottom) NMOS. The region marked are in order as (left to right) Strained Si, Strained SiGe, Relaxed and Graded SiGe. Phosphorous diffuses more in SiGe than Arsenic. The plot also show amount of germanium out diffusion…………………………………………………………………………45 Figure 3.1.6 Simulated NMOS (Left) and PMOS (Right) structure after self aligned silicidation process……………………………………………………………………………………………46 Figure 3.1.7 Simulated Arsenic concentration in NMOS structure as a function of anneals time and temperature (No Anneal, 800 C/ 30 sec, 700C/ 15 Sec, 900C/15 Sec)……………………...48 Figure 3.1.8 Simulated Phosphorous concentration in NMOS structure as a function of anneals time and temperature (No Anneal, 800C;30min, 700C;15Sec, 900C;15 Sec)………..………….49 Figure 4.1.0 Schematic diagram of a strained Si/Strained SiGe MOSFET [8]………………….55 Figure 4.1.1 Energy band diagram of strained Si/Strained SiGe PMOS (Top), NMOS (Bottom). Simulated band diagram (Left) and schematic showing hole and electron concentration (right) …………………………………………………………………………………………….55
xii
Figure 4.1.2 Conduction Current Density in strained Si in NMOS (Left) at VG=0.2V ( VTns ), (Right) at VG=1.2V (| VG|>> | VTns |), the electron sheet concentration remains in strained Si…...56
Figure 4.1.3 (a) Conduction Current Density in strained Si/strained SiGe in PMOS (Left) at VG= 0.22V ( VTns ), inversion takes place in strained SiGe layer , (Right) at VG= 1.2V (| VG|>> | VTns |), the hole sheet concentration is still in strained SiGe , however a small parasitic conduction channel forms in strained Si……………………………………………………………………………….57 Figure 4.1.3 (b) Conduction Current Density as a function of hole density in strained Si/strained SiGe in PMOS…………………………………………………………………………………. ..58 Figure 4.1.4 Classical and Quantum Mechanical Electron Density versus Depth for a NMOS device with 2nm of thick gate oxide. Adapted from [10]………………………………………...59
Figure 4.1.5 PMOS I D VD curves with and without QME………………………………………60
Figure 5.1.0 ID VD|VG curves for n MOS and p MOS devices…………………………………...64
Figure 5.1.1 ID VD|VG curves for n MOS and p MOS devices compared to results published in [2] for uniaxial strained Si……………………………………………………………………………65
Figure 5.1.2 Comparison of simulated dual channel ID VD|VG curves for n MOS and p MOS devices to single channel biaxial tensile strained device [3]……………………………………..66
Figure 5.1.3 Comparison of ID VD|VG curves obtained from unified models vs. conventional MOS model…………………………………………………………………………………………….. 66
Figure 5.1.4 Simulated dual channel ID VG|VD curves for n MOS and p MOS devices…………68
Figure 5.1.5 Comparison of simulated dual channel ID VG|VD curves for n MOS and p MOS devices to single channel biaxial tensile strained device [3]……………………………………..69 Figure 5.1.6 Typical subthreshold curves showing various leakage currents..……………... …... 70
Figure 5.1.7 Subthreshold curves (logarithmic plot of ID Vs V G) (A) for p MOS and (b) for n MOS…………………………………………………………………………………………...71 72 Figure 5.1.8 Reverse channel effect and DIBL in NMOS with initial DIBI…...………………..74 Figure 5.1.9 Subthreshold plots of (a) p MOS (b) n MOS showing various leakage currents…..75 Figure 5.2.0 Subthreshold plots of (a) p MOS showing various off state leakage current as a function of gate length……………………………………………………………………………76 Figure 5.2.2 Drain current in linear region for (a) p MOS and (b) n MOS…………………...…79 Figure 5.2.3 (a) Effective Hole mobility vs. vertical electric field, compared to various published work [2]…………………………………………………………………………………………...80 Figure 5.2.3 (b) Effective Electron mobility vs. vertical electric field for dual channel n MOS...... 81 Figure 5.2.4 Gate to drain overlap capacitance obtained from split CV method (a) n MOS(b) p MOS………………………………………………………………………………………………84 Figure 5.2.5 Schematic representation of charge thickness model for total gate capacitance [11]. ……………………………………………………………………………………………………85
xiii
Figure 5.2.6 Equivalent gate capacitance model based on charge thickness model for (a) Strained Si/SiGe device (b) Strained Si/SiGe [12]…………………………………………………………85 Figure 5.2.7 Total gate capacitance curves based on charge thickness model obtained from simulation (a) p MOS and (b) n MOS…………………………………………………………....89 List of Acronyms and Symbols 1. 2D: Two Dimensional 2. As: Arsenic 3. AMD: Advanced Micro Devices 4. B: Boron
5. CA: Accumulation Capacitance 6. CB: Conduction Band
7. CD: Depletion Capacitance
8. CF: Fringing Field Capacitance
9. CG: Gate Capacitance 10. CGDO: Gate to Drain Overlap Capacitance 11. CGSO: Gate to Source Overlap Capacitance 12. CMOS: Complimentary Metal Oxide Semiconductor 13. CMP: Chemical Mechanical Planarization 14. CPEN : Compressive Plasma Enhanced Nitride
15. Cox : Oxide Capacitance/Dielectric Capacitance
16. CT: Total Capacitance of strained Layer
17. CTH : Inversion Capacitance at heterointerface
18. CTS : Inversion Capacitance in Strained Si 19. C V: Capacitance –Voltage 20. CVD: Chemical Vapor Deposition 21. DC: Direct Current 22. DCH: Dual/Double Channel Heterostructure 23. dESL: Dual Etch Stop Liner 24. DG: Density Gradient 25. DIBL Drain Induced Barrier Lowering 26. DIBI: Drain Induced Barrier Increase 27. DOS: Density of States
xiv
28. e SiGe: Embedded Silicon Germanium
29. Eg : Band Gap Energy 30. GIDL: Gate Induced Drain Leakage 31. GSMBE: Gas Source Molecular Beam Epitaxy 32. HH: Heavy Hole 33. IBM : International Business Machine
34. ID: Drain Current 35. IEEE: Institute of Electrical and Electronic Engineer ( USA) 36. IEDM : International Electron Device Meeting 37. IIT: Indian Institute of Technology 38. ILD: Inter Layer Dielectric
39. IOFF : Off State Leakage Current
40. ION : On State Current 41. L: Gate Length 42. LDD: Lightly Doped Drain
43. Leff : Effective Gate Length 44. LH : Light Hole 45. LPCVD: Low Pressure Chemical Vapor Deposition 46. MBE: Molecular Beam Epitaxy 47. MIT: Massachusetts Institute Of Technology 48. MOS: Metal Oxide Semiconductor 49. MOSFET: Metal Oxide Semiconductor Field Effective Transistor 50. N MOS: N type Metal Oxide Semiconductor
51. NA: Acceptor Doping Concentration
52. ND: Donor Doping Concentration 53. ONO: Oxide Nitride Oxide 54. P: Phosphorous 55. PECVD: Plasma Enhanced Chemical Vapor Deposition 56. PEN: Plasma Enhanced Nitride 57. PMOS: P type Metal Oxide Semiconductor
58. QB: Base Depletion Charge
59. Qi: Inversion Charge
xv
60. QME: Quantum Mechanical Effects 61. RPCVD: Regular Pressure CVD 62. RSCE: Reverse Short Channel Effects 63. S/D: Source and Drain 64. Si: Silicon 65. SiGe: Silicon Germanium
66. SiO 2: Silicon Dioxide 67. SIMS: Secondary Ion Mass Spectroscopy 68. STI: Shallow Trench Isolation 69. SO Spin Orbital 70. SOI: Silicon on Insulator 71. SRH: Shockley Read Hall 72. SSMBE: Solid Source Molecular Beam Epitaxy
73. Tcap : Thickness of Strained Silicon Cap Layer 74. TEM: Transmission Electron Micrograph
75. Tox : Gate Oxide Thickness 76. TPEN: Tensile Plasma Enhance Nitride
77. Tpoly : Height of Polysilicon 78. UHV – Ultra High Vacuum 79. VB: Valence Band
80. VD: Drain Voltage
81. VDS : Drain Source Voltage
82. VDSAT : Drain Saturation Voltage
83. VG: Gate Voltage
84. VT: Threshold Voltage 85. W : Width of Transistor
86. WD: Depletion Width
xvi Chapter 1 : Introduction
Chapter 1: Introduction 1. Scaling theory and path forwards ...... 1 1.1. Strained Si as a performance adder ...... 2 1.2. Statement of Problem and Thesis contribution ...... 6 1.3. Thesis outline...... 8
1. Scaling theory and path forwards In the last few decades, the semiconductor industry has enabled a large scale decrease in chip area, with the conventional MOSFET proven to be remarkably scalable to gate lengths of 45 nm by simply scaling the gate length, oxide thickness, and junction depth.
The intrinsic device performance down to the 65 nm node has increased by about 17 % per year following the decrease in drawn gate length and consequently the channel length
[1]. This performance increase has mainly relied on increasing the effective carrier velocity by various innovative process methods such as gate scaling, dielectric thickness scaling, use of high k dielectrics, steep retrograde wells, heavily doped S/D junctions.
However, with conventional MOSFET the carrier mobility has been more or less constant. Hence, to effectively increase the drive current, performance boosters are needed. Looking into the history of silicon, one of the possible methods to vary mobility is straining the silicon lattice. It has been shown earlier that whenever the band structure of material is changed, properties like band gap, effective mass, mobility and diffusion profile change. Hence, by the imposition of either process induced or globally induced
P a g e | 1 Chapter 1 : Introduction strain in the silicon lattice, it has been shown that effective mobility has improved significantly.
1.1. Strained Si as a performance adder Silicon germanium technology is not a very new technology. The effects of SiGe such as stress, strain, band gap and piezoelectric effects on silicon technology have been studied since the 1950s. Various studies and research have shown that if the band structure of the material is changed, physics and electrical properties of the material change, such as effective mass, mobility, and diffusivity of dopant [2]. Table 1.1 summarizes the material properties of silicon, germanium and silicon germanium materials. From Table 1.1 it can be observed that 4.17 % lattice mismatch between silicon and germanium, makes SiGe a favorable material in strained silicon technology.
The other aspect is easy integration with current silicon process technology without any major design and capital investment.
P a g e | 2 Chapter 1 : Introduction
Table 1.1: Material properties. Property Material Type/ Empirical Equation Temp Crystal structure Si (x=0) Diamond 300 K Ge (x=1) Diamond 300 K
Si 1-xGe x Diamond (random alloy) Melting point 2 o Si 1-xGe x Ts(1412 738 x + 263 x ) C solidus, 300 K 2 o Si 1-xGe x Tl (1412 80 x 395 x ) C liquid, 300 K Si (x=0) 1412 K 300 K Ge (x=1) 937 K 300 K Thermal conductivity 1 1 Si 1-xGe x (0.046 + 0.084 x) W cm K 0.2 < x <0.85; 300 K. Si (x=0) 1.3 W cm 1 K 1 300 K Ge (x=1) 0.58 W cm 1 K 1 300 K Thermal diffusivity Si (x=0) 0.8 cm 2 s 1 300 K Ge (x=1) 0.36 cm 2 s 1 300 K Thermal expansion 6 1 Si 1-xGe x α = (2.6 + 2.55 x) x 10 K x < 0.85, 300 K 6 1 Si 1-xGe x α = (7.53 0.89 x) x 10 K x > 0.85, 300K Surface micro hardness 2 Si 1-xGe x (1150 350x) kg mm 300 K Dielectric constant (static) Si (x=0) 11.7 300 K Ge (x=1) 16.2 300 K
Si 1-xGe x 11.7 + 4.5 x 300 K Effective electron mass (longitudinal)
Si 0.98 mo 300 K Ge 1.6 mo 300 K
Si 1-xGe x 0.92 mo 300K, x < 0.85 0.159 mo 300K, x > 0.85 Effective electron mass (transverse)
Si 0.19 mo 300 K Ge 0.08 mo 300 K
Si 1-xGe x 0.19 mo 300K, x < 0.85 0.08 mo 300K, x > 0.85 2/3 Effective mass of density of states mcd =M mc for all conduction bands
Si 1-xGe x 1.06 mo 300K, x < 0.85 1.55 mo 300K, x > 0.85
P a g e | 3 Chapter 1 : Introduction
2 1/3 Effective mass density of states mc=( ml+mt ) in one valley of conduction bands
Si 1-xGe x 0.32 mo 300K, x < 0.85 0.22 mo 300K, x > 0.85
Effective hole masses (heavy) mhh
Si (x=0) 0.537 mo 4.2 K Ge (x=1) 0.33 mo
Effective hole masses (light) mlh
Si (x=0) 0.153 mo 300 K Ge (x=1) 0.0430 mo 300 K Effective hole masses (spin-orbit-split ) mso
Si 1-xGe x (0.23 0.135 x) mo 300 K Si (x=0) 0.234 mo 300 K Ge (x=1) 0.095(7) mo 300 K
Effective mass of conductivity mcc = 3/(1/m l+2/m t) Si 1-xGe x 0.26 mo 300K, x < 0.85 0.12 m 300K, x > 0.85 Lattice constant a(x) Si 5.431 Å 300 K Ge 5.658 Å 300 K
Si 1-xGe x ( 5.431 + 0.20 x + 300 K 0.027 x2) Å
Figure 1.1.0 [1] shows the schematic of various strained silicon heterostructure material stacks. These layers, when grown on each other, have different lattice constants thus creating a stress in the lattice. When a stress or strain is applied on the lattice, the symmetry of the lattice is broken and with it the electronic symmetry. Certainly this has consequences for energy band gap of the material and thus results in energy level splitting into two out of plane valleys and four in plane valleys, inversion layer quantum confinement shifts, average effective mass changes due to repopulation and band wrapping, changes in two dimensional densities of states, and reduced inter band scattering changes. All these effects lead to re population of electrons and holes,
P a g e | 4 Chapter 1 : Introduction improvement in in plane conductive mass and high density of states, and reduced scattering effects thus enabling higher electron and hole mobility.
There are numerous ways to create a stress in a film. The key idea should be to make process simple, cost effective, and compatible with existing technology with high throughput. The stress can be induced by stressing the lattice either in the x y plane, widely known as biaxial strain, or in just in the channel direction {110}, commonly referred as uniaxial strain [3]. Both of these straining techniques have different effects on the band structure and carrier transport.
Based on experimental and theoretical research, the uniaxial process induced strain has been widely accepted by different industry groups and was successfully followed in
90 nm mainstream production [4] . There are two major reasons for choosing uniaxial strained silicon over biaxial tensile strained Si. First, it results in an increase in both electron and hole mobility at lower germanium content and shows less degradation of mobility at high electric field unlike biaxial strained silicon where high hole mobility is possible with high germanium content. Second is high throughput and cost effectiveness.
However, there exists a third type of strain which is biaxial compressive strain. Various research papers [5 7] have shown high hole mobility in a biaxial compressively stressed
SiGe layer compared to uniaxial compressively strained Si layer and biaxial tensile strained Si layer.
In this work we have investigated the performance and working of the dual channel heterostructure device. A dual channel heterostructure (DCH) uses a combination of a
P a g e | 5 Chapter 1 : Introduction biaxial tensile strained Si and biaxial compressively strained SiGe layer [8 10] [Figure
1.1.0(b)] to enable simultaneously high electron and hole mobility as shown in figure
1.1.1[1].
Figure 1.1.0 Schematic of Strain Silicon Heterostructure [1]
Figure 1.1.1 Comparison of hole effective mobility in various Si channel and Strained Si/SiGe channel [1] 1.2. Statement of Problem and Thesis contribution The objective of this work is twofold, first to present dual channel heterostructure as a potential candidate for next generation strained silicon devices, secondly to develop a
P a g e | 6 Chapter 1 : Introduction unified modeling approach based on different physics based models to simulate and predict the device behavior.
Most current state of the art transistors are based on the uniaxial process induced strain using both a dual stress liner and embedded SiGe (e SiGe) technology. The main drawback for these devices is dependence on geometry and gate pitch, with the key being to achieve conformality of nitride films without pinching off the top of overlayer film.
This becomes a process challenge with shrinking gate dimensions and ultimately will create a bottleneck in achieving high performance from the device.
Dual channel heterostructure at present seems to be a promising solution in addressing the above issue. Unlike biaxial tensile strained MOS, which enhances only electron mobility significantly, dual channel heterostructure enhances both electron and hole mobility at low germanium content.
As most of the recent developmental work in strained Si has been experimental in nature, development of compact models is necessary in order to understand and correctly predict the device behavior. Further, there are no known compact SPICE (BSIM) models existing for strained Si transistors. However several authors have recently proposed and published the compact SPICE models for strained Si/Strained SiGe devices.
In this work we report the design, modeling and simulation of n MOS and p MOS transistors for a 65 nm logic technology node. A unified modeling approach consisting of different physics based models has been formulated in this work and their ability to predict the device behavior has been evaluated. In absence of access to experimental data,
P a g e | 7 Chapter 1 : Introduction the results are benchmarked with Intel’s published 65 nm work. Further, an attempt has been made to validate simulated device parametric results with recently published compact SPICE models [11 13].
1.3. Thesis Organization. This thesis work has been divided into six chapters. Chapter 2 briefly discusses the fundamentals of strained silicon technology, physics behind the mobility improvement in the strained silicon devices, and processing fundamentals for fabricating the device.
Chapter 3 describes the process flow and simulation techniques for the strained silicon devices. It also addresses the process challenges, effects of anneal time and temperature dependent dopant diffusion profiles as well as techniques to overcome them. Various assumptions taken during simulations are also discussed in order to make the simulations simpler. Chapter 4 discusses the device modeling and simulation. Band gap engineering, quantum confinement, and the operating mechanism of the dual channel hetero structure are shown. Chapter 5 discusses the electrical characterizations and validation of physics based models based on published compact model and experimental data. Mobility improvement and degradation has been briefly discussed with other device parameters.
Chapter 6 summarizes and concludes the work with suggestions for future improvements. Appendix A gives the compiled code.
P a g e | 8 Chapter 1 : Introduction Chapter 1: References
[1] D.A. Antoniadis et al., “Continuous MOSFET performance with device scaling: The role of strain and channel material innovations”, IBM J RES & DEV, Vol 50, No 4/5, pp 1 14, July/September 2006. [2] P.R. Chidambaram et al., “Fundamental of silicon material properties for successful exploitation of strain engineering in modern CMOS manufacturing”, IEEE Trans Electron Devices, Vol 53, No 5, pp 944 964,May 2006. [3] Luke Collins, “Silicon takes the strain”, IEE Review” , Vol 49 Issue 11, Dec 2003, pp 46 49 Available: http://ieeexplore.ieee.org/iel5/2188/28227/01262450.pdf?arnumber=1262450 . [4] Scott E. Thompsons et al. , “Uni axial process induced strained Si: extending the CMOS roadmap”, IEEE Trans Electron Devices, Vol 53, No 5, pp1010 1020, May 2006. [5] Sarah H. Olsen et al., “High performance n MOSFETs using a novel strained Si/SiGe CMOS Architecture”, IEEE Transactions on Electron Devices , Vol 50, No 9, pp 1961 1969, 2003. [6] J. Jung et al. , “Implementation of both high hole and electron mobility in strained Si/strained Si 1 xGe x on relaxed Si 1 y Ge y (x < y) virtual substrate,” IEEE Electron Device Lett. , vol. 24, pp. 460–462, July 2003. [7] Sarah H. Olsen et al., “Study of single and dual channel designs for high performance strained –Si SiGe n MOSFETs”, IEEE Trans Electron Devices, Vol 51, No 7, July 2004. [8] Shaofeng Yu et al., “Strained –Si strained SiGe dual channel layer structure as CMOS substrate for single work function metal gate technology” IEEE Electron Device Lett., Vol 25, No 6, pp 402 405,June 2004. [9] Yee Chia Yeo et al., “Design and fabrication of 50 nm Thin Body p MOSFET with a SiGe Hetero structure Channel” IEEE Trans Electron Devices, Vol 49, No 2, pp 279 286 ,Feb 2002. [10] Masashi Shima, “<100> Strained –SiGe channel P MOSFET with enhanced hole mobility and lower parasitic resistance” Fujitsu Sci Tech Journal” ,Vol. 39, pp 78 83, June 2003. [11] B. Bindu et al., “Analytical model of drain current of strained Si/strained Si 1 YGe Y/relaxed Si 1 xGe x NMOSFET and PMOSFET for circuit simulation”, Solid State Electron, 50, pp 448 455, March 2006. [12] B. Bindu et al., “A unified model for gate capacitance –voltage characteristics and extraction of parameters of Si/SiGe heterostructure p MOSFET”, IEEE Trans Electron Devices, Vol 54, No 8, pp 1889 1896, Aug 2007. [13] B. Bindu et al. , “Analytical model of drain–current of Si/SiGe heterostructure p channel MOSFETs for circuit simulation,” IEEE Trans. Electron Devices , vol. 53, No. 6, pp 1411–1419, Jun. 2006. P a g e | 9 Chapter 2 : Strained Si/SiGe Theory
Chapter 2 : Strained Si/SiGe Theory and Architecture 2. Introduction ...... 10 2.1. Strained Silicon Formation ...... 12 2.1.1. Uniaxial stress Generation ...... 13 2.1.2. Biaxial Stress Formation ...... 15 2.2. Strained Silicon Physics ...... 21
2. Introduction Impressive technological progress has been achieved by the semiconductor industry in
the last few decades by feature scaling. However, the era of scaling of planar
conventional CMOS as outlined by Dennard et al. is slowly diminishing, due to
fundamental scientific and engineering limits, high cost of production and saturating
performance. For the next several decades, there is no viable alternative to replace
silicon CMOS; however, by incorporating performance improvements to the existing
technology, the limits of engineering can always be pushed. The first major
performance booster to conventional CMOS was the introduction of strained Si in the
channel region [1]. In order to continue to drive the performance from strained silicon
technology, it is necessary to understand the physics behind strain and to develop
unified models to effectively predict a device behavior and design them. The following
sections of this chapter will focus on a brief history of strained Si, different strain
formation processes, physics behind strain, performance improvements in strain
technology and finally the design of a strained Si/strained SiGe heterostructure device.
P a g e | 10 Chapter 2 : Strained Si/SiGe Theory
A) History of Strained Silicon
The influence of strain on the mobility of intrinsic silicon was first observed in 1950
[2 3] . The origin of strained Si film grown on relaxed SiGe can be traced to the 1980’s
[4]. The thin Si layer takes the larger lattice constant of silicon germanium and creates
a biaxial strain. While strain effects were not largely exploited, it was in the early
1990’s that the strain was once again revived at MIT, on process induced and biaxial
strain. In 1992, the first n channel MOS with a strained Si channel exhibiting a 70%
higher mobility was demonstrated. Gannavaram et al. [5] proposed the idea of
embedded SiGe in source and drain, which is now the mainstream technology in the
state of the art strained silicon transistors. Careful analysis and cost effectiveness led
industry to adopt process induced uniaxial strain, mainly due to two reasons. First, it
results in an increase in both electron and hole mobility at lower germanium content
and shows less degradation of mobility at high electric field unlike biaxial strained
silicon where high hole mobility is possible with high germanium content. Second,
uniaxial strain is cost effective and can be easily integrated with conventional CMOS
technology. With process induced strain or uniaxial strain showing lots of promise,
commercial adoption of strain technology was followed in 90 nm node by all major
semiconductor companies, including AMD, Intel, IBM. While IBM and AMD adopted
strained Si with their SOI technology, Intel went ahead with strained Si on bulk Si. To
date a lot of new structures for strained silicon have been proposed, including process
induced strain, SiGe free strained Si technology, strained Si on insulator and strained
silicon heterostructures.
P a g e | 11 Chapter 2 : Strained Si/SiGe Theory
2.1. Strained Silicon Formation Strain in the thin film lattice can be due to various reasons, including lattice constant differences, inclusion of atoms of impurities in the interstitials, and thermal processing.
However, not all strain in the lattice is constructive and beneficial to the device. There are numerous ways to induce strain in the silicon lattice. The key requirement is to make process repeatable, cost effective and compatible with existing manufacturing technology, and able to withstand the thermal cycles [6 7].
There are various types of strain which can be applied either in one, two or three dimensions, each having its own effect on the physical properties of the material. The two major straining techniques widely studied and used in the industry are biaxial strain and uniaxial strain. Biaxial strain is strain to the lattice in the x y plane with a negative compressive strain in the z direction. The other type of strain is process–induced strain or uniaxial strain, where the principal strain lies in one direction and other two directions adjust to match. Figure 2.1.0 [8] shows, the collective summary of different methods of straining techniques.
P a g e | 12 Chapter 2 : Strained Si/SiGe Theory
Figure 2.1.0 Different Methods of Straining Si Lattice [8]
2.1.1. Uniaxial stress Generation Uniaxial stress generation process is a widely adopted process in almost all high performance logic technology devices. In uniaxial process induced strain, the strain is added in the channel layer beneath the gate/gate dielectric stack in the (110) plane by introducing a tensile/compressive stressed nitride capping layer on the device structure
[3] [9] [10]. A predominant method for depositing an ultra high stress nitride layer is plasma enhanced chemical vapor deposition process along with post deposition treatment
[11] at high temperature (~ 650°C) to minimize hydrogen content and maximize stress enhancement. In this process a tensile plasma enhanced nitride (TPEN) layer is first deposited over the device and then selectively etched over p MOS leaving a tensile stressed n MOS, followed by compressive plasma enhanced nitride layer (CPEN) layer deposition over PMOS [12] . Because these stress lines also act as an etch stops for contact etch this approach is referred to as dual etch stop liners (dESL) [13] [14]. This process is mostly used by IBM and AMD with SOI integration [15]. However, this process has a drawback due to dependence on geometry and gate pitch. With stress liners
P a g e | 13 Chapter 2 : Strained Si/SiGe Theory the key is to achieve and maintain conformality of the film without pinching off the top of overlayer film [13]. To accommodate these limitations, the process integration challenge involves the thinning of nitride stress liners without degradation of stress.
Figure 2.1.1 [13] [14] shows the stress configuration and schematic of device.
Figure 2.1.1 Stress Line configuration and schematic of a dual stress liner [13] [14]. The other common stressor approach is incorporation of SiGe in the source and drain region of p MOS commonly known as e SiGe or embedded SiGe. Because of the epitaxial deposition and lattice mismatch, with SiGe having higher lattice constant than
Si, a compressive stress is formed in the Si channel. The advantages to the e SiGe
P a g e | 14 Chapter 2 : Strained Si/SiGe Theory method includes ability to retain hole mobility at high vertical electric field and reduce
S/D extension resistance [14] [16] . However, the process challenge with SiGe S/D epi includes creating a defect free epi region and source/drain area in proximity to the channel, which influences the drive current. Figure 2.1.2 [14] shows the transmission electron micrograph (TEM) image of the e SiGe in S/D region of PMOS.
Figure 2.1.2 TEM Image of e SiGe Transistor [14].
2.1.2. Biaxial Stress Formation A widely adopted approach to introduce wafer based stress relies on the fact that the lattice constant of SiGe alloy is slightly larger than pure Si. When a film is pseudomorphically grown or deposited on a substrate, the mismatch strain between the two layers due to difference lattice constant is given by [17]
asub − afilm εstrain = Equation (1) asub where asub and afilm are the lattice in substrate and film, respectively. The stress then can finally be computed based on Hooke’s law as [17]:
ν +1 σo = −2γ εstrain Equation (2) ν −1
P a g e | 15 Chapter 2 : Strained Si/SiGe Theory where γ is the shear modulus and ν is the Poisson ratio.
As there is a 4.2% lattice mismatch between Si and Ge, the strain induced by lattice modifies the band structure of the SiGe layer and Si layer. Whenever a silicon germanium film is deposited over Si, it is forced to accommodate a film with lower lattice constant; hence the silicon germanium film is under a longitudinal and transverse compressive stress with an out of plane tensile component. On other hand, if a Si film is deposited on a SiGe film, a biaxial longitudinal and transverse tensile stressed layer is produced with an out of plane compressive component. This effect is illustrated in Figure
2.1.3 [18] with corresponding six ellipsoidal є k diagrams.
Figure 2.1.3 Band modification of tensile strained Si and compressively strained SiGe. Adapted from [18]. A) Growth of Si/SiGe epitaxial layer
The two common process technologies used in fabrication of biaxial stressed virtual substrate 1 are (a) molecular beam epitaxial (MBE) and (b) chemical vapor deposition
1 Virtual substrate is a stack comprising of buffer SiGe and Si .
P a g e | 16 Chapter 2 : Strained Si/SiGe Theory
(CVD) [18 19] [20 24] . Typically MBE can be performed either using solid source MBE
(SSMBE) or gas source MBE (GSMBE). Both processes are fairly simple; however, a typical advantage of GSMBE is the capability of selective epitaxial growth on SiO 2 mask patterned by Si substrate. Growth can be performed at both at low and high temperature with the former being a surface reaction limited growth, growth rate increasing with increase in Ge content, and the latter being an impingement flux limited growth, where growth rate saturates with increasing temperature and decreases with increasing Ge concentration. CVD can be employed to produce thin epitaxial SiGe alloy films. UHV,
LPCVD and RPCVD are the most commonly used methods.
B) Critical thickness
As an epitaxial layer grows on lattice mismatched films, the difference in lattice parameter is accommodated elastically up to a certain critical thickness so that in plane lattice parameter of the pseudomorphic film is equivalent to substrate [18 19] . The elastic energy due to strain in the films increases with film thickness. When this thickness and elastic strain energy rises above the critical value, the introduction of misfit dislocation becomes energetically favorable and the epilayer relaxes plastically.
The minimum value of film thickness is referred to as critical thickness, based on
Matthews and Blakeslee [18] which considers the balance of force exerted on a propagated dislocation with misfit and threading segments in strained films as shown in figure 2.1.4 [18] .
P a g e | 17 Chapter 2 : Strained Si/SiGe Theory
Figure 2.1.4 Schematic Illustration of Matthew and Blakeslee model of critical thickness. A pre existing threading dislocation at (a) critical interface and (b) incoherent interface. Critical thickness hC is determined by force exerted in dislocation line by misfit stress FE and tension in dislocation line FL. Adapted from [18]. The critical thickness based on the above model is given by [18]
2 b 1( −ν cos α) hc hc = 1+ ln Equation (3) 8π ()1+ν f cosθ b where α is the angle between misfit dislocation line and its burgers vector and θ is the angle between misfit dislocation burgers vector and a line in the interface drawn perpendicular to the dislocation line. Figure 2.1.5 [19] shows the critical thickness with dependence on germanium content and temperature.
Figure 2.1.5 Experimental determined critical thickness as a function of germanium content and temperature. Adapted from [19].
P a g e | 18 Chapter 2 : Strained Si/SiGe Theory
C) Misfit Dislocation and Strain Relaxation
The lattice mismatch induces strain in the film and elastic energy is accumulated with increasing film thickness. However, after a critical thickness the relief of elastic energy in strain film takes place mainly due to two reasons: (a) elastic deformation accompanying surface evolution of film; (b) plastic deformation with introduction of misfit dislocation [18][19][23] . As shown in Figure 2.1.6 [18] [23] , at the initial stage of relaxation, dislocation or half loops nucleate either heterogeneously on local imperfections or homogenously at the film surface. These half loops grow until they reach the substrate/overlayer interface, then each threading part of the dislocation bends and glides toward the edges, leaving a misfit dislocation in the plane of the interface.
Figure 2.1.6 Schematic illustration of nucleation and growth of dislocation half loop. Adapted from (Top) [18] (Bottom) [19].
P a g e | 19 Chapter 2 : Strained Si/SiGe Theory
D) Approaches to Reduce Defect Density
There are several known process techniques by which threading dislocations and misfit dislocations can be controlled. One of the most widely used methods is a compositionally graded buffer [18] [19] [22] . In this process the germanium content of the SiGe alloy gradually increases with film thickness. The profile can either be linear or step wise. The structure can be considered as the sum of low mismatched interfaces.
Misfit dislocations are successively introduced, resulting in total relaxation of strain. As each atomic plane tends to have its own equilibrium lattice, the dislocations due to differences in lattice parameter between substrate and top layer are distributed over the thickness of graded regions. Such a configuration results in much lower threading dislocation density typically in order of 10 5~ 10 7 cm 2. However, this method suffers from serious surface roughness, cross hatch pattern and residual threading dislocations, commonly known as field dislocation density and pile up density [23 26] . The residual threading dislocation and pile up can be removed from the wafers using advanced epi methods such as LPCVD growth of the buffer layer [23] . The effect is shown in figure
2.1.7. A low temperature method can also be incorporated to grow crystal quality buffer as proposed in [18]. It is found that surface roughness is much better and dislocation density is much smaller. Figure 2.1.8 [23] shows the surface roughness and relaxation ratio with SiGe growth temperature. Another method commonly used to provide a high quality epi layer is CMP. The other methods apart from above listed methods are selective epitaxy, wafer bonding technique; SiGe free strained Si, and SOI integration.
P a g e | 20 Chapter 2 : Strained Si/SiGe Theory
Figure 2.1.7 Threading dislocation as a function of Ge composition in a LPCVD grown buffer layer. Adapted from [23].
Fig 2.1.7 Fig 2.1.8 Figure 2.1.8 (a) Growth dependence of surface roughness and relaxation ratio in SiGe buffer layer. (b) Ge content dependence of surface roughness and threading dislocation in SiGe buffer. Adapted from [18].
2.2. Strained Silicon Physics Strained Si has been studied for almost 50 years and the motivation behind the use of strained Si devices was the strong dependence of mobility on the strain. The simple qualitative Drude model dictates =eτ/m where 1 /τ is the scattering rate and m is the conductivity effective mass. Strain enhances the electron and hole mobility by reducing the effective mass and scattering. For electrons, the two most acceptable theories are
P a g e | 21 Chapter 2 : Strained Si/SiGe Theory reduction in effective mass and phonon scattering (dominant at room temperature) [27
31] . However, based on various experiments and models, the effective mass theory seems to be most fitting reason and for rest of the mechanisms scattering theory seems to be exemplary case of serendipity [31] . In the case of holes, valance band wrapping and repopulation of holes explains the significant increase in mobility [1] [3] [27] [32 33] . In this section we first explain the mechanics of strain, followed by its effects on band structure and carrier transport mechanisms.
A) Effects of strain on Si crystal Symmetry and Band Structure.
Band Structure: Biaxial Tensile Strained Si
Due to commutation between symmetry and crystal Hamiltonian, crystal symmetry is a key parameter in determining the band structure and in understanding the band splitting induced strain/stress. Due to the cubic crystal structure of Si, the heavy hole
(HH) and light hole (LH) bands are degenerate at the Ґ point. As strain is induced in the
Si lattice, (assuming that strain is not equal in x, y, z plane) due to the disturbance in the symmetry, degeneracy between HH and LH band is removed.
The biaxial strain in the [001] direction is due to lattice differences between the bulk silicon and SiGe alloy. The strain tensors in the [001] direction take forms as
εxx = εyy = ε ||= [a || −a0(Si)]/ a0(Si) Equation (4)
εzz = ε ⊥= [a ⊥ −a0(Si ]/) a0(Si) Equation (5)
εxy = εzx = εyz = 0 Equation (6)
P a g e | 22 Chapter 2 : Strained Si/SiGe Theory with a|| =a 0(Si xGe 1 x) and a┴ = a 0(Si){ 1 2C 12 /C 11 x[ a|| a0(Si)]} where C11 and C 12 are elastic constants. The deformation potentials a c, a v, and b v relate the corresponding shifts and splitting of strain tensors. For a case of an indirect band gap semiconductor, like Si, the minimum of the conduction band is not at k= 0 and this minimum stems from Ґ 5c conduction band. Based on the k.p method the band dispersion can be calculated over the
Brillouin zone [28].
/1 2 /3 2 Based on the triply degenerate Γ5v,c band ( Γ8v,c ,Γ8v,c and Γ7v,c ) the strain Hamiltonian matrix takes forms given by [28]:
2/3 2/1 Γ8v,c Γ ,8 vc Γ ,7 vc
av, cε + bv, cε ||⊥ 0 0
0 av, cε − bv, cε ||⊥ 2 bv, cε ||⊥ Equation (7)
0 2 bv, cε ||⊥ av, cε
where є= 2є|| +є ┴, є ||┴= є ┴ є|| and av,c and bv,c are hydrostatic and splitting deformation potential, respectively. Based on the above Hamiltonian, the conduction band (CB) is split into four equivalent in plane 4 valleys and two out of plane 2 valleys, resulting in energy of conduction band minima of 4 in plane valley relative to 2 valleys as shown in figure 2.1.9 [28] .
P a g e | 23 Chapter 2 : Strained Si/SiGe Theory
Figure 2.1.9 Band diagram of biaxial tensile strained Si based on six 2 k.p method. Adapted from [28].
The splitting strain energy is given by [29] Estrain =0.67 x eV where x is the germanium
/1 2 mole fraction. In case of the valence band the strain Hamiltonian splits the LH ( Γ8v,c ) and
2/3 the HH ( Γ8v,c ). Also, due to the non diagonal term of the above matrix, the wave functions of the LH and the split off (SO) are mixed. Based on the crystal symmetry, under the biaxial tensile stress the x y is still a square, but the x(y z) planes become rectangle. Therefore, the HH band is now composed of states polarized in the x y direction whereas LH band is polarized in the z direction. Thus HH and LH bands at valence band edge are not degenerate. For the top most valence band this indicates that effective mass in the x y plane is close being isotropic in nature, and this is undesirable.
Fig 2.2.0 [34] shows the effect of germanium mole fraction on the CB and VB shifting.
2 Six refers to number of bands of Si used in calculation using k.p method.
P a g e | 24 Chapter 2 : Strained Si/SiGe Theory
Figure 2.2.0 CB and VB shifting of biaxial tensile strained Si as a function of germanium content calculated from 30 3 k.p method grown on a [001] buffer. The value 0 indicates the VB level. Adapted from [34].
Band Structure: Uniaxial Strained Si
In case of uniaxial stress transistors stressed along <110> axis, the crystal symmetry is destroyed more, as the <110> axis is not a highly symmetric axis. As shown in Fig
2.2.1 [3] , strain breaks the symmetry in the x y plane such that the x y plane is symmetric with respect to two diagonals. Less symmetry leads to more band wrapping, which is beneficial for the hole effective mass. In the case of uniaxial compressive stress in the channel direction the energy of the 4 valley is less compared to 2, which is undesirable for electrons and hence uniaxial tensile strain is used. Figure 2.2.2 [1] shows the band splitting in the case of uniaxial tensile strained silicon. Not much difference in the effective electron mass is observed between uniaxial and biaxial strain.
3 30 refer to number of bands of Si used in calculation using k.p method.
P a g e | 25 Chapter 2 : Strained Si/SiGe Theory
Figure 2.2.1 Band diagram of biaxial tensile strained Si based on six k.p method. Adapted from [3].
Figure 2.2.2 CB of uniaxial tensile strained Si showing sub band quantization and band splitting. Adapted from [1]. Electron Transport in Strained Si
For the MOSFET under biaxial strain in the (001) axis, the strain removes the degeneracy between the four in–plane valleys and two out of plane valleys by splitting the energy. It is well known that in the inversion mode the electronic states are quantized into subbands, which in case of a (100) surface, are composed of two series of eigenstates: one arising from two fold valley with longitudinal mass ml, and second arising from four fold valley with transverse mass mt. In the case of strained silicon, the band splitting of the conduction band E strain is superimposed on the subband energy of
P a g e | 26 Chapter 2 : Strained Si/SiGe Theory unstrained Si. The total energy of electrons occupying the subband in the two fold ( Etot,
2 ) and four fold valley (Etot, 4 ) can be represented as [29]:
2 2 h k 2 Etot, 2 = + Ei + Ec Equation (8) 2md 2
2 2 2 2 h k 4 h k 2 Etot, 4 = + Ei + Ec = + Ei + Ec + Estrain Equation (9) 2md 4 2md 2
The splitting of energy lowers the energy of the 2 valley as seen by above equations, meaning that they are preferentially occupied by the electrons. The electron mobility is thus partly increased due to the reduction in in plane transverse effective mass
(mt=0.19 m0) and increased out of plane longitudinal mass ( ml=0.98 m0) with increased density of states. Figure 2.2.3 [34] shows effective mass variation with germanium content obtained by 30 k.p method. It can be seen that with increase in germanium content the effective mass does not change significantly. For a given amount of strain, mass reduction alone explains a part of the increased mobility; hence phonon scattering and roughness scattering is also reduced. However, quantifying the reduced scattering mechanism has been difficult, and there appears to be no physical justification [31], but reduced scattering is still believed to account for the rest of mobility measurements.
P a g e | 27 Chapter 2 : Strained Si/SiGe Theory
Figure 2.2.3 Effective mass in strained Silicon grown on [001] SiGe buffer 4 as a function of germanium content. Adapted from [31].
Hole Transport in Strained Si
For holes, complex valence band structure and valence band wrapping under strain results in a much larger hole mobility enhancement. The band wrapping behaves differently for different types of strain and so does mobility enhancement. Strain alters three aspects of the band structure: (1) the out of plane effective mass, which determines the magnitude of energy shift under the applied gate voltage of transistor; (2) conductive effective mass along channel direction [110]; (3) the energy contour in kx ky plane which determines the density of states (DOS). For an unstrained Si the upper band or top band
u l Γ8v corresponds to HH and lower band Γ8v corresponds to LH. With the application of strain, the hole effective mass become a highly anisotropic and due to band wrapping energy levels becomes a mixture of the heavy, light and split off bands. The HH and LH band lose their meaning at a higher strain. To achieve high hole mobility, low in plane
4 SiGe buffers comprises of relaxed SiGe and graded SiGe stack.
P a g e | 28 Chapter 2 : Strained Si/SiGe Theory conductive mass for upper or top band and high density of states are required to populate
u the top band. With the application of the strain (Ge mole fraction > 0) the top band Γ8v is
l LH type and lower band Γ8v corresponds to HH type. As LH band is higher in energy compared to HH band, consequently the population of hole is increased in LH band which explains the higher hole mobility. In the case of uniaxial compressive strained Si channel, both smaller in plane conductive mass and high density of states is achieved.
However, in the case of biaxial tensile strained Si in the <001> direction, smaller out of plane mass is achieved compared to in plane mass in top or upper band at lower germanium content. Higher values of Ge content are required to achieve the low in plane effective mass. This also explains the loss of mobility at high electric field. Figure
2.2.4 [28] and Figure 2.2.5 [15] illustrates hole transport in biaxial tensile and uniaxial compressively strained Si.
Figure 2.2.4 DOS effective mass computed from six k. p method in a biaxial tensile strained Si as a function of germanium content. Adapted from [28].
P a g e | 29 Chapter 2 : Strained Si/SiGe Theory
Figure 2.2.5 Simplified version of valence band splitting in case of uniaxial strained Si and biaxial tensile strained Si. Adapted from [15].
B) Effects of strain on SiGe Band Structure and hole transport.
When a thin SiGe film is pseudomorphically grown on Si/relaxed SiGe, it experiences a biaxial compressive strain. As shown in figure 2.2.6[35] , the HH and LH of the strained SiGe become non degenerate at Γ point. In addition to that strained SiGe films couples the HH and LH band and introduces the band mixing. This leads to hole effective mass in the lower energy band (top most HH band) being smaller and anisotropic. Due to this, both low in plane effective mass and high density of states in the top band are achieved, resulting in high hole mobility [35] [36]. Further, due to band alignment and high valence band discontinuity the hole concentration remains confined in SiGe layer.
P a g e | 30 Chapter 2 : Strained Si/SiGe Theory
Figure 2.2.5 Valence band mixing and splitting in case of biaxial compressive strained SiGe. Adapted from [15].
P a g e | 31 Chapter 2 : Strained Si/SiGe Theory Chapter 2: References [1] Sun et al., " Physics of process Induced Uniaxially Strained Si", Material Science and Engineering, B 135, pp 179 183, 2006. [2] P.R. Chidambaram et al., “Fundamental of silicon material properties for successful exploitation of strain engineering in modern CMOS manufacturing”, IEEE Trans Electron Devices, Vol 53, No 5, pp 944 964, May 2006. [3]Scott E. Thompsons et al. , “Uni axial process induced strained Si: extending the CMOS roadmap”, IEEE Trans Electron Devices, Vol 53, No 5, May 2006, pp1010 1020. [4] H. M. Manasevit et al. , “Electron mobility enhancement in epitaxial multilayer Si–Si1 −xGe x alloy films on (100) Si,” Appl. Phys. Lett. , Vol. 41, No. 5, pp. 464–466, Sep. 1982. [5]S. Gannavaram et al , “Low temperature (800 ◦C) recessed junction selective silicon germanium source/drain technology for sub 70 nm CMOS,” in IEDM Tech. Dig. , 2000, pp. 437– 440. [6] Luke Collins, “Silicon takes the strain”, IEE Review” , Vol 49 Issue 11, pp 46 49, Dec 2003, Available: http://ieeexplore.ieee.org/iel5/2188/28227/01262450.pdf?arnumber=1262450. [7] S. E. Thompson et al , “Key differences for process induced uniaxial vs. substrate induced biaxial stressed Si and Ge channel MOSFETs,” in IEDM Tech. Dig. , 2004, pp. 221–224. [8] Thomas Hoffman, “Strain Silicon Technology”, IMEC, Strain Silicon Update, Semiconductor International, March 13, 2007. [9] Y. C. Liu et al. , “Single stress liner for both NMOS and PMOS current enhancement by a novel ultimate spacer process,” in IEDM Tech. Dig. , Washington, DC, 2005. [10] S. E. Thompson et al. , logic nanotechnology featuring strained silicon,” IEEE Electron Device Lett. , vol. 25, No. 4, pp. 191–193,Apr. 2004. [11] R. Argahvani et al. , " A reliable and manufacturable method to induce a stress of > 1 GPA on a P channel MOSFET in high volume manufacturing", IEEE Trans Electron Devices , Vol 27, No 2, pp 114 11,Feb 2006. [12] S. Thompson et al. , “A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low κ ILD, and 1 m2 SRAM cell,” in IEDM Tech. Dig. , San Francisco, CA, 2002, pp. 61–64. [13] Peter Singer (2005, Jan 01), Semiconductor International, Available http://www.semiconductor.net/article/CA490112.html . [14] Laura Peters (2007, Jan 03), Semiconductor International, Available: http://www.semiconductor.net/article/CA6418539.html.
P a g e | 32 Chapter 2 : Strained Si/SiGe Theory
[15] N. Mohta et al ., “Strained Si The Next Vector to Extend Moore’s Law,” IEEE Circuits and Devices Magazine , 2005. [16] P. Bai et al. , “A 65 nm logic technology featuring 35 nm gate lengths, enhanced channel strain, 8 cu interconnects layers, low κ ILD and 0.57 m2 SRAM cell,” in IEDM Tech. Dig. , 2004, pp. 657–660. [17] S. C. Jain et al. , “Stresses and Strains in Lattice mismatched Stripes, Quantum Wires, Quantum Dots, and Substrates in Si Technology,” J. Appl. Phys ., Vol. 79, No. 11, June 1996. [18] Yasuhiro Shiraki et al. , “Fabrication Technology of SiGe hetero structure and their properties”, Surface Science Report , 59, 2006, pp 153 207. [19] Natalia F. Izyumskaya et al., “Control over strain relaxation in Si based heterostructures”, Solid State Electronics , 48, pp 1265 1278, 2004.
[20] S. H. Olsen et al., “High performance n MOSFETs using a novel strained Si/SiGe CMOS architecture.” IEEE Transactions on Electron Devices 2003, 50 (9), 1961 1969.
[21] J. Jung et al. , “Implementation of both high hole and electron mobility in strained Si/strained Si 1 xGe x on relaxed Si 1 y Ge y (x < y) virtual substrate,” IEEE Electron Device Lett. , Vol. 24, pp. 460–462, July 2003.
[22]S. H. Olsen et al., “Impact of virtual substrate growth on high performance strained Si/SiGe double quantum well metal oxide semiconductor field effect transistors”, Journal Appl Phys , 94 (10), pp 6855 6863, 2003.
[23] Matthew Erdmann, " Growth and characterization of high Ge SiGe virtual substrates ", 204th Meeting ECS , October 2003.
[24] Mayank Bulsara, Strained silicon technology key elements of wafer fabrication ," SMG Workshop Semicon, 2003.
[25]S. H. Olsen et al. , “Strained Si/SiGe n channel MOSFETs: Impact of cross hatching on device performance,” Semicond. Sci. Technol. , vol. 17, pp. 655–661, 2002. [26] J. W. Matthews et al. , “Defects in epitaxial multilayer,” J. Cryst. Growth , Vol. 27, pp.118– 125, 1974. [27] M. V. Fischetti and S. E. Laux, “Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys,” J. Appl. Phys. , Vol. 80, No. 4, pp. 2234–2252, 1996. [28] Soline Richard et al., " Strained silicon on Ge: temperature dependence of carrier effective masses", Journal of Appl Phy , Vol 94, No 8, pp 5088 5094,Oct 2003. [29] Shin ichi Takagi et al., “Comparative study of phonon limited mobility of two dimensional electron in strained and unstrained Si metal oxide semiconductor field effect transistor”, Journal Appl Phy , Vol 80, No3, pp 1567 1577,Aug 1996.
P a g e | 33 Chapter 2 : Strained Si/SiGe Theory
[30] Th. Volesang et al., “Electron transport in strained Si layers on Si 1 xGe x Substrate”, Appl Phy Lett , Vol 63, No 2, pp 186 188, July 1993. [31] M.V. Fischetti et al., “On the enhanced electron mobility in the strained silicon inversion layers”, Journal of Appl Phy , Vol 92, No 12, pp 7320 7324, Dec 2002. [32] C. W. Leitz et al., “Hole mobility enhancements in strained Si–Si Ge p type metal oxide semiconductor field effect transistors grown on relaxed Si Ge (x < y) virtual substrates,” Appl. Phys. Lett., vol. 79, No. 25, pp. 4246–4284, 2001. [33] M.V. Fischetti et al., "Six band k.p calculation of the hole mobility in silicon inversion layers: dependence on surface orientation, strain and silicon thickness", Journal Appl Phy, Vol 94, No 2, pp 1079 1095, July 2003. [34] D. Rideau et al. , "Strained Si, Ge and SiGe alloy modeling with full zone k.p method optimized from first principle calculation", ST microelectronics CEDEX France, Vol 1, July 2006. [35] Yee Chia Yeo et al., “Design and fabrication of 50 nm Thin Body p MOSFET with a SiGe Hetero structure Channel” IEEE Trans Electron Devices, Vol 49, No 2, pp 279 286, Feb 2002. [36] Masashi Shima, “<100> Strained –SiGe channel P MOSFET with enhanced hole mobility and lower parasitic resistance” Fujitsu Sci Tech Journal” , 39, pp 78 83, June 2003.
P a g e | 34 Chapter 3: Process Simulation
Chapter 333: Process Modeling Analysis, Simulation and Device Design 3. Introduction ...... 35 3.1. Dual Channel Substrate Stack Formation ...... 37 3.2. STI and Gate Stack Formation ...... 39 3.3. Source and Drain Formation ...... 41 3.4. Silicidation ...... 45 3.5. Thermal Effects on Dopant Diffusion...... 46 3.5.1. Arsenic Diffusion Profile ...... 46 3.5.2. Phosphorous diffusion profiles ...... 47
3. Introduction A dual channel strained Si/SiGe, dual spacer, oxynitride gate dielectric integration scheme was used for this 65 nm logic process technology. The n channel and p channel devices were designed using a novel CMOS process technique in SUPREM4 based on the
Silvaco Athena process simulator [1] . The strained Si/Strained SiGe channel layers were pseudomorphically grown on a relaxed Si 1 xGe x, SiGe graded buffer layer and silicon substrate [2 3]. The process specifications for designing the flow were based on minimum capping layer thickness for the strained silicon layer [4 8], the melting point of the silicon germanium layers, and diffusivity of the various dopants in the layers. The sections of this chapter will focus on process development, various splits used in process development, effects of annealing temperature on the diffusivity, and process challenges at each step. Table 3 1 gives the complete information on the various parameters used in the processing.
P a g e | 35 Chapter 3: Process Simulation Table 3.2 Key process parameter and process recipe
P a g e | 36 Chapter 3: Process Simulation
3.1. Dual Channel Substrate Stack Formation A dual channel strained silicon MOS technology was designed and simulated using
SILVACO’s SUPREM 4 based ATHENA simulator. Strained Si strained SiGe channel layers were pseudomorphically grown on relaxed SiGe, graded buffer layer and silicon substrate. The virtual substrate stack consists of relaxed SiGe, graded buffer layer and silicon substrate. The virtual substrate (VS) was grown using the epitaxial deposition models. Model Sigec is invoked in the Method statement to simulate dopant diffusion in
SiGe. The germanium percentage in SiGe was defined as y.N Si where NSi is the atomic density of undoped silicon .
All device samples were pseudomorphically grown using SiH 4 and GeH 4 on a (100) oriented Si substrate that was ~ 10 15 cm 3 B doped. Growth begins with deposition of a relaxed compositionally graded SiGe buffer layer, grown at 500°C, which forms the virtual substrate of device layers. All compositionally graded layers were graded at 10%
Ge/ m, capped with 70 nm of relaxed Si 0.85 Ge 0.15 layer, epitaxially grown at 500°C in order to minimize the misfit dislocations [6]. Following virtual substrate growth ~ 12 nm compressively strained Si 0.7 Ge 0.3 was grown and finally a tensile strained Si was grown.
The strained Si layers for n channel and p channel were targeted to be ~ 5 nm and 3 nm, respectively, to ensure that the primary inversion layer forms first in strained Si for
NMOS, and in strained SiGe for PMOS [3 4] [7 8]. The thin cap also minimizes electrostatic degradation from buried channel conduction [2]. The controlled removal of
2 5 nm Si on the p channel device relative to n channel structure was done by controlled oxidization of silicon surface, and etching of sacrificial oxide film. All layers were in
P a g e | 37 Chapter 3: Process Simulation situ doped with boron ~10 17 cm 3 with a retrograde well for n MOS. For p MOS the n well was formed by in situ doping of relaxed SiGe layer , strained SiGe and Si layer with phosphorous ~ 10 17 cm 3, with a retrograde well. During the entire simulations the structure considered for silicon germanium was silicon with highly doped germanium in order to properly simulate diffusion profiles in silicon germanium layers. For the present work we have considered the devices with germanium concentration scheme of 15/30 5 with different gate lengths and different anneal times. Figure 3.1.0 shows the architecture of the dual channel heterostructure device grown on bulk Si and Figure 3.1.1 shows the simulated dual channel strained substrate with dopant profiles.
Figure 3.1.0 Schematic of dual channel strained wafer
5 15/30 refers to Ge content in Relaxed SiGe and Strained SiGe, respectively.
P a g e | 38 Chapter 3: Process Simulation
(A) Si Ge=20nm Si Graded
=12nm 0.3 Ge
0.7 Si Si Si
Relaxed Si 0.85 Ge 0.15 Strained Strained Si =3nm Strained
(B) nm
20 =12nm =12nm 0.3 Si Ge= Si Ge 0.7 Graded Relaxed Si 0.85 Ge 0.15 Strained Si Si Strained
Strained Strained Si =5nm Si Figure 3.1.1 Simulated wafer structure (001) buffer SiGe for (A) PMOS (B) NMOS. 3.2. STI and Gate Stack Formation For creating isolation, a novel CMOS STI process was incorporated. The substrate was masked and 0.312 m deep trenches were created in the wafer. A thin film of oxide was deposited prior to STI filling. To adjust the field threshold voltage, a blanket implant
P a g e | 39 Chapter 3: Process Simulation was done through an oxide mask for p channel (P, 4E13cm 2,10KeV), n channel (B,
3E13cm 2,16KeV). The implant dose matrix was designed so that, for surface channel devices (n MOS), VTS (threshold voltage for strained silicon layer) is equal to VTH
(threshold voltage at strained silicon strained silicon germanium heterojunction); for buried channel devices (p MOS), VTS is much larger than VTH . The implant was done through oxide in order to protect the wafers from any misfit dislocation and strain relaxation [6] [9]. The remaining oxide was then etched off and CMP was done.
An oxynitride film was used as a gate dielectric stack to minimize gate leakage and boron diffusion through the gate oxide. A 1.7 nm thick film of oxynitride gate dielectric was deposited using monte carlo CVD method with deposition rate of 1nm/min. In absence of unified models for dual plasma nitride RTA growth for oxynitride, a CVD scheme was adopted in the processing recipe. Following gate dielectric deposition,
1200 Å of polysilicon film was deposited using LPCVD with a deposition rate of
12 Å/min for 100 minutes. The polysilicon was in situ doped with phosphorous and boron ~ 10 20 cm 3 for n and p channel, respectively. The polysilicon and gate oxide were finally patterned for the source/drain structure formation. Figure 3.1.2 shows the resultant device structure after gate patterning.
P a g e | 40 Chapter 3: Process Simulation
(A)
Poly Gate = 1300Å
Poly Length = 65 nm
Strained SiGe STI = 0.312µ Relaxed SiGe
(B)
Poly Gate = 1300Å
STI = 0.312µm Poly Length = 65 nm
Strained Si Strained SiGe
Figure 3.1.1 simulated (A) PMOS (B) NMOS after gate stack pattern with feature size. 3.3. Source and Drain Formation An ultra shallow source drain scheme was integrated in this work, with a target junction depth of 34~40 nm. CMOS transistors with ultra shallow source and drain region, an abrupt junction and LDD architecture are known to have better a drive current and enhanced channel strain. In addition, ultra shallow junctions play a significant role in
P a g e | 41 Chapter 3: Process Simulation controlling short channel effects and providing low external resistance ( Rext ) [10]. A
30 nm thick oxide film was deposited prior to the first source/drain implant. The oxide layer acted as a spacer and a mask to prevent any misfit dislocations and strain relaxation due to implant related damage. Source/drain implant I was carried out with As
(5E16 cm 2/22 KeV) for n MOS and B (6E13 cm 2/12 KeV) for p MOS. Finally the oxide layer was patterned to form spacer I. A 50 nm thick nitride layer was deposited prior to source/drain implant II. Source/drain implant II was carried out with P
(4E14cm 2/18 KeV) for n MOS and B (6E15 cm 2/16 KeV). Finally, the nitride layer was etched to form spacer II, thus making the total spacer stack 19 nm thick. Figure 3.1.3 and figure 3.1.4 show the structure after source/drain implant I and II. As seen in figure 3.1.4, germanium out diffusion is observed in the strained Si layer.
(A)
P a g e | 42 Chapter 3: Process Simulation
(B)
Figure 3.1.3 Source/Drain concentration for PMOS (a) after Implant I (b) after Implant II. The region marked are in order as (left to right) Strained Si, Strained SiGe, Relaxed and Graded SiGe (A) (B)
Figure 3.1.4 Source/Drain concentration for NMOS (a) after Implant I (b) after Implant II. The region marked are in order as (left to right) Strained Si, Strained SiGe, Relaxed and Graded SiGe.
P a g e | 43 Chapter 3: Process Simulation
Source/drain dopant activation was achieved using rapid thermal anneal (RTA) at
900°C for 15 sec in nitrogen ambient. The final junction depth after anneal was calculated to be 34 nm for n MOS and 76 nm for p MOS with effective gate length of 54
~ 58 nm. Figure 3.1.5 shows the doping profiles in the source/drain region for (a) n MOS and (b) p MOS after annealing.
Ge Composition
Figure 3.1.5 Source/Drain concentration after RTA (900C, 15 Sec) (Top) PMOS (bottom) NMOS. The region marked are in order as (left to right) Strained Si, Strained SiGe, Relaxed and Graded SiGe. Phosphorous diffuses more in SiGe than Arsenic. The plot also show amount of germanium out diffusion.
P a g e | 44 Chapter 3: Process Simulation
3.4. Silicidation Silicidation with ultra shallow junctions is a big process challenge, due to consumption of silicon during the silicide process in the active source and drain regions
[11]. One of the effective methods used in the industry to address this problem is the use of elevated source and drain regions. There are quite significant advantages of using this process, but incorporating it leads to an increase in process steps. Thus in order to develop a cost effective processing technology, the self aligned novel silicidation process recipe was modified. A 100 nm thick film of refractory material (Ti or Ni) was deposited followed by silicidation in nitrogen ambient at 450°C for 1 minute. Using a low temperature anneal reduced the reaction rate. However, thin silicides lead to a rise in the parasitic capacitance and series resistance. Figure 3.1.6 shows the cross section of simulated structure for (a) n channel and (b) p channel device after silicidation.
Lgate = 55 nm
Figure 3.1.6 Simulated NMOS (Left) and PMOS (Right) structure after self aligned silicidation process.
P a g e | 45 Chapter 3: Process Simulation
3.5. Thermal Effects on Dopant Diffusion. The annealed structures were analyzed using secondary ion mass spectroscopy
(SIMS). The depth profiles were extracted using SIMS in ATHENA. The SUPREM 4 model in ATHENA treats silicon germanium layer as a germanium doped silicon region.
The model considers two major factors – (a) diffusivity dependence on germanium concentration, and (b) intrinsic carrier concentration with germanium content. Equation
10 [1] shows the diffusion models for boron in the silicon germanium.
x DIX.E + x.EAFACT.SIGE D BI = DIX 0. exp− Equation (10) kT
Similarly, the linear variation of the intrinsic carrier concentration for silicon and
SiGe can be given as [1]
Si NI.E NI.POW n i = Ni 0. exp− .T kT Equation (11) SiGe Si ni = n i • 1( + x • NIFACT.SIGE)
The above model in the SUPREM4 simulates the boron diffusion effectively, but is reasonably valid for other dopant [12 14].
3.5.1. Arsenic Diffusion Profile Arsenic profile from n MOS device is shown in the Figure 3.1.7, for source/drain regions, for various anneal temperature and time. From the figure, it is clearly observed that the As profile looks alike in the strained silicon region for splits without anneal and low temperature anneal, whereas for high temperature anneal, As tends to diffuse more into the silicon germanium layer. Increasing anneal time (800°C 30 min split) at lower P a g e | 46 Chapter 3: Process Simulation temperature also shows similar diffusion profiles as seen with higher temperature anneal and shows significant diffusion of As in the silicon germanium region. The results obtained from the simulation matched the experimental observation reported in [12 14]
No Anneal 700C, 15s 900C, 15s
800C, 30min
Strained Strained Si
Strained SiGe Relaxed SiGe
Figure 3.1.7 Simulated Arsenic concentration in NMOS structure as a function of anneal time and temperature (No Anneal, 800 C/ 30 min, 700C/ 15 Sec, 900C/15 Sec). 3.5.2. Phosphorous diffusion profiles The phosphorus diffusion model in the silicon is assumed to be based on neutral, single and double negatively charged interstitials [13]. The dopant diffusivity in strained
SiGe/SiGe was simulated based on SUPREM4 ’s two dimensional and fully coupled models in conjunction with model SiGe , to activate diffusion profiles based on germanium concentration. Figure 3.1.8 shows the phosphorous profiles without anneal and with, 900ºC /15 sec, 800ºC /30 min, 700ºC/15 sec anneals. Phosphorous diffuses more in SiGe both at higher anneal temperature, and low temperature anneal but higher anneal time. The results reported in this work are in agreement with results reported in
[12] [14]. P a g e | 47 Chapter 3: Process Simulation
800C, 30min No Anneal 700C, 15s
Si SiGe 900C, 15s Strained Strained Si Figure 3.1.8 Simulated phosphorous concentrations in NMOS structure as a function of anneal time and temperature (No Anneal; 800 C/30 min; 700C/15 Sec; 900C/15 Sec).
P a g e | 48 Chapter 3: Process Simulation Chapter 3 References [1] Silvaco ATHENA Process Simulator Manual V 5.10, Silvaco International CA, Available at www.silvaco.com . [2] Shaofeng Yu et al., “Strained –Si strained SiGe dual channel layer structure as CMOS substrate for single work function metal gate technology” IEEE Electron Device Lett., Vol 25, No 6, pp 402 405, June 2004.
[3] S. H. Olsen et al., “High performance n MOSFETs using a novel strained Si/SiGe CMOS architecture.” IEEE Transactions on Electron Devices 2003, 50 (9), 1961 1969.
[4] Jongwan Jung et al., “Mobility enhancement in dual channel P MOSFETs .”, IEEE Trans Electron Devices, Vol. 51, No 9, pp 1424 1431, Sep 2004. [5] K. Rim et al , “Fabrication and analysis of deep submicron strained Si NMOSFET’s,” IEEE Trans Electron Devices, Vol. 47, No. 7, pp. 1406 1415, July 2000.
[6] Yasuhiro Shiraki et al. , “Fabrication Technology of SiGe hetero structure and their properties”, Surface Science Report , 59, pp 153 207, 2006.
[7]Yee Chia Yeo et al., “Design and fabrication of 50 nm Thin Body p MOSFET with a SiGe Hetero structure Channel” IEEE Trans Electron Devices, Vol 49, No 2, pp 279 286, Feb 2002.
[8] D.A. Antoniadis et al., “Continuous MOSFET performance with device scaling: The role of strain and channel material innovations”, IBM J RES & DEV, Vol 50, No 4/5, pp 1 14, July/Sep 2006.
[9] J. W. Matthews et al. , “Defects in epitaxial multilayer,” J. Cryst. Growth , Vol. 27, pp.118– 125, 1974. [10] P. Bai et al. , “A 65 nm logic technology featuring 35 nm gate lengths, enhanced channel strain, 8 cu interconnects layers, low κ ILD and 0.57 m2 SRAM cell,” in IEDM Tech. Dig. , 2004, pp. 657–660. [11] Lance Scudder et al., “Selective silicon processing for advance ultra shallow junction engineering”, Applied Material, pp 92 95, 2002. [12] S. Eguchi et al. , “Comparison of arsenic and phosphorous diffusion behavior in silicon germanium alloy”, Appl Phy Lett , Vol.80, No. 10, pp 1743 1745, March 2002. [13] S. Eguchi et al. , “Germanium concentration dependence of arsenic diffusion in silicon germanium alloys”, Appl Phy Lett , Vol.84, No. 3, pp 368 370, Jan 2004. [14] Erika Duda et al, “Secondary ion mass spectrometer characterization of source/drain junction for strained silicon channel metal oxide semiconductor field effect transistor,” J. Vac. Sci.Technol. B, Vol. 22, No. 1, pp. 327 331, Jan./Feb. 2004
P a g e | 49
Chapter 4 –Device Modeling Analysis
Chapter 444: Device Modeling Analysis and Quantum Mechanical Modeling 4. Introduction ...... 50 4.1. Device Simulation ...... 50 4.1.1. Numerical Solution Techniques ...... 50 4.1.2. Models ...... 51 4.2. Operation of Strained Si/strained SiGe MOS ...... 54 4.3. Quantum Mechanical Effects in Strained SiGe PMOS ...... 57 4. Introduction The devices designed in Silvaco Athena ™ [1] were exported to the ATLAS ™ device simulator for parametric analysis. The device behavior and DC parameters are extracted by numerical solution of physics based semiconductor models. Various specification and adjustment parameters defined in BISM 3V3.3 [2] and ATLAS are taken as default. This chapter focuses on device simulation, various physics based models, and discussion of quantum mechanical effects.
4.1. Device Simulation All the DC parameter and device behavior analyses were performed in ATLAS.
ATLAS is a physics based 2D and 3D device simulator. For this work, all the simulations performed were based on 2D numerical solutions of physics based equations. ATLAS has a direct interface with the process simulator and the entire device structure data was directly exported to the device simulator.
4.1.1. Numerical Solution Techniques Different combination of models will require ATLAS to solve up to six equations.
The types of solution techniques used in this work are (a) fully coupled Newton and (b)
P a g e | 50
Chapter 4 –Device Modeling Analysis decoupled Gummel. The Gummel method will solve for each unknown in turn keeping the other variables constant, while repeating the process until convergence is achieved.
The Newton method solves the total system of unknowns simultaneously.
4.1.2. Models Compact models have been the heart of CAD tools in order to predict the device behavior by extracting the device parameters. It is thus important to choose the correct models in order to precisely predict the device behavior in the various ranges of operating voltages.
ATLAS provides various physics based device models based on classical semiconductor physics and BSIM models. For this work 2D SPICES, BLAZE and
Quantum simulators have been used from the ATLAS framework. 2D SPICES is a silicon based simulator supporting a wide range of physics based models for the MOS devices which includes field and concentration based mobility models, density of states, energy balance transport models, drift–diffusion transport models, Fermi Dirac and
Boltzmann statistics and recombination models. Blaze is a 2D based compound semiconductor device simulator for III V, II VI, IV IV materials, and simulates devices with position dependent band structure [1] by modification of charge transport equations.
The third simulator used for this work is a quantum simulator. As the devices scale down to sub micron level, the classical physics equations underestimate the effects of quantum confinement and quantum potential well formed in the devices. Various models from these simulators have been invoked during the 2D simulation.
P a g e | 51
Chapter 4 –Device Modeling Analysis a) Energy Balance Transport and Drift Diffusion Model
Impact of field based transport mechanism, velocity saturation, and velocity overshoot on device behavior were accounted for by numerical solution of energy balance transport models [1] [3] [4] and drift diffusion models. The conventional drift – diffusion models neglect non local transport effects such as velocity overshoot, diffusion associated with carrier temperature and dependence of impact ionization rates on carrier energy distribution. The energy balance transport model is derived from the Boltzmann transport equation and incorporates the relationship of current density to carrier temperature, or energy. Thus, using the drift diffusion model in conjunction with energy balance transport model modifies the current density obtained from classical drift diffusion models. b) Band Gap Narrowing
A band gap narrowing model incorporates the effects of doping level on the conduction band and valence band. The band gap narrowing effects are enabled by BGN parameter of the Model statement. As the strained Si strained SiGe device is a band gap engineered device, proper invocation of this model is extremely important [1] [4]. c) Carrier-Carrier Scattering Model
The carrier carrier scattering model includes the dependence on temperature doping, and carrier carrier scattering. This model also includes the effect of lattice scattering, ionized impurity scattering (with screening of charged carriers) and impurity clustering effects on effective mobility [1] [5] [6][7] .
P a g e | 52
Chapter 4 –Device Modeling Analysis d) Shockley-Read-Hall Concentration –Dependent Lifetime Model.
The Shockley Read Hall (SRH) model incorporates the effects of six carrier recombination generation mechanisms viz, phonon transition, photon transition, auger transition, surface recombination, impact ionization and tunneling. The concentration dependent model incorporates the dependence of impurity concentration on carrier recombination [1] [5] [6] . e) Density Gradient Quantum Mechanical Model
With shrinking geometries, quantum confinement effects associated with carriers become dominant and can no longer be simply modeled by classical physics. The effects due to quantum confinement of carriers associated with variation of local potential are predicted and solved using the density gradient model. The density gradient (DG) method calculates a position dependent potential energy according to higher derivatives of the carrier densities. This model is based on the Wigner function equation of motion, which consists of quantum corrections to the carrier temperature in the carrier conduction current and energy equation [1] [4]. In addition to that, the model has the capability to reproduce the carrier concentration predicted by Schrodinger Poisson model but to also predict transport properties. However, this model cannot predict the bound state energy or wave function given by Schrodinger Poisson model. In the density gradient model the expression for electron and hole current is given as:
Jn = qDn∇n − qn n∇(ψ − ∧)− nn(kTL∇(ln nie)) Equation (12)
Jp = −qDp∇p − qp p∇(ψ − ∧)− pp(kTL∇(ln nie)) Equation (13)
γh 2 1 2 2 Equation (14) where ∧ = ∇ log n + ()∇ log n 12m 2
P a g e | 53
Chapter 4 –Device Modeling Analysis 4.2. Operation of Strained Si/strained SiGe MOS As shown in Figure 4.1.0, strained Si/strained SiGe dual channel layer substrate
consists of a stack of tensile strained silicon layer and compressively strained silicon
germanium layer, on relaxed SiGe layer, graded buffer SiGe layer and bulk silicon layer.
Figure 4.1.1 shows the corresponding band diagram under positive and negative gate
bias.
Figure 4.1.0 Schematic diagram of a strained Si/Strained SiGe MOSFET [8].
Figure 4.1.1 Energy band diagram of strained Si/Strained SiGe PMOS (Top), NMOS (Bottom). Simulated band diagram (Left) and schematic showing hole and electron concentration (right) P a g e | 54
Chapter 4 –Device Modeling Analysis For NMOS, in accumulation (VG < VFBS (flat band voltage at surface)), the holes are
accumulated at the Si/SiON interface. In the depletion mode (VG region is formed in the silicon cap layer. With increase in gate voltage, the depletion region width W=WD at VG=V Tsn and inversion occurs at SiON/Si interface. The depletion width WD is given [8 9] 2 2εSiGe(φTH − VB) εsi εsi εsi εsi WD = + tSiGe + tbuff + tcap − tSiGe + tbuff + tcap qNa εSiyGey εSixGex εSiyGey εSixGex Equation (15) where ΦTH is the potential at the top of the Si/SiGe hetero interface, tcap is silicon capping layer thickness and VB is substrate bias. With further increase in gate voltage, the electron sheet concentration increases, resulting in increased drive current. However, if the gate voltage reaches the flat band voltage of the heterojunction (VG=V FBHS), the entire silicon cap layer is depleted and eventually the region extends to the SiGe layer [8 9]. Thus, in the case of NMOS, the inversion layer forms in the strained silicon layer initially and drain current is mainly due to electrons in the strained Si layer as shown in Figure 4.1.2. Strained Si Strained Si Strained SiGe Strained SiGe Figure 4.1.2 Conduction Current Density in strained Si in NMOS (Left) at VG=0.2V ( VTns ), (Right) at VG=1.2V (| VG|>> | VTns |), the electron sheet concentration remains in strained Si. P a g e | 55 Chapter 4 –Device Modeling Analysis In the case of PMOS, with increase in negative gate bias the depletion layer width widens in SiGe layer and equals to WD as given by: 2 2εSiGe(VB − φTH ) εsi εsi εsi εsi WD = + tSiGe + tbuff − tSiGe + tbuff qND εSiyGey εSixGex εSiyGey εSixGex Equation (16) at VG = V THP ( threshold voltage at Si/SiGe heterojunction), an inversion layer forms in the strained SiGe layer as shown in Figure 4.1.3(a) (left). Two factors play important roles in creating inversion layer in silicon germanium: (1) TSiPMOS < T SiNMOS and (2) the VTH (threshold voltage at hetero junction) is much less than VTSp (threshold voltage of silicon). Also with high valence band discontinuity the inversion layer is confined to strained silicon germanium region only. However, with continuous increase in the gate voltage, at VG=V TSp , the band bends sufficiently to create a parasitic parallel conductive channel in the Si cap near the interface [5] as shown in Figure 4.1.3(a) (right). Figure 4.13 (b) shows the inversion layer density in the top two layers as a function of hole density. Figure 4.1.3 Conduction Current Density in strained Si/strained SiGe in PMOS (Left) at V = 0.22V G (VTns ), inversion takes place in strained SiGe layer , (Right) at VG= 1.2V (| VG|>> | VTns |), the hol e sheet concentration is still in strained SiGe , however a small parasitic conduction channel forms in strained Si. P a g e | 56 Chapter 4 –Device Modeling Analysis Vg = -0.22 V Vg = 1.2 V Figure 4.1.3 Conduction Current Density as a function of hole density in strained Si/strained SiGe in PMOS. 4.3. Quantum Mechanical Effects in Strained SiGe PMOS . In the classical model, the electrons at the Si/SiO2 interface of a typical MOSFET form a classical electron gas and behave in the same manner as an electron in the bulk. This assumption is only valid if the thickness of the inversion layer is much larger than the de Broglie wavelength. In a submicron device, with oxide thickness as small as 3 nm, the inversion layer thickness becomes smaller than the de Broglie wavelength and the inversion layer is confined in the potential well close to the silicon surface, with energy levels being quantized. The inversion layer behaves as a 2D electron gas. Classical physics fails to take account of quantization of energy levels in the potential well at the interface and does not yield an accurate magnitude of inversion layer. Figure 4.1.4 shows the electron distribution using the classical and quantum mechanical models. P a g e | 57 Chapter 4 –Device Modeling Analysis Figure 4.1.4 Classical and Quantum Mechanical Electron Density versus De pth for a NMOS device with 2nm of thick gate oxide. Adapted from [10] In this work, the inversion charge layer in the channel is calculated by solving Fermi Dirac statistics, in conjunction with density gradient quantum mechanical model and self consistent Poisson Schrödinger equation. Considering the quantum mechanical effects (QME) of MOS, inversion mainly takes place in deep sub micron devices, with thin gate oxides and high substrate concentration. In order to simulate QME, a PMOS device structure with 1.7 nm gate oxide, Leff =58 nm, 3 nm strained Si cap layer with substrate doping of 10 17 cm 3 was adopted. Figure 4.1.5 illustrates the effect of the QME on the I V characteristics of PMOS. The shift in the current is by 3.7 % relative to the case without QME. Incorporating QME results in the decrease of the hole sheet concentration in the Si channel but gives an increase in the SiGe channel, thus decreasing the threshold voltage of surface parasitic channel in the strained silicon surface. Further, with increase in gate bias the hole sheet P a g e | 58 Chapter 4 –Device Modeling Analysis concentration increases further in SiGe which is beneficial for high mobility. However, both surface potential and normal field increase when QME is taken into consideration. The increase in the channel field will aggregate the scattering mechanisms and depress the carrier mobility [5]. However, this phenomenon is less pronounced in the strained SiGe PMOS as compared to strained Si PMOS shown by Yang et al. [5]. Figure 4.1.5 PMOS I D VD curves with and without QME. P a g e | 59 Chapter 4 –Device Modeling Analysis Chapter 4: Reference [1] Silvaco ATLAS Device Simulator Manual V 5.10, Silvaco International CA, Available at www.silvaco.com . [2] BSIM 3 V 3.3 User Manual, Department of Electrical Engineering and Computer Sciences, University of California Berkley. Available at http://www device.eecs.berkeley.edu/~bsim3 . [3] Th. Volesang et al., "Electron transport in strained Si layers on Si 1 xGe x Substrate", Appl Phy Lett , Vol 63, No 2, pp 186 188, July 1993. [4] Shaofeng Yu et al., “Strained –Si strained SiGe dual channel layer structure as CMOS substrate for single work function metal gate technology” IEEE Electron Device Lett., Vol 25, No 6, pp 186 188, June 2004. [5] Rong Yang et al. , “ Simulation and comparison of MOS inversion layer quantum mechanics effects in SiGe PMOSFET and Si PMOSFET”, Microelectronics Journal , Vol. 35, pp 145 149, 2004. [6] Shin ichi Takagi et al., “Comparative study of phonon limited mobility of two dimensional electron in strained and unstrained Si metal oxide semiconductor field effect transistor”, Journal Appl Phy , Vol 80, No 3, pp 1567 1577, Aug 1996. [7] M.V. Fischetti et al., “On the enhanced electron mobility in the strained silicon inversion layers”, Journal of Appl Phy , Vol 92, No 12, pp 7320 7324, Dec 2002. [8] B. Bindu et al., “Analytical model of drain current of strained Si/strained Si 1 YGe Y/relaxed Si 1 xGe x NMOSFET and PMOSFET for circuit simulation”, Solid State Electron, 50, pp 448 455, March 2006. [9] B. Bindu et al., “A unified model for gate capacitance –voltage characteristics and extraction of parameters of Si/SiGe heterostructure p MOSFET”, IEEE Trans Electron Devices, Vol 54, No 8, pp 1889 1896 Aug 2007. P a g e | 60 Chapter 5 –Electrical Characterization Chapter 5: Electrical Characterization: Performance Analysis of DCH MOS 5. Introduction ...... 61 5.1. Drain Current Characteristics (I D VD, V GS ) ...... 61 5.2. Threshold Voltage ...... 66 5.3. Short Channel Effects ...... 68 5.3.1. Sub threshold Conduction ...... 69 5.3.2. DIBL ...... 71 5.3.3. Leakage ...... 73 5.4. Mobility ...... 75 5.5. Capacitance Voltage Curve Analysis. ...... 81 5. Introduction Based on device models explained in Chapter 4, electrical characterization was performed on the simulated devices. All the device characterization was performed in the ATLAS framework [1]. In the absence of access to experimental results, this work has been benchmarked with Intel’s published 65 nm work [2]. In addition to that, simulated results have also been validated with published [3] compact SPICE model for dual channel heterostructure devices. 5.1. Drain Current Characteristics (I D VD, V GS ) Based on two dimensional numerical device solution done with ATLAS, the ID VDS (VGS ) characteristics of n MOS and p MOS devices were obtained. The drain current of p MOS and n MOS can be modeled and understood based on the region of operation and device design. For the p MOS, based on the device operational theory explained in the previous Page | 61 Chapter 5 –Electrical Characterization chapter, the total current is given by sum of the currents at the heterointerface and Si/SiO 2 interface as [4]: SiGe 2 H − z p vt CDp |VG −VTHP | | −VD | I Dsub = exp 1− exp |VG <|| VTHP | L mpvt vt H H H ID = I D = I Dsat {}1 + λp |VD −VDsat | |VTHP ≤ | | VG <|| VTSP | H S s I | VG = VTSP + I 1 + λp |VD −V | | VG ≥|| VTSP | D Dsatp {}Dsatp Equation (17) For n MOS the total device current can be expressed as: Si 2 s − z n vt CDn |VG −VTsn | | −VD | I Dsub = exp 1− exp |VG >|| VTsn | L mnvt vt Si s s − z n maxCox αnVD s ID = I Dlin = VG −VTsn − VD |VD <|| VDsatn | VD s 2 L1+ []1+θ ()VG −VTsn s n 2VLn s S s s I Dn = I Dsatn {}1 + λp |VD −VDsatn | |VD ≥|| VDsatn | Equation (18) The general parameter evaluation followed directly from the ATHENA device structure with Lgate =65 nm (Leff = 55 nm) with a retrograde channel, physical oxide thickness of 1.7 nm and doping concentration of ~10 20 cm 3. For simulating the I V curves, all the above models described in Chapter 4 were incorporated. To incorporate the quantum correction potential, a damping factor is specified by the QFACTOR parameter in the solve statement. The source and body of the FET were connected to ground. The gate voltage | VG| was stepped up from 0.6 V to 1.2 V in steps of 0.2 V. For each gate voltage Page | 62 Chapter 5 –Electrical Characterization the drain voltage | VDS | was swept from 0 to 2V in step of 0.1 V. Figure 5.1.0 shows the simulated output curves for n MOS and p MOS. The peak drain current at |VG| of 1.2 V was obtained to be 0.92 mA/ m and 0.43 mA/ m for the n MOS and p MOS devices, respectively. From the figure it can be clearly seen that n MOS device does not show any channel length modulation behavior, typically seen in all sub micron devices. The possible cause for the discrepancy can be attributed to failure of the velocity saturation model. Figure 5.1.0 ID VD|VG curves for n MOS and p MOS devices. In the absence of access to experimental results, ATLAS predicted IDS VDS characteristics of the strained Si/Strained SiGe channel devices were benchmarked with Intel’s published 65 nm ultra low power state of the art logic transistor with device specification of Vnom =1.2 V, T ox (physical)=1.7 nm, Leff =55 nm) [2] . The comparison also shows the Page | 63 Chapter 5 –Electrical Characterization performance of biaxial strained device with uniaxial device. Figure 5.1.1 shows the comparison of this work benchmarked with Intel’s work. It can be analyzed from the figure that there is 15 % improvement in drain current for biaxial tensile strained n MOS on compressively strained SiGe compared to uniaxial strained n MOS. For p MOS the drain current shows an improvement of 38% at lower value of VG; however, at VG= 1.2 V, the peak drain current is nearly the same. Figure 5.1.1 ID VD|VG curves for n MOS and p MOS devices compared to results published in [2] for uniaxial strained Si. Figure 5.1.2 shows the comparison of drain current characteristics of a dual channel device (Vnom =1.0 V, T ox (physical) =1.7 nm, Leff =55 nm) with a biaxial strained single channel device [3] with a device specification of (Vnom =1.0V, T ox (physical) =1.3 nm, Leff =50 nm). It is clearly evident from the figure that the dual channel device enhances p MOS current by 25%. Taking into the consideration the difference in physical oxide thickness and effective gate length, the enhancement would be much higher. Page | 64 Chapter 5 –Electrical Characterization Figure 5.1.2 Comparison of simulated dual channel ID VD|VG curves for n MOS and p MOS devices to single channel biaxial tensile strained device [3]. Figure 5.1.3 shows the comparison of the unified modeling approach developed in this work for strained Si versus the conventional MOS models. It is clearly evident from the figure that the conventional MOS model fails to take into account the effects of strain, band gap dependent statistics and mobility enhancement due to strain. 5.0E 04 1.2 V 4.5E 04 Unified Models 4.0E 04 1.0 V Conventional MOS Model 3.5E 04 3.0E 04 2.5E 04 2.0E 04 Figure 5.1.3 Comparison of ID VD|VG 1.5E 04 CurrentDrain in A/µm curves obtained from unified models 1.0E 04 vs. conventional MOS model. 5.0E 05 0.0E+00 2 1.5 1 0.5 0 Drain Voltage Page | 65 Chapter 5 –Electrical Characterization 5.2. Threshold Voltage Figure 5.1.4 shows the ID VG characteristics of the simulated device. The ID VG characteristics were obtained at constant VDS =0.1 V, 1 V. The source and the body of the device are assumed to be connected to ground. The gate voltage | VG| was swept from 0 to 1.2 V. This biasing scheme ensures that transistors are in the linear regime of operation for extraction of the threshold voltage. Threshold voltage was defined as the gate voltage (VG) where ID = 100 nA/ m at VDS = 0.1 V. The drain current value was chosen based on extrapolation of the ID VG. The threshold voltages of the p MOS and n MOS devices were obtained to be 0.2 V and 0.22 V, respectively. Based on the drain current model in [4 5], the threshold voltage of the p MOS can be defined as [5] : VTH = φm − χs − (Eg − EV /) q − Qd / CT − k1 Equation (19) where Φm is the metal work function, χs and Eg are the electron affinity and band gap of the Si. Qd is the depletion charge given by qN DWD and k1 is the fitting parameter. For this device k1 is in 0.227 and is consistent with the value published in [5]. CT is the total capacitance given by 1/C T=1/C ox +1/C cap where Ccap is defined as є si /tcap . Based on the 8 2 6 2 above model, with Qdp = 6.9x10 C/cm , CT = 1.749x10 F/cm the threshold voltage reported is 0.22 V. For n MOS the threshold model is given by [4]: VTH = VFB + 2φFn + Qd / CT Equation (20) Page | 66 Chapter 5 –Electrical Characterization where VFB is flat band voltage, in this case taken to be 1.1 V, ΦFn is the Fermi potential and Qdn is the depletion charge, given as qN AWD. Substituting the parameters of n MOS 8 2 6 2 in the above equation with Qdn and CT to be 6.98x10 C/cm , 1.31 x10 F/cm , the estimated threshold voltage comes out to be +0.24 V. Thus, the above published circuit model verifies the threshold voltage extracted from simulation . 1.E 02 1.E 02 1.E 03 1.E 03 1.E 04 1.E 04 1.E 05 0.1V 1.E 05 1.E 06 1.E 06 Log Drain Current (A/ m) 1.E 07 1.E 07 1.E 08 1.E 09 1.E 08 1.5 1 0.5 0 0.5 1 1.5 Gate Voltage Figure 5.1.4 Simulated dual channel ID VG|VD curves for n MOS and p MOS devices. Figure 5.1.5 shows the threshold voltage of a single channel device [3] with a dual channel device. As expected, dual channel devices exhibit lower threshold voltage than the single channel devices, due to band alignment, different electron affinities and increased oxide trap density [6]. The variation in the threshold voltage between single channel and dual channel devices is 10%. Page | 67 Chapter 5 –Electrical Characterization Figure 5.1.5 Comparison of simulated dual channel ID VG|VD curves for n MOS and p MOS devices to single channel biaxial tensile strained device [3]. 5.3. Short Channel Effects To achieve higher circuit density and performance per watt, CMOS technology has been scaled for more than 30 years. With continuous scaling the supply voltage ( VDD ) has to be scaled in order to meet power constraints. Hence, threshold voltage of the device has to be commensurately scaled to maintain a high drive current and achieve performance improvement. However, the threshold voltage scaling results in substantial increase in leakage current [7]. Figure 5.1.6 shows typical ID VG curves in logarithmic scale. The curve allows measurement of several device parameters such as off state leakage current IOFF , threshold voltage, and sub threshold slope. These parameters are indicative of device Page | 68 Chapter 5 –Electrical Characterization performance and modulate with decrease in channel width, giving significance rise in narrow width effects, and increase in off state current with increase in drain bias. All the adverse effects which cause increase in leakage and reduction in threshold voltage in short devices are called short channel effects. Due to adverse short channel effects, the channel length cannot be arbitrarily scaled. Therefore, in order to take best advantage of scaling new design structures must be designed and various process optimizations need to take place. The key is to optimize the channel profile and mitigate leakage currents while maximizing drain current. In this section we analyze significant short channel effects on the device and their implication on the device performance. Figure 5.1.6 Typical subthreshold curves showing various leakage current. Adapted from [7] 5.3.1. Sub threshold Conduction Subthreshold or weak inversion conduction current occurs when | VG| < | VT|. In weak inversion, a small amount of inversion charge is always present in the channel. For a case when | VDS | ≥ 0.1V, or drain bias is very small, the potential across the reverse biased p n junction diminishes, thus lowering the electrostatic potential Φs and vertical electric field. Page | 69 Chapter 5 –Electrical Characterization In such a scenario, the majority of the drain current is dominated by diffusion current. The weak inversion current is given as: W 2 (Vg −Vth)/mvT −VDS /vT Ids = 0Cox (m −1 )(vT ) × e × (1− e ) Equation (21) L where Cdm 3tox m =1+ =1+ Equation (22) Cox Wdm m is referred to the subthreshold swing coefficient and ν T is thermal voltage. The inverse of the slope of log 10 (Ids ) versus Vgs characteristic is referred as subthreshold swing (St) given by −1 d(log 10Ids) mkT St = = 3.2 Equation (23) dVgs q Subthreshold slope is a figure of merit of transistor performance and indicates the rate of decrease of IOFF . Figure 5.1.7 shows the subthreshold characteristics of n MOS and p MOS devices. A Page | 70 Chapter 5 –Electrical Characterization B Figure 5.1.7 Subthreshold curves (logarithmic plot of ID Vs V G) (A) for p MOS and (b) for n MOS. The subthreshold swing of both p MOS and n MOS was found to be 88mV/dec and 78 mV/dec, respectively, at drain voltage ( Vds ) of 0.1 V. Comparing subthreshold conduction of dual channel device with single channel device biaxial strained, both p MOS and n MOS subthreshold slope for the dual channel device shows slight degradation. However, compared to uniaxial strain published in [2], the subthreshold slope looks much better. 5.3.2. DIBL The electrostatic integrity of the devices was assessed in terms of drain induced barrier lowering (DIBL). In short channel devices, with the decrease in gate length, the source/drain depletion width in the vertical direction and potential have a strong effect on the band bending over a significant portion of the device, resulting in energy barrier Page | 71 Chapter 5 –Electrical Characterization lowering. DIBL occurs when the depletion regions of the drain and source interact with each other near the channel surface to lower the potential. When a high drain bias is applied, it lowers the barrier height further, resulting in decrease of threshold voltage, and injection of carriers into the channel at the surface, independent of gate voltage. From the Figure 5.1.7, it can be clearly seen that with increase in drain voltage the threshold voltages rolls down, showing DIBL effect in the devices. DIBL for p MOS and n MOS was found to be 26 mV/V and 12 mV/V, respectively, showing more pronounced DIBL effect and degraded electrostatics in p MOS due to buried conducting channel. However, for the n MOS devices with increase in drain voltage an initial increase in threshold voltage was observed, showing drain induced barrier increase (DIBI) as shown in Figure 5.1.8. The reason for initial increase in the threshold voltage or reverse short channel effect was found to be transient enhanced diffusion due to threaded dislocations and {311} clusters which enhanced boron diffusion and boron pile up near the source and drain Page | 72 Chapter 5 –Electrical Characterization RSCE and DIBL in NMOS 0.36 0.03 0.025 0.35 0.345 Threshold Voltage 0.02 DIBL 0.015 0.34 0.335 0.01 0.33 0.325 0.005 0 0.32 in DIBLmv/V -0.005 ThresholdVolatge (V) in 0.312 -0.01 0.31 -0.015 0.3 -0.02 0 0.5 1 1.5 2 2.5 Vds in V Figure 5.1.8 Reverse channel effect and DIBL in NMOS with initial DIBI. 5.3.3. Leakage A transistor can have six basic types of leakage mechanisms as shown in figure 5.1.9: leakage due to reverse biased p n junction, subthreshold leakage, oxide tunneling, hot carrier injection, gate induced drain leakage (GIDL), and channel punch through current. The off state current is comprised of channel punch through current, GIDL and subthreshold leakage; however, current due to hot carrier injection and reverse biased p n junction consist of both on state and off state current. Figure 5.1.9 shows the different off state current in the (a) p MOS and (b) in the n MOS. For p MOS the off state current was found to be 80 nA/ m at Vds of 1 V. For n MOS device the off state leakage current was found to be 10 nA/ m at drain bias of 1 V. The off state leakage current is consistent with the result published in [8 9]; however, for this work both n MOS and p MOS leakage is less than reported in the literature [3]. Interestingly, it can be observed from the graph that both subthreshold and junction Page | 73 Chapter 5 –Electrical Characterization leakage has increased with drain bias in p MOS whereas it is almost the same in the case of n MOS. The ION /IOff ratio exceeds ten orders of magnitude. Compared to the published literature [2], the leakage in p MOS and n MOS devices has increased by 10x and 4x, respectively at |VG| of 1.2 V. A B Junction Leakage Figure 5.1.9 Subthreshold plots of (a) p MOS (b) n MOS showing various leakage currents. Page | 74 Chapter 5 –Electrical Characterization Figure 5.2.0 shows the off state current in p MOS as a function of gate length at a drain bias of 0.1 V. It can be seen from the figure that the increase in leakage is about 10x times from 90 nm to 65 nm. Looking down at 50 nm, p MOS performance has degraded by almost 100x compared to its performance at 90 nm. Thus further leakage optimization techniques need to be incorporated for p MOS. Figure 5.2.0 Subthreshold plots of (a) p MOS showing various off state leakage current as a function of gate length. 5.4. Mobility Extraction The mobility extraction for n MOS and p MOS was done using the split CV method. Effective mobility was determined at low drain bias of 100 mV. From the drain current equation of the MOS, the effective mobility at low drain bias can be written as a function of the charge assuming that channel charge is uniform from source to drain. Page | 75 Chapter 5 –Electrical Characterization L ID 1 eff = Equation (24) W VDS Qi L gD eff = Equation (25) W Qi ∂ID gD = |VGS = cons Equation (26) ∂VDS In the above equation the Qi is the inversion charge density. In order to determine the effective mobility we need to determine the inversion charge. There are two methods for obtaining the inversion charge density. The first way is the approximation of inversion charge in terms of gate voltage i.e., Qi = Cox(VG −VT ) Equation (27) This approximation fails close to threshold voltage and in the subthreshold region owing to the fact that accurate threshold voltage cannot be easily determined, and variation between the different methods can lead to large error in mobility determination. The other way to determine the channel inversion charge density is by relating it to the channel capacitance between gate and source/drain. Figure 5.2.1 shows the schematic representation of split –current measurement. As the time varying gate voltage is applied to the device two types of current flow in the device. With substrate grounded we measure the current I1: dQi dVGC I 1 = = Cgc Equation (28) dt dt Page | 76 Chapter 5 –Electrical Characterization This relates the inversion charge layer density as: VGS Qi = CgcdVgs Equation (29) ∫−∞ Similarly the bulk charge density can be calculated as: VGS QB = CgbdVgs Equation (30) ∫−∞ Figure 5.2.1. (a)Schematic representation of the split current measurement. (b) To measure I1, the substrate is grounded and the capacitance between the source drain contacts and the gate electrode is measured as a function of gate bias. (c) To measure I2, the source drain contacts are grounded and the capacitance is measured between the substrate and the gate electrode as a function of gate bias Adapted from [10] . Now in order to calculate the transconductance, the slope of drain current was determined. The drain current was obtained in the linear region for various gate biases, with a drain bias varying from 0 to 0.1 V. Since mobility is a function of vertical electric field, the vertical electric field was determined by: ηQi + Qd ξeff = Equation (31) εs Page | 77 Chapter 5 –Electrical Characterization The value of η was taken to be ½ in this case. Based on the above setup, the effective mobility was determined. The C V analysis was performed in the Silvaco ATLAS simulator using the density gradient quantum simulator to account for abrupt potential variation and quantum confinement of charges. Default values for the density gradient model were taken as there are no accurate available data. The inversion charge and bulk charge was determined by integrating the C V curve. Figure 5.2.2 shows the drain current of n MOS and p MOS. A B Figure 5.2.2 Drain current in linear region for (a) p MOS and (b) n MOS. Page | 78 Chapter 5 –Electrical Characterization Figure 5.2.3 (a) shows the effective mobility of p MOS and Figure 5.2.3 (b) shows n MOS for a short channel device as a function of varying electric field. The p MOS mobility was compared to the published result in [2]. The peak mobility obtained from this work was 160 cm 2/V.s. The enhancement in mobility is around 12% compared to the published result. The mobility in the p MOS is a weighted function of mobility in the surface channel and buried channel layers and is a strong function of the thickness of the capping layer. For this work we have determined only the net effective mobility of the device, as determining mobility for each layer and modeling it was beyond the scope of this work. The results obtained for p MOS mobility are also in agreement with data published in the literature [9]. However, some deviations are bound to happen due to lacking of a proper field based model for SiGe and due to unavailability of proper values for the quantum model to determine the exact amount of charge. /V.s 2 cm Figure 5.2.3 (a) Effective Hole mobility vs vertical electric field, compared to various published work [2]. Page | 79 Chapter 5 –Electrical Characterization For n MOS the peak mobility was determined to be 273 cm 2 /V.s. The proper validation of n MOS mobility could not be determined due to unavailability of data for short channel transistors. However, based on the work published in the literature [9] for dual – channel MOS with 100 nm of gate length, the enhancement in the electron mobility is around ~ 45%. As the mobility is known to degrade with decreasing gate length, the apparent enhancement in the electron mobility, obtained for this work at 65 nm can be accounted for (a) the excessively degraded mobility in the published literature [9] result and (b) due to unavailability of proper simulation values of density gradient quantum model, which can result in either underestimation or overestimation of inversion charge. Also, as per the published result, slight degradation in electron mobility is observed for n MOS due to high surface roughness and significant interface charge density. /V.s 2 cm Figure 5.2.3 (b) Effective Electron mobility vs. vertical electric field for dual channel n MOS. Page | 80 Chapter 5 –Electrical Characterization 5.5. Capacitance Voltage Curve Analysis. A) Gate overlap Capacitance Low frequency C V analysis was performed on both n MOS and p MOS devices to extract gate overlap capacitance to source and drain and total gate capacitance. The simulation was performed in the ATLAS framework. To measure the overlap capacitance, the gate of the device was biased initially to high voltage at VG = 2 V with source and drain shorted and grounded. The gate voltage was then swept from 2 V to 2 V with a step of 0.2 at frequency of 1 MHz. The measured capacitance includes four capacitances in addition to desired gate to channel capacitance Cgsd, CGS (measured ) = Cgsd + CS + Ctop + Cof + Cif Equation (32) Cs is a parasitic capacitance arising from equipment and test structures; Ctop is due to electric field emerging from top surface of gate electrode ending at drain; Cof and Cif are outer and inner fringing field capacitance associated with the sidewall of the gate and the bottom of the gate to the inner sides of the source and drain regions. In simulation, the effect of parasitic capacitance due to equipment and electrodes are not present, hence the major parasitic capacitance coupled with gate to source/drain capacitance is fringing field capacitance. The extrinsic capacitance or the fringing field capacitance consists of bias independent outer fringing capacitance and a bias dependent inner fringing capacitance. The fringing field capacitance is determined based on compact BSIM 3.33 model [11] Page | 81 Chapter 5 –Electrical Characterization and only outer fringing field capacitance is implemented. It is virtually impossible to separate fringing field capacitance from overlap capacitance. However the fringing field capacitance can be theoretically calculated by [11] : 2εox tpoly CF = ln1+ Equation (33) π Tox where tpoly is the poly thickness. The gate to source and gate to drain capacitance can thus be calculated as [11] : CGSO/CGDO = 0.6 Xj*C ox Equation (34) Based on the above theoretical model with tpoly = 1100 Å and Xj as 58 nm and 70 nm the overlap capacitance is obtained as 9.37E 10 F/m2 and 1.639E 09 F/m 2 for n MOS and p MOS, respectively. The fringing field capacitance is obtained as 1.59E 10 F/m 2 for both n MOS and p MOS as poly thickness was the same for both. The overall capacitance was theoretically found as 1.59E 15 F/ m2 and 1.79E 15 F/ m2 for n MOS and p MOS, respectively. Figure 5.2.4 shows Cgdo for (a) n MOS and (b) p MOS. The simulated results are consistent with theoretically calculated value based on the BSIM 3.33 model [11] . Page | 82 Chapter 5 –Electrical Characterization A B Figure 5.2.4 Gate to drain overlap capacitance obtained from split CV method (a) n MOS (b) p MOS. In the case of p MOS C V curves a kink or a flat plateau is observed in the onset of weak inversion and end of depletion mode. The kink arises from confinement of holes at the strained Si/Strained SiGe heterointerface. Also in the strong inversion region the kink refers to formation of a parasitic conducting channel in the strained Si cap layer. The C V curve results are also in good agreement with results published in [9] [12] [13] . Page | 83 Chapter 5 –Electrical Characterization B) Total Gate Capacitance The total gate capacitance of the strained Si/SiGe MOSFET can be given by the series combination of oxide capacitance and semiconductor capacitance based on a charge thickness capacitance model. The charge thickness model is a charge based model based on DC charge thickness. Figure 5.2.5 [11] describes the charge thickness concept. Figure 5.2.5 Schematic representation of charge thickness model for total gate capacitance [11]. Based on the charge thickness model, Figure 5.2.6 shows (a) the equivalent capacitance circuit model for strained Si/SiGe device, and (b) for a p MOS strained Si/strained SiGe device. Figure 5.2.6 Equivalent gate capacitance model based on charge thickness model for (a) Strained Si/SiGe device (b) Strained Si/SiGe [12]. Page | 84 Chapter 5 –Electrical Characterization Assuming negligible interface charges and capacitance due to interface charges, the net gate capacitance can be expressed as [12] : 1 1 CG = + Equation (35) Cox CS where CS can be represented as parallel combination of depletion capacitance (CD), inversion layer capacitance at the heterointerface ( CTH ) and inversion layer capacitance (CTs ) at the Si/SiO 2 interface. For n MOS the capacitance can simply be taken as the parallel combination of CD and CTs . As the depletion charge and the inversion charge are function of varying gate voltage, the semiconductor capacitance varies for different regions of operation. For the subthreshold region, the charge and the net capacitance can be treated for two different cases of gate voltage: (a) accumulation region ( VG ≥ VFBS ); (b) depletion region (VTHS < VG< VFBS ). In case of accumulation region, the net capacitance is a series combination of oxide capacitance and accumulation capacitance (CA) given as [12]: dQs ψs CA = = CLD 1+ , Equation (36) dψs 2vt where CLD = εs / εsvt / qND / A Equation (37) Cox ψs = (VG −VFBS ) Equation (38) CLD Page | 85 Chapter 5 –Electrical Characterization In case of depletion mode, the bulk semiconductor capacitance is a parallel combination of CD, CLD and Cox , where depletion capacitance is given by [12] : 2 1 (2C ox(VG −VFBS))) CD = 1+ −1 Equation (39) Cox qεsiNa / d However, in the case of highly doped epitaxial layers, due to band confinement and presence of electrons near the hetero interface in case of p MOS the net capacitance is a series combination of CLD and Cox . Thus this results in a kink in the C V characteristics. The C V characteristic for the above threshold region can be divided into two regions of operation for p MOS: (a) VG≤ VTH ; (b) VTS ≥ VG. For case (a) the charge at the Si/SiGe interface is an increasing function of gate voltage, hence the capacitance (CTH ) at the onset of inversion in the strained SiGe layer is a function of gate voltage. Hence in this case the total capacitance is a series combination of CTH and Cox , where CTH can be expressed as [12]: H CTH = −q(dρs / dψs) Equation (40) For case (b) when the gate voltage is equal to the threshold voltage of the strained Si layer, the sheet charge density at Si/SiO 2 interface increases; however, the sheet charge density now in the heterostructure is constant and no longer varies with increase in gate voltage. Hence in this case the net capacitance is a series combination of Cox and CTS where CTS is represented as [12]: Page | 86 Chapter 5 –Electrical Characterization S S CTS = −q(dρs / dψs) = −q(dρs / dVG)(dVG / dψs) Equation (41) Since hole concentration in the buried channel is fixed, dVG /dψs = 0, thus capacitance in this region is same as oxide capacitance. In case of n MOS the capacitance model remains the same as determined for bulk silicon. Figure 5.2.7 shows the total gate capacitance for (a) buried channel strained SiGe p MOS and (b) surface channel n MOS. To validate the C V curve analysis, calculations were made based on the C V model published in [12]. The obtained C V curve shows reasonable agreement with calculated values of capacitance in accumulation (2.4 fF/ m 2, 2 CA=2.5 fF / m ). In strong inversion the obtained gate capacitance is less than the oxide capacitance as theoretically predicted, since there is always some parasitic capacitance present there. However, the threshold value obtained from the C V curve is less than the calculated value obtained from the ID VG curve. At present there seems to be no valid reason for this discrepancy other than some simulation artifacts. Also, as predicted in the model, a kink is observed in the accumulation region and in strong inversion for p MOS due to heavily doped epitaxial layers and shifting of the holes from buried channel to surface channel. Page | 87 Chapter 5 –Electrical Characterization B Figure 5.2.7 Total gate capacitance curves based on charge thickness model obtained from simulation (a) p MOS and (b) n MOS. Page | 88 Chapter 5 –Electrical Characterization Chapter 5: References [1] Silvaco ATLAS Device Simulator Manual V 5.10, Silvaco International CA, Available at www.silvaco.com . [2] Jan et al . "A 65 nm ultra low power logic platform technology using uni axial strained silicon transistor," IDEM Tech Digest , Oct 2005 [3] Jerry G. Fossum et al., " Performance Projection of scaled CMOS devices and circuits with strained Si on SiGe channels", IEEE Trans Electron Devices, Vol 50, No 4, pp 1042 1050, April 2003. [4] B. Bindu et al., “Analytical model of drain current of strained Si/strained Si 1 YGe Y/relaxed Si 1 xGe x NMOSFET and PMOSFET for circuit simulation”, Solid State Electron, 50, pp 448 455, March 2006. [5] B. Bindu et al. , “Analytical model of drain–current of Si/SiGe heterostructure p channel MOSFETs for circuit simulation,” IEEE Trans. Electron Devices , vol. 53, No. 6, pp 1411–1419, Jun. 2006. [6] S. H. Olsen et al. , “Study of strain relaxation in Si/SiGe metal oxide semiconductor field effect transistors,” Journal of Applied Physics 2005, 97 (11), 114504. [7] K. Roy et al. , “Leakage current mechanisms and leakage reduction techniques in deep submicrometer CMOS circuits,” Proceedings of the IEEE, Vol. 91, No. 2, pp. 305 327 February 2003. [8] Shaofeng Yu et al., “Strained –Si strained SiGe dual channel layer structure as CMOS substrate for single work function metal gate technology” IEEE Electron Device Lett., Vol 25, No 6, June 2004, pp 402 405 [9] Yee Chia Yeo et al. , "Enhanced performance in Sub 100 CMOSFETs using strained epitaxial silicon germanium," Department of Electrical Engineering and Computer Sciences, University of California at Berkley, 2000 Available at: http://www.eecs.berkeley.edu/~hu/PUBLICATIONS/Hu_papers/Hu_IEDM/Hu_IEDM00_05.pdf [10] http://courses.ece.uiuc.edu/ece598/gt/Lab%20Practicals/Lab1.pdf [11] BSIM 3 V 3.3 User Manual, Department of Electrical Engineering and Computer Sciences, University of California Berkley. Available at: http://www device.eecs.berkeley.edu/~bsim3 . [12] B. Bindu et al., “A unified model for gate capacitance –voltage characteristics and extraction of parameters of Si/SiGe heterostructure p MOSFET”, IEEE Trans Electron Devices, Vol 54, No 8, pp 1889 1896, Aug 2007. Page | 89 Chapter 5 –Electrical Characterization [13] Sarah H. Olsen et al., “Study of single and dual channel designs for high performance strained –Si SiGe n MOSFETs”, IEEE Trans Electron Devices, Vol 51, No 7, July 2004. Page | 90 Chapter 6 –Conclusion and Future Work Chapter 6: Conclusion and Future Work . 6.1 Summary For more than 30 years, innovative methods in semiconductor engineering and designs have been leading the silicon revolution by doubling the transistor count to beat Moore’s law, while advancing logic technology process, performance per watt, high efficiency and speed. As feature size becomes smaller and smaller, circuits operate at higher speeds, thus increasing challenges to deliver more powerful and power efficient devices. Active power, low off state leakage, concurrent process circuit variability, fundamental limits of materials, and short channel effects must be addressed in order to continue delivering smaller, more powerful and power efficient devices. However, there is no viable alternative for silicon technology to address all these issues. Hence in order to continue leveraging performance out of silicon, capabilities of various innovative materials and circuit design need to be investigated. At present there are a lot of such technologies under research such as silicon on insulator, finfets, strained silicon, high K dielectrics, 3D transistors, III V materials and nanowires. Strained silicon at present with high K dielectrics has appeared to be a solid candidate for all future sub micron technology and has been successfully integrated with silicon technology in the 90 nm node. However, the current strained silicon process technology suffers from issues like conformality of nitride stress layer, stress variation in channel and optical proximity issues. In addition to that, there are no known proper compact models at present for P a g e | 91 Chapter 6 –Conclusion and Future Work strained silicon technology. A lot of other alternative designs have been reported by various research groups and one such alternative design is a dual channel strained Si/strained SiGe architecture. Double channel heterojunction strained Si/strained Si 0.7 Ge 0.30 /relaxed Si 0.85 Ge 0.15 n MOSFET and p MOSFET devices were designed, optimized and simulated for 65 nm logic technology node. I V and C V measurement with quantum effects showed two conducting channels for p MOS: first at the Si/Si 0.7 Ge 0.30 interface in the compressively strained Si 0.7 Ge 0.30 , then at the Si/ONO interface. The devices were designed with differential silicon cap layer for n MOS and p MOS to obtain inversion levels in the desired strain layers with high levels of strain, low electrostatic degradation, and better film conformality. Quantitative simulations were performed to develop and optimize processing technology and to predict device behavior. Low thermal processing, with low time RTA was developed and optimized to maintain a high level of strain and film conformality. Thermal effects on phosphorus and arsenic diffusion profile in strained Si/Strained SiGe layers were investigated and it was observed that phosphorous diffuses more in silicon germanium compared to arsenic. Based on the analysis, source/drain doping and annealing was optimized to yield shallow source/drain junction. Poly gate length and gate oxide thickness were relaxed to ~55 nm and 1.7 nm with ultra shallow junction depth of 38 and 40 nm for n and p channel devices, respectively, with 10 20 cm 3 concentration to mitigate sub threshold and gate leakages . A unified modeling scheme was formulated based on different physics based model. Device simulations, based on P a g e | 92 Chapter 6 –Conclusion and Future Work self consistent solution of the Schrödinger Poisson equation in addition to a density gradient quantum model and band gap narrowing, were performed to analyze the impact of field based transport mechanisms, and overall performance of the devices. The extracted I V measurement showed an improved n MOS and p MOS current of 0.94 mA/ m and 0.45 mA/ m with an overall improvement in performance by 25~30% over published results from Intel’s 65 nm work and other research groups. However, the variance in the simulated results (this work) and Intel’s work can be reduced by effectively tuning the electric field model, proper optimizing the doping levels, and the adjusting the simulation parameters and assumptions. Short channel effects were also investigated and were observed to be controlled with subthreshold swing of 88 mV/dec and 78 mv/dec for p MOS and n MOS. A low DIBL was also observed with 12mV/V and 26mV/V for n MOS and p MOS, respectively. The off state leakage current was higher for this work compared to published work on uniaxial strain silicon by a factor of 10X. The extracted mobility exhibits an increase in both n MOS and p MOS mobility. Quantitative simulation from this work revealed much higher mobility than obtained by experimental work. The variance in the results owed to the factor of unavailability of proper data and fitting for the mobility models in the present work. Further, the results of this work are in accordance with results obtained from the published compact model and slight variance is observed due to different assumptions and fitting parameter used. Thus the key messages from this work can be summarized as P a g e | 93 Chapter 6 –Conclusion and Future Work 1) Process induced strain is the most significant innovation in submicron MOS transistor technology, but scalability is a major bottleneck in driving performance for sub 65 nm technologies. 2) Compound semiconductor material such as SiGe, a promising solution for foreseeable future of MOS transistor technology. 3) Dual channel CMOS transistor technology with a biaxial tensile strained Si and biaxial compressive strained SiGe channel is a promising solution to sustain the scaling challenges. 6.2 Recommendations for Future Work The work done in this investigation has provided some insight into processing, design and working of strained silicon/strain silicon germanium heterostructures. However, several issues were encountered during the investigations which need to be solved in order to continue better development of strained silicon technology. The recommendations for future work are listed below. (A) Effects of strain on lattice and stress relaxation An attempt was made in this work to include the effects of strain using band gap narrowing and density gradient quantum model; however, these models are not sufficient to determine the exact amount of stress in the film. Further, SUPREM 4 does not have any feature to incorporate effects of processing on stress relaxation and misfit dislocation which can lead to error in prediction of device behavior. P a g e | 94 Chapter 6 –Conclusion and Future Work (B) Effects of germanium out –diffusion Germanium out diffusion is a well known issue in silicon germanium process technology. The present model, though, shows some amount of germanium diffusion but due to lack of proper silicon germanium diffusion model and fitting parameters several discrepancies were observed between this work and other simulation work reported. This can have serious implications in predicting device behavior as stress level varies due to impurity. Further, there, is no way we can determine the amount of surface roughness and cross hatching in the device. (C) Field based mobility model The present model for SiGe in ATLAS does not have any unified method for mobility determination. Also the model ignores the effect of germanium concentration and stress dependence of electric field. Both germanium content and electric field levels play significant roles in mobility statistics, hence there is need to develop those models. (D) Reduction of dislocation and issues relating to epi growth of SiGe. This issue needs to be addressed in order to facilitate the success of these devices. Epitaxial growth of silicon germanium is a process challenge and issues relating to stress relaxation, threaded dislocations, and critical thickness of strain cap layers need to be solved by either process optimization or integrating the present technology with SOI. P a g e | 95 Chapter 6 –Conclusion and Future Work (E) Optimization of p MOS silicon cap and high K integration As we have seen, buried channel in p MOS leads to electrostatic degradation and high off state leakage current. Process optimization needs to be made to integrate SiGe channel directly with gate dielectric such as incorporation of high k dielectric. P a g e | 96 Appendix A –Simulation Codes APPENDIX A: SIMULATION CODES Process Simulation ################################################################################################ ######################### STRAINED SILICON PMOS PROCESS SIMULATION###### ################ go athena # Mesh Define line x loc=0.00 spac=0.20 line x loc=0.1 spac=0.3 line x loc=0.2 spac=0.30 line x loc=0.30 spac=0.30 line x loc=0.6 spac=0.02 line x loc=0.7 spac=0.02 line x loc=0.8 spac=0.30 line x loc =1.0 spac=0.30 line x loc=1.1 spac=0.20 line y loc=0.00 spac=0.05 line y loc=1.00 spac=1.0 # Mesh Intialize init silicon c.boron=1.0e15 orientation=100 # Strained Si/Strained SiGe Epitaxial Growth Method MODEL.SIGE Method STRESS.HIST # Graded SiGe deposit silicon thick=0.02 div=10 c.phosphor=1.0e17 c.germanium=1E20 f.germanium=10E21 # Relaxed SiGe deposit silicon thick=0.07 div =10 c.phosphor=4e17 c.germanium =7.5E21 # Strained SiGe deposit silicon thick=0.012 div =10 c.phosphor=4e17 c.germanium=15E21 # Strained Si epitaxy time=10 temp=500 thickness=0.012 c.phosphor=4e17 division= 10 dy=0.1 ydy=0.1 # STI Formation and Controlled Removal of Strained Si layer. diffus time= 20 temp=980 dryo2 press=1.00 hcl.pc=0 deposit nitride thick=0.05 divisions=5 etch nitride start x=0.2 y= 0.21 etch cont x=0.2 y= 0.12639 etch cont x=0.3 y= 0.126391 etch done x=0.3 y= 0.21 etch nitride start x=1.0 y= 0.21 etch cont x=1.0 y= 0.12639 cont x=1.1 y= 0.12639 etch done x=1.1 y= 0.21 etch oxide start x=0.2 y= 0.13 etch cont x=0.2 y= 0.10534 etch cont x=0.3 y= 0.10534 etch done x=0.3 y= 0.13 etch oxide start x=1.0 y= 0.13 etch cont x=1.0 y= 0.10534 etch cont x=1.1 y= 0.10534 etch done x=1.1 y= 0.13 etch silicon start x=0.2 y= 0.10534 P a g e | 97 Appendix A –Simulation Codes etch cont x=0.2 y= 0.03 etch cont x=0.3 y= 0.03 etch done x=0.3 y= 0.10534 etch silicon start x=1.0 y= 0.10534 etch cont x=1.0 y= 0.03 etch cont x=1.1 y= 0.03 etch done x=1.1 y= 0.10534 deposit oxide thick=0.20 divisions = 8 etch material=oxide above p1.y= 0.10534 etch nitride all # PMOS V T Implant Adjust deposit oxide thick=0.003 implant phosphor dose=4e12 energy=10 tilt=0 rotation=0 amorph etch material=oxide above p1.y= 0.10534 # Gate Oxide Deposition OxyNitride method GRID.OXIDE=0.05 GRIDINIT.OX=0.01 rate.depo machine=CVDOXIDE oxynitride n.m sigma.dep=0.20 smooth.win=0.1 \ smooth.step=1 monte1 dep.rate=1 deposit machine = CVDOXIDE TIME = 2 MINUTES struct outfile =GOX.str # Poly Deposition rate.depo machine=LPCVDPOLY polysilicon a.m sigma.dep=0.80 smooth.win=0.1 \ smooth.step=4 monte1 dep.rate=12 deposit machine=LPCVDPOLY time=100 minutes c.boron=4.0e21 divisions=8 dy =0.1 # Gate Stack Pattern deposit photoresist thick=0.040 divisions = 8 etch photoresist left p1.x=0.610 etch photoresist right p1.x=0.675 etch polysilicon left p1.x=0.61 etch polysilicon right p1.x=0.675 etch oxynitride left p1.x=0.610 etch oxynitride right p1.x=0.675 etch photoresist all # Oxide Spacer deposit oxide thick=0.030 division=10 dy=0.1 deposit photoresist thick=1 etch photoresist start x=0.30 y= 1.4 etch cont x=0.3 y= 0.18 etch cont x=0.60 y= 0.18 etch done x=0.60 y= 1.4 etch photoresist start x=0.69 y= 1.4 etch cont x=0.69 y= 0.18 etch cont x=1.02 y= 0.18 etch done x=1.02 y= 1.4 # Source Drain Impant I implant boron dose=6e13 energy= 12 tilt=0 rotation=0 amorph etch photoresist all # Spacer I pattern etch oxide start x=0.0 y= 0.3 etch cont x=0.0 y= 0.10526 etch cont x=0.59 y= 0.10526 etch done x=0.59 y= 0.3 P a g e | 98 Appendix A –Simulation Codes etch oxide start x=0.70 y= 0.3 etch cont x=0.70 y= 0.10526 etch cont x=1.2 y= 0.1026 etch done x=1.2 y= 0.3 # Spacer II Nitride deposit nitride thick=0.050 divisions = 10 # S/D II Mask deposit photoresist thick=1 etch photoresist start x=0.30 y= 1.4 etch cont x=0.3 y= 0.2 etch cont x=0.60 y= 0.2 etch done x=0.60 y= 1.4 etch photoresist start x=0.69 y= 1.4 etch cont x=0.69 y= 0.2 etch cont x=1.02 y= 0.2 etch done x=1.02 y= 1.4 # S/D II Implant implant boron dose=6e15 energy=16 tilt=0 rotation=0 amorph etch photoresist all etch nitride above p1.y= 0.23472 etch nitride left p1.x=0.56 etch nitride right p1.x=0.72 etch oxide above p1.y= 0.23472 # Anneal diffus time=0.20 temp=900 nitro press=1.00 # Silicidation deposit titanium thick=0.1 divisions =9 dy=0.10 ydy=0.10 diffus time=1 temp=450 nitro press=1.00 etch titanium all struct outfile = PMOS_L65.str quit ############################### STRAINED SILICON NMOS PROCESS SIMULATION############### go athena line x loc=0.00 spac=0.2 line x loc=0.1 spac=0.2 line x loc=0.2 spac=0.2 line x loc=0.30 spac=0.2 line x loc=0.6 spac=0.02 line x loc=0.7 spac=0.02 line x loc=0.8 spac=0.2 line x loc =1.0 spac=0.2 line x loc=1.1 spac=0.2 line y loc=0.00 spac=0.1 line y loc=1.00 spac=1.0 # Mesh Intialize init silicon c.boron=1.0e15 orientation=100 Method MODEL.SIGE Method STRESS.HIST P a g e | 99 Appendix A –Simulation Codes # Strained Si/Strained SiGe Epitaxy deposit silicon thick=0.02 div=10 c.boron=1.0e17 c.germanium=1E20 f.germanium=7.5E21 deposit silicon thick=0.07 div =10 c.boron=1.0e17 c.germanium =7.5E21 deposit silicon thick=0.012 div =10 c.boron=1.0e17 c.germanium=15E21 epitaxy time=10 temp=500 thickness=0.025 c.boron=1.0e15 division= 10 dy=0.1 ydy=0.1 # STI Formation diffus time= 20 temp=1000 dryo2 press=1.00 hcl.pc=0 deposit nitride thick=0.05 divisions=5 struct outfile = nitride_depo_15_30.str etch nitride start x=0.2 y= 0.21 etch cont x=0.2 y= 0.14 etch cont x=0.3 y= 0.14 etch done x=0.3 y= 0.21 etch nitride start x=1.0 y= 0.21 etch cont x=1.0 y= 0.14 etch cont x=1.1 y= 0.14 etch done x=1.1 y= 0.21 etch oxide start x=0.2 y= 0.15 etch cont x=0.2 y= 0.116 etch cont x=0.3 y= 0.116 etch done x=0.3 y= 0.15 etch oxide start x=1.0 y= 0.15 etch cont x=1.0 y= 0.116 etch cont x=1.1 y= 0.116 etch done x=1.1 y= 0.15 etch silicon start x=0.2 y= 0.1164 etch cont x=0.2 y= 0.07 etch cont x=0.3 y= 0.07 etch done x=0.3 y= 0.1164 etch silicon start x=1.0 y= 0.1164 etch cont x=1.0 y= 0.07 etch cont x=1.1 y= 0.07 etch done x=1.1 y= 0.1164 deposit oxide thick=2 divisions =10 etch material=oxide above p1.y= 0.11614 etch nitride all # NMOS V T Adjustment deposit oxide thick=0.01 divisions=8 implant boron dose=3.0e13 energy=16 tilt=0 rotation=0 amorph etch material=oxide above p1.y= 0.11614 # Gate Oxide Deposition OxyNitride method GRID.OXIDE=0.05 GRIDINIT.OX=0.01 rate.depo machine=CVDOXIDE oxynitride n.m sigma.dep=0.20 smooth.win=0.1 \ smooth.step=1 monte1 dep.rate=1.0 deposit machine = CVDOXIDE TIME = 2 # Poly Deposition rate.depo machine=LPCVDPOLY polysilicon a.m sigma.dep=0.80 smooth.win=0.1 \ smooth.step=4 monte1 dep.rate=12 deposit machine = LPCVDPOLY TIME = 100 MINUTES c.phosphor = 1E20 divisions = 8 # Gate Stack Pattern deposit photoresist thick=0.040 divisions = 8 P a g e | 100 Appendix A –Simulation Codes etch photoresist left p1.x=0.610 etch photoresist right p1.x=0.680 etch polysilicon left p1.x=0.610 etch polysilicon right p1.x=0.680 etch oxynitride right p1.x=0.680 etch oxynitride left p1.x=0.610 etch photoresist all # Oxide Spacer deposit oxide thick=0.028 divisions=5 # S/D1 Mask deposit photoresist thick=1 etch photoresist start x=0.30 y= 1.4 etch cont x=0.3 y= 0.146 etch cont x=0.60 y= 0.146 etch done x=0.60 y= 1.4 etch photoresist start x=0.69 y= 1.4 etch cont x=0.69 y= 0.146 etch cont x=1.0 y= 0.146 etch done x=1.0 y= 1.4 # S/D Implant I implant arsenic dose=5e16 energy= 22 tilt=0 rotation=0 amorph # Oxide Spacer Pattern etch photoresist all etch oxide start x=0.0 y= 0.28 etch cont x=0.0 y= 0.1162 etch cont x=0.59 y= 0.1162 etch done x=0.59 y= 0.28 etch oxide start x=0.70 y= 0.28 etch cont x=0.70 y= 0.1162 etch cont x=1.2 y= 0.1162 etch done x=1.2 y= 0.28 # Spacer II Nitride deposit nitride thick=0.040 divisions = 8 # S/DII Mask deposit photoresist thick=1 etch photoresist start x=0.30 y= 1.4 etch cont x=0.3 y= 0.156 etch cont x=0.59 y= 0.156 etch done x=0.59 y= 1.4 etch photoresist start x=0.68 y= 1.4 etch cont x=0.68 y= 0.156 etch cont x=1.0 y= 0.156 etch done x=1.0 y= 1.4 #S/D Implant II implant phosphor dose=3e14 energy=18 tilt=0 rotation=0 amorph # Spacer II Pattern etch photoresist all etch nitride above p1.y= 0.2458 etch oxide above p1.y= 0.2458 etch nitride left p1.x=0.57 etch nitride right p1.x=0.72 P a g e | 101 Appendix A –Simulation Codes # Anneal diffus time=0.25 temp=900 nitro press=1.00 # Silicidation deposit titanium thick=0.007 divisions=10 dy=0.10 ydy=0.10 diffus time=0.40 temp=450 nitro press=1.00 etch titanium all struct outfile = Titanium_silicidation_15_30.str quit Device Simulations ############################################ NMOS IDS- VD CURVE ############################ # DEFINE ELECTRODE go athena init infile = Titanium_silicidation_15_30.str electrode name=Source x=0.42 y= 0.1164 electrode name=Gate x=0.647 y= 0.2496 electrode name=Drain x=0.84 y= 0.1146 electrode name=Substrate x=0.04 y= 0.1164 struct outfile = NMOS_DEVICE_15_30.str #### DEVICE SIMULATOR BEGINS go atlas init infile = NMOS_DEVICE_15_30.str # SET FLAGS FOR MOBILITY MODELS models boltzman bgn ccsmob consrh fldmob DGLOG print temperature=300 # METHOD OF SOLUTION method newton gummel climit = 60 # define the Gate workfunction contact name=gate n.poly Solve QFACTOR=0.0 Solve QFACTOR=0.0001 Solve QFACTOR=0.001 Solve QFACTOR=0.01 Solve QFACTOR=0.1 Solve QFACTOR=1.0 # set gate biases with Vds=0.0 solve init solve vgate=0.0 outf=solve_ntmp0 solve vgate=0.2 outf=solve_ntmp2 solve vgate=0.4 outf=solve_ntmp4 solve vgate=0.6 outf=solve_ntmp6 solve vgate=0.8 outf=solve_ntmp8 solve vgate=1.0 outf=solve_ntmp1 solve vgate=1.2 outf=solve_ntmp12 #load in temporary files and ramp Vds load infile=solve_ntmp0 log outf=NIDSAT_00_15_30.log solve name=drain vdrain=0 vfinal=2.0 vstep=0.1 P a g e | 102 Appendix A –Simulation Codes load infile=solve_ntmp2 log outf=NIDSAT_0.2_15_30.log solve name=drain vdrain=0 vfinal=2.0 vstep=0.1 load infile=solve_ntmp4 log outf=NIDSAT_0.4_15_30.log solve name=drain vdrain=0 vfinal=2.0 vstep=0.1 load infile=solve_ntmp6 log outf=NIDSAT_0.6_15_30.log solve name=drain vdrain=0 vfinal=2.0 vstep=0.1 load infile=solve_ntmp8 log outf=NIDSAT_0.8_15_30.log solve name=drain vdrain=0 vfinal=2.0 vstep=0.1 load infile=solve_ntmp1 log outf=NIDSAT_1.1_15_30.log solve name=drain vdrain=0 vfinal=2.0 vstep=0.1 load infile=solve_ntmp12 log outf=NIDSAT_1.2_15_30.log solve name=drain vdrain=0 vfinal=2.0 vstep=0.1 extract name="nidsmax" max(i."drain") extract name="nsat_slope" slope(minslope(curve(v."drain",i."drain"))) extract max current and saturation slope output e.field j.electron j.hole j.conduc j.total e.velocity h.velocity \ ex.field ey.field flowlines e.mobility h.mobility qss e.temp h.temp \ charge val.band con.band qfn qfp j.disp photogen impact tot.doping save outf=SS_900_15_15_30.str qui ##################################### PMOS IDS- VD CURVE ##################################### #### DEVICE SIMULATOR BEGINS ##### go atlas init infile = PMOS_L65.str # SET FLAGS FOR MOBILITY MODELS ##################### models boltzman bgn ccsmob fldmob DGLOG print temperature=300 # METHOD OF SOLUTION method newton climit = 60 # define the Gate workfunction contact name=gate p.poly # set gate biases with Vds=0.0 solve init solve vgate=0 outf=solve_ntmp0 solve vgate= 0.2 outf=solve_ntmp02 solve vgate= 0.4 outf=solve_ntmp04 solve vgate= 0.6 outf=solve_ntmp06 solve vgate= 0.8 outf=solve_ntmp1 P a g e | 103 Appendix A –Simulation Codes solve vgate= 1.0 outf=solve_ntmp2 solve vgate= 1.2 outf=solve_ntmp3 # load in temporary files and ramp Vds load infile=solve_ntmp00 log outf=PIDSAT_0.0_15_30.log solve name=drain vdrain=0 vfinal= 2.0 vstep= 0.1 output e.field j.electron j.hole j.conduc j.total e.velocity h.velocity \ex.field ey.field flowlines e.mobility h.mobility qss e.temp h.temp \ charge val.band con.band qfn qfp j.disp photogen impact tot.doping save outf=flatband.str load infile=solve_ntmp02 log outf=PIDSAT_0.2_15_30.log solve name=drain vdrain=0 vfinal= 2.0 vstep= 0.1 load infile=solve_ntmp04 log outf=PIDSAT_0.415_30.log solve name=drain vdrain=0 vfinal= 2.0 vstep= 0.1 output e.field j.electron j.hole j.conduc j.total e.velocity h.velocity \ex.field ey.field flowlines e.mobility h.mobility qss e.temp h.temp \ charge val.band con.band qfn qfp j.disp photogen impact tot.doping save outf=weakinv.str load infile=solve_ntmp06 log outf=PIDSAT_0.6_15_30.log solve name=drain vdrain=0 vfinal= 2.0 vstep= 0.1 load infile=solve_ntmp1 log outf=PIDSAT_0.8_15_30.log solve name=drain vdrain=0 vfinal= 2.0 vstep= 0.1 load infile=solve_ntmp2 log outf=PIDSAT_1.0_15_30.log solve name=drain vdrain=0 vfinal= 2.0 vstep= 0.1 load infile=solve_ntmp3 log outf=PIDSAT_1.2_15_30.log solve name=drain vdrain=0 vfinal= 2.0 vstep= 0.1 extract name="Pidsmax" max(i."drain") extract name="Psat_slope" slope(minslope(curve(v."drain",i."drain"))) extract max current and saturation slope tonyplot overlay PIDSAT_0.8_15_30.log PIDSAT_1.0_15_30.log PIDSAT_1.2_15_30.log PIDSAT_0.6_15_30.log PIDSAT_0.415_30.log PIDSAT_0.2_15_30.log output e.field j.electron j.hole j.conduc j.total e.velocity h.velocity \ex.field ey.field flowlines e.mobility h.mobility qss e.temp h.temp \charge val.band con.band qfn qfp j.disp photogen impact tot.doping save outf=strong.str # quit P a g e | 104 Appendix B –Material Parameters APPENDIX B: Material Parameters Used in Simulation Default Material Properties of Si and SiGe as specified in ATLAS Manual Table B1 : Band Parameters for Silicon and Polysilicon Table B2: Static dielectric constant for silicon and polysilicon Table B3: Lattice mobility model (Low Field Mobility) for Si and polysilicon Table B4 : Band Gap Narrowing Parameters P a g e | 105 Appendix B –Material Parameters Table B5: Material Parameter for SiGe ( x=0.3) P a g e | 106