Strained-Silicon Transistors with Silicon-Carbon Source/Drain H-1-2

Home , Strained silicon

Extended Abstracts of the 2006 International Conference on Solid State Devices and Materials, Yokohama, 2006, pp. 162-163

H-1-2 (Invited)

Strained-Silicon Transistors with Silicon-Carbon Source/Drain Yee-Chia Yeo Department of Electrical and Computer Engineering, National University of Singapore (NUS), Singapore 117576. Phone: +65 6516 2298 Fax : +65 6779 1103 E-mail: [email protected]

1. Introduction feasible. SEM images of transistors with selectively grown New materials and device structures are being actively ex- Si1-yCy S/D show achievement of excellent epi selectivity on planar plored to extend the performance limits of CMOS transistors. A and FinFET devices [5],[8]. For FinFET devices, the spacers by the higher carrier mobility achieves a higher drive current IDsat for a fin sidewall need to be removed, so that the Si1-yCy stressor wraps given supply voltage VDD and off-state leakage current Ioff, and around the fin on the top and sidewall surfaces, forming a Π-shape, reduces power consumption for a given speed performance. In for maximum strain benefits (Fig. 5). assessing various CMOS performance enhancement options, manufacturability, cost of implementation, and performance bene- 4. Strain Engineering and Electrical Performance fits are important considerations. Schemes that allow simple and Si1-yCy S/D can be integrated with other stressors, including cost-effective integration with current manufacturing process, and the tensile-stress SiN liner. The combination of Si1-yCy S/D and which offer superior performance improvement are preferred, e.g. tensile-stress SiN liner on planar 50 nm gate length SOI n-FETs process-strained-Si or local strained-Si [1]-[3]. To improve elec- and on 25 nm gate length tri-gate FinFETs have been recently re- ported [5],[8]. Fig. 6 plots the Ioff-Ion data for control FinFETs tron mobility in n-FETs, tensile strain εxx along the [110] channel direction is desired. with raised Si S/D, strained-FinFETs with Si0.99C0.01 S/D, and In this paper, we examine the enhancement of n-FET per- strained FinFETs with Si0.99C0.01 S/D and tensile-stress SiN liner. For devices with matched Ioff, Vth, subthreshold swing, and DIBL, formance using silicon-carbon (Si1-yCy) source and drain (S/D) stressors. Selective epitaxy of silicon-carbon, and its integration Si0.99C0.01 S/D contributes to a 20% increase in IDsat. By using in a fabrication process will be discussed. High performance multiple stressors, up to 56% IDsat enhancement was observed. levels can be achieved by combining the strain effects due to mul- Fig. 7 plots the IDS-VDS characteristics for planar SOI n-FETs tiple stressors with optimum surface and channel orientations. obtained from DC and pulse measurements. These devices have a width of 1.1 µm. In the narrow width regime, reduction in IDsat 2. Strain Effects due to Silicon-Carbon enhancement was observed, and is attributed to the interaction Fig. 1 shows the lattice property of Si1-yCy. In the relaxed between S/D stressor and isolation stress. By comparing n-FETs state, the lattice constant of Si1-yCy aSiC,relaxed is smaller than that of with Si0.99C0.01 S/D with control transistors at the same gate length, Si aSi. When Si1-yCy is pseudomorphically grown on Si, the ∆IDsat/IDsat and ∆IDlin/IDlin were obtained. Fig. 8 plots ∆IDsat/IDsat Si1-yCy lattice is stretched horizontally and compressed vertically and ∆IDlin/IDlin for devices with various gate lengths LG. The IDsat [Fig. 2(a)]. Therefore, the lattice constant aSiC⊥ in the perpen- and IDlin enhancement increases with decreasing LG. Integration dicular or growth direction is reduced further, as given by aSiC⊥ = of Si1-yCy S/D with tensile-stress SiN liner leads to even higher IDsat (aSiC,relaxed – aSi)·(1 + 2C12/C11) + aSi. Fig. 2(b) shows the XRD data or IDlin enhancement. obtained from Si1-yCy/Si [5]. In a transistor with Si1-yCy S/D, the Fig. 9 compares IDsat enhancement for n-FETs with various small vertical lattice parameter aSiC⊥ interacts with the adjacent Si channel orientations. The conventional channel orientation [110] lattice [Fig. 2(c)], leading to a lateral tensile strain in Si that ex- is assigned 0º, and the [010] direction is equivalent to 45º. Since tends towards the channel region. The maximum magnitude of the piezoresistance coefficient is orientation dependent, IDsat en- the lateral strain induced in Si near the edges of the channel can be hancement shows a similar orientation dependence. Lateral ten- larger than the lattice mismatch between the relaxed Si and Si1-yCy sile stress is the most effective in the [010] channel orientation, materials. The distribution of strain components was calculated consistent with the piezoresistance effect. Very significant in- using finite element simulation [6]. Fig. 3 shows that the lateral crease in IDsat can therefore be achieved if stress effects of multiple strain component εxx, i.e. the change in lattice parameter in the stressors are combined with the use of an optimum channel orien- horizontal direction, is positive (tensile) in the Si channel. εxx is tation where the stress sensitivity is the highest. more tensile nearer to the Si surface. The vertical strain εzz pro- 5. Summary file reflects the vertical compression of the Si lattice near the ver- Silicon-carbon S1-yCy S/D is a promising technology option tical heterojunction. Both tensile εxx and compressive εzz contrib- for pushing the performance limits of n-channel bulk, SOI, or ute to increased electron mobility. Furthermore, the electron FinFET devices. Its combination with other stressors and opti- inversion layer in an n-FET is formed near the surface where the mum channel orientation could realize very high n-FET drive cur- magnitudes of εxx and εzz also tend to be the largest. rent for high performance logic applications. 3. Selective Epitaxy and Process Integration Acknowledgments. The author acknowledges research grant from the Nanoelectronics Research Program, A*STAR, Singapore, and discussions Si1-yCy S/D was grown using an ultra-high-vacuum chemical vapor deposition (UHVCVD) system. A carbon concentration of with students (K.-W. Ang, T.-Y. Liow, K.-J. Chui, G. Wang, K.-M. Tan, R. about 1–1.3% was used [7]-[8], although higher carbon concentra- T.-P. Lee, E.-H. Toh, H.-C. Chin), collaborators G. Samudra (NUS), N. Balasubramanian (IME), Y.-L. Foo (IMRE). tions may also be employed. The insertion of Si1-yCy S/D is an additional technology option for n-FET performance improvement References at the 32 nm technology node and beyond. Fig. 4 illustrates a [1] S. Ito et al., IEDM 2002, pp. 247. [2] C.-H. Ge et al., IEDM 2003, pp. 73. process flow that forms Si1-yCy S/D for planar or FinFET devices. After gate stack and spacer formation, a S/D recess etch is per- [3] T. Ghani et al., IEDM 2003, pp. 978. [4] M. Berti et al., APL 72, pp. 1602, 1998. formed prior to the selective epitaxy of Si1-yCy S/D. A hard mask [5] K.-W. Ang et al., VLSI Symp. 2006, pp. 80. covered the gate during selective epitaxy. The process integration [6] Y.-C. Yeo et al., APL 83, 023103, 2005. is simple and highly manufacturable. CMOS process integration [7] K.-W. Ang et al., IEDM 2004, pp. 1069. of n-FETs with Si1-yCy S/D and p-FETs with Si1-xGex S/D is also [8] T.-Y. Liow et al., VLSI Symp. 2006, pp. 68.

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109 5.44 (a) Relaxed SiC Epitaxial SiC (b) 8 (004) Rocking Curve

) 10 aSi aSiC,relaxed on Silicon SiC Peak c 7 aSiC e Si substrate 0.0 s 10 )

5.43 /

s 6 ) t

% 10 n (

Å Relaxed Lattice

5 u i ( 5.42 -0.2 Si0.99C0.01 o

10 S c

Constant a C (004)

a 4 i SiC,relaxed (

S 10

Si Peak y t a 3 m 5.41 i -0.4 s aSi 10 o t n

r 2 e n f

t 10

5.40 n C

t 1

-0.6 i I s S Silicon 10

a 0

o 10

5.39 f -0.8 34.4 34.6 34.8 35.0 o C Expt. Data o

Bragg Angle ( ) e n (c) n-FET

c 5.38 Heterojunction o i i

t -1.0 Gate t t Lattice Constant a a 5.37 i Gate v L in Growth

-1.2 e Direction a 5.36 SiC, D SiC SiC -1.4 Tensile SiC/Si 5.35 Strain 0.00 0.01 0.02 Hetero- Si SiC Carbon Mole Fraction y Si junction Lattice Lattice

Fig. 1. Lattice constants of relaxed Si1-yCy alloy Fig. 2. (a) Schematic of relaxed Si1-yCy and epitaxial Si1-yCy on Si. Epitaxial Si1-yCy is under aSiC,relaxed, and epitaxial Si1-yCy on Si in the growth lateral tensile strain and vertical compressive strain. (b) Reciprocal space map and HRXRD data direction aSiC⊥. Expt. data is from [4]. from [5]. (c) Si C S/D induces lateral tensile strain in the n-FET channel. 1-y y ε ε Lateral Strain Component xx Vertical Strain Component zz Planar FET Strained -Si Stra ined-Si Active/Fin Definition 0 0.60 0.20 0 -0.30 -0.30-0.15 0.25 0.50 -0.25 -0.25 0.40 0.30 0.40 0.25 -0.20 -0.20 Si1-yCy 0.30 0.35 Well and VT Implants ) -5 0.35 0.30 ) -5 SiC -0.15 -0.10 -0.15 SiC 0.25 m SiC m -0.20 Gate Stack Formation n -10 0.20 SiC n -10 S D ( ( -0.05

z 0.15 z S/D Ext./Spacer Formation

S D -15 0.30 -15 h h 0.10 t t 0 p -20 p -20 Recess Etch (Optional), e e -0.20 0.05 -0.20 0.10 FinFET 0.05 Selective Si1-yCy Epitaxy D -0.15 -0.15 D 0.05 -25 -0.10 0 -0.10 -25 -0.05 -0.05 0.05 S/D Formation -30 -30 -20 -10 0 10 20 30 40 50 60 70 -20 -10 0 10 20 30 40 50 60 70 Passivation, Contact, Metallization Si C Horizontal Distance x (nm) Horizontal Distance x (nm) 1-y y Fig. 3. Simulated lateral strain εxx (left) and vertical strain εzz (right) components in a Fig. 4. Process flow (left), and SEM images of planar transistor with Si0.99C0.01 S/D regions. The S/D stressor separation is 50 nm. In the in- n-FET with Si1-yCy S/D and FinFET with Si1-yCy S/D. version layer, i.e. near the surface, εxx is tensile (positive), and εzz is compressive (negative).

10-3 FinFET: SiC S/D + SiN Liner

Si1-yCy High-Stress High-Stress V

FinFET: SiC S/D -4 0 Source SiN Liner SiN Liner 10 Control FinFET =

G -5

V 10 Si1-yCy

@ -6

Si1-yCy Stressor ) 10

Drain m µ µ µ µ -7 Si Fin / 10 A

Si fin (

f Spacer f -8 o

I 10 Gate o -9 θ = 45 SiO 10 2 SiO2 200 300 400 Si Si I (µA/µm) @ V = 1.2 V Dsat GS Fig. 5. A n-channel strained multiple-gate transistor or FinFET with Si1-yCy S/D and Fig. 6. Ioff-Ion plot for control FinFETs, strained-FinFETs tensile-stress SiN liner. The Si1-yCy S/D wraps around the Si fin to form a Π-shaped with Si0.99C0.01 S/D, and strained FinFETs with Si0.99C0.01 structure [8]. S/D and tensile-stress SiN liner [8].

0.8 0.8 ) SiC S/D (Pulse) SiC S/D + Tensile SiN Liner SiC S/D + Tensile SiN Liner 0.7 0.8 m Control (Pulse)

µ µ SiC S/D only µ µ V -V = 1.0 V SiC S/D only / SiC S/D (DC) GS T t A 0.6 t a a

Control (DC) s 0.6 s m 0.6 ( D D

S 0.5 I I / D / t t I L = 80 nm

G a a

t s

0.4

n 0.4

D [010] 0.4 D

e W = 1.1 µm I I r [110] r ∆ ∆ ∆ ∆ ∆ ∆ 0.3 ∆ ∆ u C 0.2 0.2 0.2 n i L = 50 nm a G

r n-FET 0.1 (001) Surface n-FET D 0.0 0.0 0.0 0.0 0.5 1.0 1.5 0 15 30 45 60 75 0.0 0.2 0.4 0.6 0.8 1.0 o Drain Voltage V (V) ∆I /I Channel Orientation ( ) DS Dlin Dlin Fig. 7. IDS-VDS of planar n-FET with Si0.99C0.01 Fig. 8. Significant enhancement in IDsat can be Fig. 9. Larger IDsat enhancement can be obtained S/D. Pulse measurement corrected for achieved by combining the strain effects of for n-FETs with the [010] channel orientation due self-heating effects. Si1-yCy S/D and tensile-stress SiN liner. to the higher sensitivity to strain.