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Gate oxide
Designing a Nanoelectronic Circuit to Control a Millimeter-Scale Walking Robot
Advanced MOSFET Structures and Processes for Sub-7 Nm CMOS Technologies
Outline MOS Gate Dielectrics Incorporation of N Or F at the Si/Sio
Gate Oxide Reliability: Physical and Computational Models
Microelectronic Device Fabrication I Physics 445/545 Integration
Overview of Nanoelectronic Devices
Effect of Oxide Layer in Metal-Oxide-Semiconductor Systems
Nano-Electro-Mechanical (NEM) Relay Devices and Technology for Ultra-Low Energy Digital Integrated Circuits
Electrical Characterisation of III-V Nanowire Mosfets
A Self-Aligned Gate Definition Process with Submicron Gaps
Self-Aligned-Gate Gallium Oxide Metal-Oxide-Semiconductor Transistors
The Field Effect Transistor
Nanoelectronics, Nanophotonics, and Nanomagnetics Report of the National Nanotechnology Initiative Workshop February 11–13, 2004, Arlington, VA
Fatigue Mechanisms in Al-Based Metallizations in Power Mosfets Roberta Ruffilli
Device-Level Predictive Modeling of Extreme Electromagnetic Interference
The Manufacturing Process
Neuron MOS Binary-Logic Integrated Circuits. II. Simplifying
Investigating 50Nm Channel Length Mosfets Containing a Dielectric
Top View
The Relentless March of the MOSFET Gate Oxide Thickness to Zero G
Impact of Nitrogen Profile in Gate Nitrided-Oxide on Deep-Submicron CMOS Performance and Reliability
Needs and Opportunities for Nanotribology in Mems and Nems R.W
What Everyone Needs to Know About Carbon-Based Nanocircuits`
Nanowire Transistor Performance Limits and Applications Wei Lu, Member, IEEE, Ping Xie, and Charles M
Nano-Electro-Mechanical Switch (Nems) for Ultra
Molecular-Scale Electronics: from Concept to Function
A Guideline for Material Design of Gate Oxide in Further Scaled MOSFET ~Improvement of Electrical Properties by Ceo2/La2o3 Stack
Transparent Oxide Semiconductor Gate Based Mosfets for Sensor Applications
Reliability Analysis and Improvement of Nanoscale CMOS Digital Circuits
Gate Oxide Breakdown Presentation
Nanoscale CMOS
Is Negative Capacitance FET a Steep-Slope Logic Switch?
The Electronic Structure at the Atomic Scale of Ultrathin Gate Oxides
Compact and Explicit Physical Model for Lateral Metal-Oxide-Semiconductor Field-Effect Transistor with Nanoelectromechanical
Optimization of the Process for Semiconductor Device Fabrication in the Micron 636 Whittemore Cleanroom Facility Masters of Scie
Moletronics II
Section 9 ROM, EPROM, & EEPROM
Manufacturing Design and Fabrication of 100 Nm (Leff) CMOS Devices
A Review of Oxide Breakdown
Future Challenges and Needs for Nano- Electronics from Manufacturing View Point
Integration of Metallic Source/Drain Contacts in MOSFET Technology
Fabrication and Characterization of Gate Last Si Mosfets with Sige Source and Drain
Thin Dielectrics for MOS Gate
Self-Aligned Polysilicon Gate Metal-Oxide-Semiconductor Field Effect Transistor for Large Area Electronics
Challenges for Nanoscale Mosfets and Emerging Nanoelectronics
Future of Integrated Circuits: a Survey of Nano-Electronics
Designing in Mosfets for Safe and Reliable Gate-Drive Operation Rev
Role of High-K Gate Dielectrics and Metal Gate Electrodes in Emerging Nanoelectronic Devices
Metal Oxide Semiconductor Field Effect Transistors - MOSFETS
Investigating 50Nm Channel Length Mosfets Containing a Dielectric Pocket, in a Circuit Environment
Vmos) for Smart Sensors and Extension to a Novel Neu-Gaas (Vgaas) Paradigm (Invited)
Compact and Explicit Physical Model for Lateral MOSFET with NEMS Based Resonant Gate V2
Self-Aligned Top-Gate Metal-Oxide Thin-Film Transistors Using a Solution-Processed Polymer Gate Dielectric