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Electrical Characterisation of III-V Nanowire Mosfets Electrical Characterisation of III-V Nanowire MOSFETs Hellenbrand, Markus 2020 Document Version: Publisher's PDF, also known as Version of record Link to publication Citation for published version (APA): Hellenbrand, M. (2020). Electrical Characterisation of III-V Nanowire MOSFETs. Department of Electrical and Information Technology, Lund University. Total number of authors: 1 General rights Unless other specific re-use rights are stated the following general rights apply: Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights. • Users may download and print one copy of any publication from the public portal for the purpose of private study or research. • You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal Read more about Creative commons licenses: https://creativecommons.org/licenses/ Take down policy If you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately and investigate your claim. LUND UNIVERSITY PO Box 117 221 00 Lund +46 46-222 00 00 Electrical Characterisation of III-V Nanowire MOSFETs MARKUS HELLENBRAND DEPARTMENT OF ELECTRICAL AND INFORMATION TECHNOLOGY | FACULTY OF ENGINEERING | LTH | LUND UNIVERSITY Electrical Characterisation of III-V Nanowire MOSFETs Doctoral Thesis Markus Hellenbrand Department of Electrical and Information Technology Lund, May 2020 Academic thesis for the degree of Doctor of Philosophy, which, by due permission of the Faculty of Engi- neering at Lund University, will be publicly defended on Friday, 12 June, 2020, at 9:15 a.m. in lecture hall E:1406, Department of Electrical and Information Technology, Ole Römers Väg 3, 223 63 Lund, Sweden. The thesis will be defended in English. The Faculty Opponent will be Professor Tibor Grasser, TU Wien, Austria. Organisation: Document Type: LUND UNIVERSITY DOCTORAL THESIS Department of Electrical and Information Technology Date of Issue: Ole Römers Väg 3 May 2020 223 63 Lund Sweden Sponsoring Organisation(s): Swedish Foundation for Strategic Research (SSF) Author: Swedish Research Council (VR) Markus Hellenbrand European Union (EU) Title: Electrical Characterisation of III-V Nanowire MOSFETs Abstract: The ever increasing demand for faster and more energy-efficient electrical computation and communication presents severe challenges for the semiconductor industry and particularly for the metal-oxide-semiconductor field-effect transistor (MOSFET), which is the workhorse of modern electronics. III-V materials exhibit higher carrier mobilities than the most commonly used MOSFET material Si so that the realisation of III-V MOSFETs can enable higher operation speeds and lower drive voltages than that which is possible in Si electronics. A lowering of the transistor drive voltage can be further facilitated by employing gate-all-around nanowire geometries or novel operation principles. However, III-V materials bring about their own challenges related to material quality and to the quality of the gate oxide on top of a III-V MOSFET channel. This thesis presents detailed electrical characterisations of two types of (vertical) III-V nanowire transistors: MOSFETs based on conventional thermionic emission; and Tunnel FETs, which utilise quantum-mechanical tunnelling instead to control the device current and reach inverse subthreshold slopes below the thermal limit of 60 mV/decade. Transistor characterisations span over fourteen orders of magnitude in frequency/time constants and temperatures from 11 K to 370 K. The first part of the thesis focusses on the characterisation of electrically active material defects (‘traps’) related to the gate 18 20 3 1 stack. Low-frequency noise measurements yielded border trap densities of 10 to 10 cm− eV− and hysteresis measurements yielded effective trap densities – projected to the oxide/semiconductor interface – of 2 1012 to 3 1013 cm 2 eV 1. Random × × − − telegraph noise measurements revealed that individual oxide traps can locally shift the channel energy bands by a few meV and that such defects can be located at energies from inside the semiconductor band gap all the way into the conduction band. Small-signal radio frequency (RF) measurements revealed that parts of the wide oxide trap distribution can still interact with carriers in the MOSFET channel at gigahertz frequencies. This causes frequency hystereses in the small-signal transconductance and capacitances and can decrease the RF gains by a few decibels. A comprehensive small-signal model was developed, which takes into account these dispersions, and the model was applied to guide improvements of the physical structure of vertical RF MOSFETs. This resulted in values for the cutoff frequency fT and the maximum oscillation frequency fmax of about 150 GHz in vertical III-V nanowire MOSFETs. Bias temperature instability measurements and the integration of (lateral) III-V nanowire MOSFETs in a back end of line process were carried out as complements to the main focus of this thesis. The results of this thesis provide a broad perspective of the properties of gate oxide traps and of the RF performance of III-V nanowire transistors and can act as guidelines for further improvement and finally the integration of III-V nanowire MOSFETs in circuits. Keywords: MOSFET, TFET, III-V, Nanowire, Hysteresis, Low-Frequency Noise, Random Telegraph Noise, cryogenic, Reliability, Radio Frequency, Small-Signal Model. Classification System and/or Index Terms Language: Electronic Engineering, Nano Technology English Supplementary Bibliographical Information: ISBN (printed): – 978-91-7895-519-0 Key title and ISSN: ISBN (digital): Series of Licentiate and Doctoral Theses; 1654-790X, No. 130 978-91-7895-520-6 Recipient’s Notes: Number of Pages: Price: 156 Security Classification: Unclassified General Permissions: I, the undersigned, being the copyright owner and author of the above-mentioned thesis and its abstract, hereby grant to all reference sources permission to publish and disseminate said abstract. Signature: Date: 11 May 2020 Electrical Characterisation of III-V Nanowire MOSFETs Doctoral Thesis Markus Hellenbrand Department of Electrical and Information Technology Lund, May 2020 Markus Hellenbrand Department of Electrical and Information Technology Lund University Ole Römers Väg 3, 223 63 Lund, Sweden Series of Licentiate and Doctoral Theses ISSN 1654-790X, No. 130 ISBN 978-91-7895-519-0 (printed) ISBN 978-91-7895-520-6 (digital) c 2020 Markus Hellenbrand This thesis is typeset using LATEX 2# with the body text in Palatino and Goudy Initials, headings in Helvetica, text in figures in Arial, and the body text in Appendix B in Computer Modern. Frontispiece: Micrograph of a transistor sample with probe tips in contact. Printed by Tryckeriet i E-huset, Lund University, Lund, Sweden. No part of this thesis may be reproduced or transmitted in any form or by any means without written permission from the author. Distribution of the original thesis in full, however, is permitted without restriction. “The Road goes ever on and on Down from the door where it began. Now far ahead the Road has gone, And I must follow, if I can, Pursuing it with weary feet, Until it joins some larger way, Where many paths and errands meet. And whither then? I cannot say.” The Fellowship of the Ring, J. R. R. Tolkien iii Abstract he ever increasing demand for faster and more energy-efficient elec- trical computation and communication presents severe challenges Tfor the semiconductor industry and particularly for the metal-oxide- semiconductor field-effect transistor (MOSFET), which is the workhorse of modern electronics. III-V materials exhibit higher carrier mobilities than the most commonly used MOSFET material Si so that the realisation of III- V MOSFETs can enable higher operation speeds and lower drive voltages than that which is possible in Si electronics. A lowering of the transistor drive voltage can be further facilitated by employing gate-all-around nanowire geometries or novel operation principles. However, III-V materials bring about their own challenges related to material quality and to the quality of the gate oxide on top of a III-V MOSFET channel. This thesis presents detailed electrical characterisations of two types of (ver- tical) III-V nanowire transistors: MOSFETs based on conventional thermionic emission; and Tunnel FETs, which utilise quantum-mechanical tunnelling instead to control the device current and reach inverse subthreshold slopes below the thermal limit of 60 mV/decade. Transistor characterisations span over fourteen orders of magnitude in frequency/time constants and tempera- tures from 11 K to 370 K. The first part of the thesis focusses on the characterisation of electrically active material defects (‘traps’) related to the gate stack. Low-frequency noise 18 20 3 1 measurements yielded border trap densities of 10 to 10 cm− eV− and hysteresis measurements yielded effective trap densities – projected to the oxide/semiconductor interface – of 2 1012 to 3 1013 cm 2 eV 1. Random × × − − v telegraph noise measurements revealed that individual oxide traps can locally shift the channel energy bands by a few millielectronvolts and that such defects can be located at energies
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